diff options
| author | Robert Hancock <[email protected]> | 2019-06-18 09:47:15 -0600 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2019-07-30 10:20:06 +0200 |
| commit | a0549f7390d33ec522de3a53e6031189d46a9ce7 (patch) | |
| tree | e42231be4b5524faf75ebe717c7d7a0ffd9a39ab /include | |
| parent | 3372081cfd25e2afaaa043d9da78f7de1cf84636 (diff) | |
fpga: virtex2: Add additional clock cycles after DONE assertion
Some Xilinx FPGA configuration options can result in the startup
sequence extending past the end of the FPGA bitstream. Continue applying
CCLK clock cycles for 8 cycles after DONE is asserted in order to ensure
the startup sequence is complete, as recommended by Xilinx.
Signed-off-by: Robert Hancock <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions