diff options
| author | Marek Vasut <[email protected]> | 2025-06-30 02:10:29 +0200 |
|---|---|---|
| committer | Patrice Chotard <[email protected]> | 2025-07-29 17:02:31 +0200 |
| commit | a36e87127a39734bff1896a4fa5bdab546bce6f4 (patch) | |
| tree | 84a5ec2fbc796d2d341e103d1b4c89ee18fb8b11 /include | |
| parent | b87ebbe87c05cf5759c5ca93f3749089fdcc4a20 (diff) | |
ARM: stm32: Limit early cache enablement in SPL to STM32MP15xx
The STM32MP13xx SRAM size is half that the SRAM size on STM32MP15xx,
disable early dcache start on STM32MP13xx as the TLB itself takes
about a quarter of the SPL size. The dcache will be enabled later,
once DRAM is available and TLB can be placed in DRAM.
Reviewed-by: Patrice Chotard <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions