diff options
| author | Christian Marangi <[email protected]> | 2024-08-03 10:43:24 +0200 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-08-19 16:15:26 -0600 |
| commit | a776493f4b4b51515db456e635709a93e256dacd (patch) | |
| tree | 60e59679c43a4e54ab01040f9db15ba27fef74c6 /include | |
| parent | a942c0c3f5d454241cf2c1d61d06a42dcd6a14cc (diff) | |
clk: mediatek: mt7622: add missing clock PERI_UART4_PD
Add missing clock PERI_UART4_PD for peri clock gates. This is needed to
match upstream linux clk ID in preparation for OF_UPSTREAM.
Also convert infracfg to mux + gate implementation as now we have mux on
top of gates.
Signed-off-by: Christian Marangi <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/dt-bindings/clock/mt7622-clk.h | 25 |
1 files changed, 13 insertions, 12 deletions
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h index 0820fab0a22..4b6501c1020 100644 --- a/include/dt-bindings/clock/mt7622-clk.h +++ b/include/dt-bindings/clock/mt7622-clk.h @@ -146,18 +146,19 @@ #define CLK_PERI_UART1_PD 13 #define CLK_PERI_UART2_PD 14 #define CLK_PERI_UART3_PD 15 -#define CLK_PERI_BTIF_PD 16 -#define CLK_PERI_I2C0_PD 17 -#define CLK_PERI_I2C1_PD 18 -#define CLK_PERI_I2C2_PD 19 -#define CLK_PERI_SPI1_PD 20 -#define CLK_PERI_AUXADC_PD 21 -#define CLK_PERI_SPI0_PD 22 -#define CLK_PERI_SNFI_PD 23 -#define CLK_PERI_NFI_PD 24 -#define CLK_PERI_NFIECC_PD 25 -#define CLK_PERI_FLASH_PD 26 -#define CLK_PERI_IRTX_PD 27 +#define CLK_PERI_UART4_PD 16 +#define CLK_PERI_BTIF_PD 17 +#define CLK_PERI_I2C0_PD 18 +#define CLK_PERI_I2C1_PD 19 +#define CLK_PERI_I2C2_PD 20 +#define CLK_PERI_SPI1_PD 21 +#define CLK_PERI_AUXADC_PD 22 +#define CLK_PERI_SPI0_PD 23 +#define CLK_PERI_SNFI_PD 24 +#define CLK_PERI_NFI_PD 25 +#define CLK_PERI_NFIECC_PD 26 +#define CLK_PERI_FLASH_PD 27 +#define CLK_PERI_IRTX_PD 28 /* APMIXEDSYS */ |