Merge patch series "clk: mediatek: mt7622: clk migration for OF_UPSTREAM"

Christian Marangi <[email protected]> says:

These are all the required patches to migrate clk and correctly support
OF_UPSTREAM. This will align the clk index to upstream to support the same
clk implementation with downstream and upstream DTS.

1 files changed, 37 insertions, 31 deletions

diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
index 76fcaff0e42..cdbcaef76eb 100644
--- a/include/dt-bindings/clock/mt7622-clk.h
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -117,46 +117,51 @@
 #define CLK_TOP_I2S1_MCK_DIV_PD		104
 #define CLK_TOP_I2S2_MCK_DIV_PD		105
 #define CLK_TOP_I2S3_MCK_DIV_PD		106
+#define CLK_TOP_A1SYS_HP_DIV_PD		107
+#define CLK_TOP_A2SYS_HP_DIV_PD		108
 
 /* INFRACFG */
 
-#define CLK_INFRA_DBGCLK_PD		0
-#define CLK_INFRA_TRNG			1
+#define CLK_INFRA_MUX1_SEL		0
+#define CLK_INFRA_DBGCLK_PD		1
 #define CLK_INFRA_AUDIO_PD		2
 #define CLK_INFRA_IRRX_PD		3
 #define CLK_INFRA_APXGPT_PD		4
 #define CLK_INFRA_PMIC_PD		5
+#define CLK_INFRA_TRNG			6
 
 /* PERICFG */
 
-#define CLK_PERI_THERM_PD		0
-#define CLK_PERI_PWM1_PD		1
-#define CLK_PERI_PWM2_PD		2
-#define CLK_PERI_PWM3_PD		3
-#define CLK_PERI_PWM4_PD		4
-#define CLK_PERI_PWM5_PD		5
-#define CLK_PERI_PWM6_PD		6
-#define CLK_PERI_PWM7_PD		7
-#define CLK_PERI_PWM_PD			8
-#define CLK_PERI_AP_DMA_PD		9
-#define CLK_PERI_MSDC30_0_PD		10
-#define CLK_PERI_MSDC30_1_PD		11
-#define CLK_PERI_UART0_PD		12
-#define CLK_PERI_UART1_PD		13
-#define CLK_PERI_UART2_PD		14
-#define CLK_PERI_UART3_PD		15
-#define CLK_PERI_BTIF_PD		16
-#define CLK_PERI_I2C0_PD		17
-#define CLK_PERI_I2C1_PD		18
-#define CLK_PERI_I2C2_PD		19
-#define CLK_PERI_SPI1_PD		20
-#define CLK_PERI_AUXADC_PD		21
-#define CLK_PERI_SPI0_PD		22
-#define CLK_PERI_SNFI_PD		23
-#define CLK_PERI_NFI_PD			24
-#define CLK_PERI_NFIECC_PD		25
-#define CLK_PERI_FLASH_PD		26
-#define CLK_PERI_IRTX_PD		27
+#define CLK_PERIBUS_SEL			0
+#define CLK_PERI_THERM_PD		1
+#define CLK_PERI_PWM1_PD		2
+#define CLK_PERI_PWM2_PD		3
+#define CLK_PERI_PWM3_PD		4
+#define CLK_PERI_PWM4_PD		5
+#define CLK_PERI_PWM5_PD		6
+#define CLK_PERI_PWM6_PD		7
+#define CLK_PERI_PWM7_PD		8
+#define CLK_PERI_PWM_PD			9
+#define CLK_PERI_AP_DMA_PD		10
+#define CLK_PERI_MSDC30_0_PD		11
+#define CLK_PERI_MSDC30_1_PD		12
+#define CLK_PERI_UART0_PD		13
+#define CLK_PERI_UART1_PD		14
+#define CLK_PERI_UART2_PD		15
+#define CLK_PERI_UART3_PD		16
+#define CLK_PERI_UART4_PD		17
+#define CLK_PERI_BTIF_PD		18
+#define CLK_PERI_I2C0_PD		19
+#define CLK_PERI_I2C1_PD		20
+#define CLK_PERI_I2C2_PD		21
+#define CLK_PERI_SPI1_PD		22
+#define CLK_PERI_AUXADC_PD		23
+#define CLK_PERI_SPI0_PD		24
+#define CLK_PERI_SNFI_PD		25
+#define CLK_PERI_NFI_PD			26
+#define CLK_PERI_NFIECC_PD		27
+#define CLK_PERI_FLASH_PD		28
+#define CLK_PERI_IRTX_PD		29
 
 /* APMIXEDSYS */
 
@@ -169,6 +174,7 @@
 #define CLK_APMIXED_AUD2PLL		6
 #define CLK_APMIXED_TRGPLL		7
 #define CLK_APMIXED_SGMIPLL		8
+#define CLK_APMIXED_MAIN_CORE_EN	9
 
 /* AUDIOSYS */
 
@@ -206,7 +212,7 @@
 #define CLK_AUDIO_DLMCH			31
 #define CLK_AUDIO_ARB1			32
 #define CLK_AUDIO_AWB			33
-#define CLK_AUDIO_AWB3			34
+#define CLK_AUDIO_AWB2			34
 #define CLK_AUDIO_DAI			35
 #define CLK_AUDIO_MOD			36
 #define CLK_AUDIO_ASRCI3		37