clk: mediatek: fix parent rate lookup for fixed PLL clocks

The refactoring in commit 00d0ff7f81bf ("clk: mediatek: refactor parent
rate lookup functions") introduced a regression where fixed PLL clocks
using mtk_clk_fixed_pll_ops are not properly recognized as valid parents
in the CLK_PARENT_APMIXED case.

Fixed PLL clocks are implemented using mtk_clk_fixed_pll_ops instead of
mtk_clk_apmixedsys_ops, but they can also serve as parent clocks in the
APMIXED domain. The parent lookup function needs to check for both
driver ops to properly resolve the parent clock device.

Add mtk_clk_fixed_pll_ops checks alongside mtk_clk_apmixedsys_ops checks
in mtk_find_parent_rate() to restore support for fixed PLL parent clocks.

Fixes: 00d0ff7f81bf ("clk: mediatek: refactor parent rate lookup functions")
Signed-off-by: Sam Shih <[email protected]>
Signed-off-by: Weijie Gao <[email protected]>
Link: https://patch.msgid.link/923e50db696d910803828cd26b0ca0fbbfe11570.1776326933.git.weijie.gao@mediatek.com
Signed-off-by: David Lechner <[email protected]>

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