Merge https://source.denx.de/u-boot/custodians/u-boot-riscv

3 files changed, 69 insertions, 0 deletions

diff --git a/include/configs/openpiton-riscv64.h b/include/configs/openpiton-riscv64.h
new file mode 100644
index 00000000000..42c64f3ca5e
--- /dev/null
+++ b/include/configs/openpiton-riscv64.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ * Copyright (c) 2021 Tianrui Wei
+ *
+ * Authors:
+ *   Anup Patel <[email protected]>
+ *   Tianrui Wei <[email protected]>
+ */
+
+#ifndef __OPENPITON_RISCV64_CONFIG_H
+#define __OPENPITON_RISCV64_CONFIG_H
+
+#include <linux/sizes.h>
+
+/* Environment options */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR     (CONFIG_SYS_SDRAM_BASE + SZ_32M)
+#define CONFIG_SYS_LOAD_ADDR        0x87000000
+#define CONFIG_SYS_MALLOC_LEN       SZ_256M
+#define CONFIG_SYS_BOOTM_LEN        SZ_256M
+
+#ifdef CONFIG_SPL
+#define CONFIG_SPL_MAX_SIZE     0x00100000
+#define CONFIG_SPL_BSS_START_ADDR   0x82000000
+#define CONFIG_SPL_BSS_MAX_SIZE     0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
+		CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE  0x0100000
+#define CONFIG_SPL_STACK    (0x80000000 + 0x04000000 - \
+		GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "boot/fw_payload.bin"
+#define CONFIG_SPL_GD_ADDR 0x85000000
+#endif
+
+/* -------------------------------------------------
+ * Environment
+ */
+//Disable persistent environment variable storage
+#define CONFIG_ENV_IS_NOWHERE   1
+
+/* ---------------------------------------------------------------------
+ * Board boot configuration
+ */
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_addr_r=0x86000000\0" \
+	"kernel_addr_r=0x80200000\0" \
+	"image=boot/Image\0" \
+	"mmcdev=0\0" \
+	"mmcpart=1\0"
+
+#define CONFIG_USE_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND \
+	"fdt addr ${fdtcontroladdr}; " \
+	"fdt move ${fdtcontroladdr} ${fdt_addr_r}; " \
+	"load mmc ${mmcdev}:${mmcpart} ${kernel_addr_r} ${image}; " \
+	"booti ${kernel_addr_r} - ${fdt_addr_r}; "
+
+#endif/* __CONFIG_H */
diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h
index 0d69d1c5482..b6c29f8c604 100644
--- a/include/configs/sifive-unleashed.h
+++ b/include/configs/sifive-unleashed.h
@@ -75,6 +75,7 @@
 	"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
 	"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
 	"partitions=" PARTS_DEFAULT "\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	BOOTENV \
 	BOOTENV_SF
 
diff --git a/include/configs/sifive-unmatched.h b/include/configs/sifive-unmatched.h
index 4fad69bb199..d63a5f62fbc 100644
--- a/include/configs/sifive-unmatched.h
+++ b/include/configs/sifive-unmatched.h
@@ -73,6 +73,7 @@
 	"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
 	"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
 	"partitions=" PARTS_DEFAULT "\0" \
+	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
 	BOOTENV
 
 #define CONFIG_PREBOOT \
@@ -80,4 +81,10 @@
 	"fdt addr ${fdtcontroladdr};"
 #endif /* CONFIG_SPL_BUILD */
 
+#define CONFIG_SYS_EEPROM_BUS_NUM		0
+#define CONFIG_SYS_I2C_EEPROM_ADDR		0x54
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		0x1
+
+#define CONFIG_ID_EEPROM
+
 #endif /* __SIFIVE_UNMATCHED_H */