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authorTom Rini <[email protected]>2022-10-28 20:27:01 -0400
committerTom Rini <[email protected]>2022-11-10 09:45:54 -0500
commitb85d75951fe126267a29bc953ed59ed64a152288 (patch)
tree507941c6838a68351caac0b8d5a052ef281bdbe6 /include
parent22a2283f2de687b30ca257a4b3834f7686fabb56 (diff)
powerpc: Migrate SYS_L3_SIZE to Kconfig
Introduce three options, one for each observed L3 cache size, and have the size select'd as needed. Signed-off-by: Tom Rini <[email protected]> Reviewed-by: Simon Glass <[email protected]>
Diffstat (limited to 'include')
-rw-r--r--include/configs/P2041RDB.h2
-rw-r--r--include/configs/T102xRDB.h1
-rw-r--r--include/configs/T104xRDB.h1
-rw-r--r--include/configs/T208xQDS.h1
-rw-r--r--include/configs/T208xRDB.h1
-rw-r--r--include/configs/T4240RDB.h1
-rw-r--r--include/configs/kmcent2.h1
7 files changed, 0 insertions, 8 deletions
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index f4027ed01a2..874910f24e3 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -59,8 +59,6 @@
#else
#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
#endif
-#define CONFIG_SYS_L3_SIZE (1024 << 10)
-#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_DCSRBAR 0xf0000000
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 27bc387814a..72b98c5f27f 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -104,7 +104,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (256 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#ifdef CONFIG_PHYS_64BIT
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index d91a13f8afd..f8c905404d5 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -78,7 +78,6 @@
* (CONFIG_SYS_INIT_L3_VADDR) will be different.
*/
#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE 256 << 10
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index 5d5d6346fa6..8d3b49655ac 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -76,7 +76,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 407350c25c3..86c92de50e9 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -71,7 +71,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index c8875c809c3..05c4406b770 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -52,7 +52,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE (512 << 10)
#define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000
diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h
index 3def0016474..e5cc62ebdc2 100644
--- a/include/configs/kmcent2.h
+++ b/include/configs/kmcent2.h
@@ -154,7 +154,6 @@
* Config the L3 Cache as L3 SRAM
*/
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
-#define CONFIG_SYS_L3_SIZE 256 << 10
#define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull