diff options
| author | Shaohui Xie <[email protected]> | 2011-09-13 17:51:39 +0800 |
|---|---|---|
| committer | Kumar Gala <[email protected]> | 2011-10-03 08:29:54 -0500 |
| commit | ba50fee6ae7e626bb2eda9d28403d7d3950f407a (patch) | |
| tree | 7a6bd82233c3f92e547ba4a0e87170c57ffaa908 /include | |
| parent | d4b9106609a67617d8cef3bb6bce124974865388 (diff) | |
powerpc/p2041rdb: update cpld reset command according to CPLD 2.0
CPLD 2.0 provides a new register which bit[0] is set to '1' will reset
board with initializing the CPLD registers to default values. And add
bit[6] of register at offset 0x5 to use to enable flash bank selection.
Signed-off-by: Shaohui Xie <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions