diff options
| author | Tom Rini <[email protected]> | 2023-07-12 13:10:04 -0400 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2023-07-12 13:10:04 -0400 |
| commit | bf5152d0108683bbaabf9d7a7988f61649fc33f4 (patch) | |
| tree | a5c78fa71f1045f3503a2217cccb7474e95290ac /include | |
| parent | 8e21064cb3452950b09301baec06d86e37342471 (diff) | |
| parent | 478fedfda42ea2a444991de1696fa0adc8bb16d4 (diff) | |
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-riscv
- Add ethernet driver for StarFive JH7110 SoC
- Add ACLINT mtimer and mswi devices support
- Add Lichee PI 4A board
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/qemu-riscv.h | 2 | ||||
| -rw-r--r-- | include/configs/sifive-unleashed.h | 2 | ||||
| -rw-r--r-- | include/configs/starfive-visionfive2.h | 1 | ||||
| -rw-r--r-- | include/configs/th1520_lpi4a.h | 22 |
4 files changed, 25 insertions, 2 deletions
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h index 20135f569eb..f6d326bda0d 100644 --- a/include/configs/qemu-riscv.h +++ b/include/configs/qemu-riscv.h @@ -11,8 +11,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 1000000 - #define RISCV_SMODE_TIMER_FREQ 1000000 /* Environment options */ diff --git a/include/configs/sifive-unleashed.h b/include/configs/sifive-unleashed.h index de3a0dcdd59..f208f5e20db 100644 --- a/include/configs/sifive-unleashed.h +++ b/include/configs/sifive-unleashed.h @@ -14,8 +14,8 @@ #define CFG_SYS_SDRAM_BASE 0x80000000 #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 1000000 - #define RISCV_SMODE_TIMER_FREQ 1000000 /* Environment options */ diff --git a/include/configs/starfive-visionfive2.h b/include/configs/starfive-visionfive2.h index 93dcc22d366..4ee02b8420f 100644 --- a/include/configs/starfive-visionfive2.h +++ b/include/configs/starfive-visionfive2.h @@ -9,6 +9,7 @@ #define _STARFIVE_VISIONFIVE2_H #define RISCV_MMODE_TIMERBASE 0x2000000 +#define RISCV_MMODE_TIMEROFF 0xbff8 #define RISCV_MMODE_TIMER_FREQ 4000000 #define RISCV_SMODE_TIMER_FREQ 4000000 diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h new file mode 100644 index 00000000000..87496a52c4c --- /dev/null +++ b/include/configs/th1520_lpi4a.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2023 Yixun Lan <[email protected]> + * + */ + +#ifndef __TH1520_LPI4A_H +#define __TH1520_LPI4A_H + +#include <linux/sizes.h> + +#define CFG_SYS_SDRAM_BASE 0x00000000 + +#define UART_BASE 0xffe7014000 +#define UART_REG_WIDTH 32 + +/* Environment options */ + +#define CFG_EXTRA_ENV_SETTINGS \ + "PS1=[LPi4A]# \0" + +#endif /* __TH1520_LPI4A_H */ |