diff options
| author | Martyn Welch <[email protected]> | 2022-10-25 10:55:02 +0100 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2022-11-08 17:34:47 +0100 |
| commit | c8f3402ad294b0dd9484e22d338040aa89bae2cf (patch) | |
| tree | 0edd28baea2a577a806ff7d72cc9172225fa087b /include | |
| parent | e0554577598adf3b559d0a8b705e4078ef9fba17 (diff) | |
arm: imx8mp: Initial MSC SM2S iMX8MP support
Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction
with the MSC SM2-MB-EP1 Mini-ITX Carrier Board.
Signed-off-by: Martyn Welch <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/msc_sm2s_imx8mp.h | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/include/configs/msc_sm2s_imx8mp.h b/include/configs/msc_sm2s_imx8mp.h new file mode 100644 index 00000000000..59ab7329fad --- /dev/null +++ b/include/configs/msc_sm2s_imx8mp.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Based on vendor support provided by AVNET Embedded + * + * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH + * Copyright 2021 General Electric Company + * Copyright 2021 Collabora Ltd. + */ + +#ifndef __MSC_SM2S_IMX8MP_H +#define __MSC_SM2S_IMX8MP_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +#if defined(CONFIG_CMD_NET) +#define CONFIG_FEC_MXC_PHYADDR 1 +#define PHY_ANEG_TIMEOUT 20000 +#endif + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 2) + +#include <config_distro_bootcmd.h> +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc1,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ + +/* Link Definitions */ + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */ +#define PHYS_SDRAM_2 0xc0000000 +#define PHYS_SDRAM_2_SIZE 0x0 + +#define CONFIG_MXC_UART_BASE UART2_BASE_ADDR + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#endif |