diff options
| author | Felix Radensky <[email protected]> | 2010-06-28 01:57:39 +0300 |
|---|---|---|
| committer | Wolfgang Denk <[email protected]> | 2010-06-29 23:03:23 +0200 |
| commit | c987f4753b0afadb38acd7e61df7ba11e8a0203f (patch) | |
| tree | 319f90bd75fcc28742fb6b76b5bb30dfc3316709 /include | |
| parent | d3bee08332fbc9cc5b6dc22ecd34050a85d44d0a (diff) | |
tsec: Fix eTSEC2 link problem on P2020RDB
On P2020RDB eTSEC2 is connected to Vitesse VSC8221 PHY via SGMII.
Current TBI PHY settings for SGMII mode cause link problems on
this platform, link never comes up.
Fix this by making TBI PHY settings configurable and add a working
configuration for P2020RDB.
Signed-off-by: Felix Radensky <[email protected]>
Acked-by: Andy Fleming <[email protected]>
Acked-by: Peter Tyser <[email protected]>
Tested-by: Peter Tyser <[email protected]>
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/P1_P2_RDB.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 125911f2f85..b8917307897 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -425,6 +425,15 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ETHPRIME "eTSEC1" #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +/* TBI PHY configuration for SGMII mode */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_ANEG_ENABLE \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + #endif /* CONFIG_TSEC_ENET */ /* |