diff options
| author | Tom Rini <[email protected]> | 2026-01-28 08:39:52 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-01-28 08:39:52 -0600 |
| commit | cd4f4f74213aa02df1a0f2c533cd2cabfac6aa2e (patch) | |
| tree | afd975b1faab29828f8fdf73eb0aa063a7025fa4 /include | |
| parent | 4234f4d432bf1dcd30b5fee91c71abc1acae5e75 (diff) | |
| parent | 8e918cbe7a1cb87d0b18df91ed1edec9fff2f941 (diff) | |
Merge tag 'fsl-qoriq-for-2026.04-rc2' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Rename freescale to nxp
- Add CPLD support via IFC to the ls1021a-iot board
- Use scmi_clk_state_in_v2 in sandbox
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/ls1021aiot.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index 971a393817a..59acf00b8e5 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -44,6 +44,40 @@ #define CFG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE +/* CPLD */ + +#define CFG_SYS_CPLD_BASE 0x7fb00000 +#define CPLD_BASE_PHYS CFG_SYS_CPLD_BASE + +#define CFG_SYS_FPGA_CSPR_EXT (0x0) +#define CFG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \ + CSPR_PORT_SIZE_8 | \ + CSPR_MSEL_GPCM | \ + CSPR_V) +#define CFG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024) +#define CFG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \ + CSOR_NOR_NOR_MODE_AVD_NOR | \ + CSOR_NOR_TRHZ_80) + +/* CPLD Timing parameters for IFC GPCM */ +#define CFG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \ + FTIM0_GPCM_TEADC(0xf) | \ + FTIM0_GPCM_TEAHC(0xf)) +#define CFG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \ + FTIM1_GPCM_TRAD(0x3f)) +#define CFG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \ + FTIM2_GPCM_TCH(0xf) | \ + FTIM2_GPCM_TWP(0xff)) +#define CFG_SYS_FPGA_FTIM3 0x0 +#define CFG_SYS_CSPR0_EXT CFG_SYS_FPGA_CSPR_EXT +#define CFG_SYS_CSPR0 CFG_SYS_FPGA_CSPR +#define CFG_SYS_AMASK0 CFG_SYS_FPGA_AMASK +#define CFG_SYS_CSOR0 CFG_SYS_FPGA_CSOR +#define CFG_SYS_CS0_FTIM0 CFG_SYS_FPGA_FTIM0 +#define CFG_SYS_CS0_FTIM1 CFG_SYS_FPGA_FTIM1 +#define CFG_SYS_CS0_FTIM2 CFG_SYS_FPGA_FTIM2 +#define CFG_SYS_CS0_FTIM3 CFG_SYS_FPGA_FTIM3 + /* * Serial Port */ |