diff options
| author | Gabor Juhos <[email protected]> | 2013-06-12 18:02:46 +0200 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2013-07-24 09:51:05 -0400 |
| commit | da84f33b046fe99c5fbb6f7d8f8b03c7333b260d (patch) | |
| tree | cae25d170f59261651ca5ff9f2b6aeb2501f94d2 /include | |
| parent | b1a14c471cb4ea633746e7249e468a86a69f2495 (diff) | |
MIPS: mips32/cache.S: remove superfluous register assignment
The t4 register already holds the cache
line size, and the value of the register
is not changed in mips_init_icache.
Get the cache line size value from t4 for
mips_init_dcache as well and remove the
superfluous assignment of t5 register.
Signed-off-by: Gabor Juhos <[email protected]>
Diffstat (limited to 'include')
0 files changed, 0 insertions, 0 deletions