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authorTom Rini <[email protected]>2023-06-19 16:43:53 -0400
committerTom Rini <[email protected]>2023-06-19 16:43:53 -0400
commitdd9484a828d268f175d7c54400574d47b2e4f9ab (patch)
tree086f83a2501521b19d3c805776d07ca2eeae08c9 /include
parentacfd0ff3cf23506e7de4c4fca1c3b4b713281317 (diff)
parent3e41ebaa467763cfa0957d3a0944bdc960033839 (diff)
Merge branch '2023-06-19-corstone1000-fwu-updates' into next
To quote the author: Now that the nvmxip block driver is merged we can add on top of it the platform code to use GPT and FWU metadata in the Corstone1000. But first, push 2 fixes that are needed to make all this work: - move nvmxip header to include - setup fwu metadata structures as packed (we have a 32bit writer - Secure enclave Cortex-M0 and a 64bit reader host Cortex-A35)
Diffstat (limited to 'include')
-rw-r--r--include/fwu_mdata.h7
-rw-r--r--include/nvmxip.h32
2 files changed, 36 insertions, 3 deletions
diff --git a/include/fwu_mdata.h b/include/fwu_mdata.h
index 8fda4f4ac22..56189e2f40a 100644
--- a/include/fwu_mdata.h
+++ b/include/fwu_mdata.h
@@ -6,6 +6,7 @@
#if !defined _FWU_MDATA_H_
#define _FWU_MDATA_H_
+#include <linux/compiler_attributes.h>
#include <efi.h>
/**
@@ -22,7 +23,7 @@ struct fwu_image_bank_info {
efi_guid_t image_uuid;
uint32_t accepted;
uint32_t reserved;
-};
+} __packed;
/**
* struct fwu_image_entry - information for a particular type of image
@@ -38,7 +39,7 @@ struct fwu_image_entry {
efi_guid_t image_type_uuid;
efi_guid_t location_uuid;
struct fwu_image_bank_info img_bank_info[CONFIG_FWU_NUM_BANKS];
-};
+} __packed;
/**
* struct fwu_mdata - FWU metadata structure for multi-bank updates
@@ -62,6 +63,6 @@ struct fwu_mdata {
uint32_t previous_active_index;
struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK];
-};
+} __packed;
#endif /* _FWU_MDATA_H_ */
diff --git a/include/nvmxip.h b/include/nvmxip.h
new file mode 100644
index 00000000000..f4ef37725d2
--- /dev/null
+++ b/include/nvmxip.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2023 Arm Limited and/or its affiliates <[email protected]>
+ *
+ * Authors:
+ * Abdellatif El Khlifi <[email protected]>
+ */
+
+#ifndef __DRIVER_NVMXIP_H__
+#define __DRIVER_NVMXIP_H__
+
+#include <blk.h>
+
+#define NVMXIP_BLKDRV_NAME "nvmxip-blk"
+#define NVMXIP_BLKDEV_NAME_SZ 20
+
+/**
+ * struct nvmxip_plat - the NVMXIP driver plat
+ *
+ * @phys_base: NVM XIP device base address
+ * @lba_shift: block size shift count
+ * @lba: number of blocks
+ *
+ * The NVMXIP information read from the DT.
+ */
+struct nvmxip_plat {
+ phys_addr_t phys_base;
+ u32 lba_shift;
+ lbaint_t lba;
+};
+
+#endif /* __DRIVER_NVMXIP_H__ */