diff options
| author | Tom Rini <[email protected]> | 2022-07-04 21:30:23 -0400 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2022-07-04 21:30:23 -0400 |
| commit | e1d3e637c78790e18d64733fae913d088c4c3c76 (patch) | |
| tree | a9a9543a30046f8ab8b4fe8020c045610c889e25 /include | |
| parent | 284c1a9b4b91120385c346a1924628a695314905 (diff) | |
| parent | 9167a1c28c2751b97ac48da5384e540e714a752a (diff) | |
Merge tag 'fsl-qoriq-2022-7-3' of https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq into next
Several patches from Pali
- fsl_elbc detection fix
- sort p2020 dts node, drop duplicated node
- p1_p2_rdb_pc board cleanup
- simplify mpc85xx _start_cont jumping code
Diffstat (limited to 'include')
| -rw-r--r-- | include/configs/p1_p2_rdb_pc.h | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 6d417c57fdb..2a24236c111 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -173,7 +173,6 @@ * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable * (early boot only) * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0 - * 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable @@ -280,14 +279,6 @@ #endif /* CPLD config size: 1Mb */ -#define CONFIG_SYS_PMC_BASE 0xff980000 -#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE -#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \ - BR_PS_8 | BR_V) -#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ - OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \ - OR_GPCM_EAD) - /* Vsc7385 switch */ #ifdef CONFIG_VSC7385_ENET #define __VSCFW_ADDR "vscfw_addr=ef000000\0" |