summaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
authorKunihiko Hayashi <[email protected]>2025-09-10 18:23:26 +0900
committerTom Rini <[email protected]>2025-09-19 11:55:29 -0600
commite246e2b65885e6d5fd052ec2acdf2b07a53171f0 (patch)
treeb20e4408497dd40331d55efb34f5bebd1955e11a /include
parentc85b8071e7d3fd333f8a2fdd28083cb5ec3a0645 (diff)
configs: qemu-sbsa: Define GIC register base address
If GICV3 is enabled, GICD_BASE and GICR_BASE are needed at arch/arm/cpu/armv8/start.S. Signed-off-by: Kunihiko Hayashi <[email protected]>
Diffstat (limited to 'include')
-rw-r--r--include/configs/qemu-sbsa.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/configs/qemu-sbsa.h b/include/configs/qemu-sbsa.h
index aff78160e12..669d0fe7c58 100644
--- a/include/configs/qemu-sbsa.h
+++ b/include/configs/qemu-sbsa.h
@@ -86,4 +86,8 @@
#define CFG_SYS_INIT_RAM_ADDR SBSA_MEM_BASE_ADDR
#define CFG_SYS_INIT_RAM_SIZE 0x1000000
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE SBSA_GIC_DIST_BASE_ADDR
+#define GICR_BASE SBSA_GIC_REDIST_BASE_ADDR
+
#endif /* __CONFIG_H */