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authorTom Rini <[email protected]>2025-09-26 11:36:52 -0600
committerTom Rini <[email protected]>2025-09-26 11:36:52 -0600
commitedce3c2905a2a9561d10bdb03e587a93e273758d (patch)
tree0f989cfc4b576121496541d8f62f17c6cbc977b7 /include
parent97f2f941e77cdfb7a0d6c2eae1d2e0cde8192523 (diff)
parent1566f803bff58f472c38e2e34204753529d01136 (diff)
Merge tag 'u-boot-imx-next-20250926' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx into next
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/27737 - Add support for i.MX94 EVK. - Set CONFIG_ETHPRIME to eth0 on phycore-imx93. - Expand the nxp_fspi support to i.MX8QXP/8DXL/8ULP.
Diffstat (limited to 'include')
-rw-r--r--include/configs/imx94_evk.h24
-rw-r--r--include/scmi_nxp_protocols.h55
2 files changed, 79 insertions, 0 deletions
diff --git a/include/configs/imx94_evk.h b/include/configs/imx94_evk.h
new file mode 100644
index 00000000000..f93c3c4e4a8
--- /dev/null
+++ b/include/configs/imx94_evk.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __IMX94_EVK_H
+#define __IMX94_EVK_H
+
+#include <linux/sizes.h>
+#include <linux/stringify.h>
+#include <asm/arch/imx-regs.h>
+
+#define CFG_SYS_INIT_RAM_ADDR 0x90000000
+#define CFG_SYS_INIT_RAM_SIZE 0x200000
+
+#define CFG_SYS_SDRAM_BASE 0x90000000
+#define PHYS_SDRAM 0x90000000
+#define PHYS_SDRAM_SIZE 0x70000000UL /* 2GB - 256MB DDR */
+#define PHYS_SDRAM_2_SIZE 0x180000000 /* 8GB */
+
+/* Using ULP WDOG for reset */
+#define WDOG_BASE_ADDR WDG3_BASE_ADDR
+
+#endif
diff --git a/include/scmi_nxp_protocols.h b/include/scmi_nxp_protocols.h
new file mode 100644
index 00000000000..fe6ecd6a7cf
--- /dev/null
+++ b/include/scmi_nxp_protocols.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef _SCMI_NXP_PROTOCOLS_H
+#define _SCMI_NXP_PROTOCOLS_H
+
+#include <asm/types.h>
+#include <linux/bitops.h>
+
+enum scmi_imx_protocol {
+ SCMI_IMX_PROTOCOL_ID_MISC = 0x84,
+};
+
+#define SCMI_PAYLOAD_LEN 100
+
+#define SCMI_ARRAY(X, Y) ((SCMI_PAYLOAD_LEN - (X)) / sizeof(Y))
+
+#define SCMI_IMX_MISC_RESET_REASON 0xA
+
+struct scmi_imx_misc_reset_reason_in {
+#define MISC_REASON_FLAG_SYSTEM BIT(0)
+ u32 flags;
+};
+
+struct scmi_imx_misc_reset_reason_out {
+ s32 status;
+ /* Boot reason flags */
+#define MISC_BOOT_FLAG_VLD BIT(31)
+#define MISC_BOOT_FLAG_ORG_VLD BIT(28)
+#define MISC_BOOT_FLAG_ORIGIN GENMASK(27, 24)
+#define MISC_BOOT_FLAG_O_SHIFT 24
+#define MISC_BOOT_FLAG_ERR_VLD BIT(23)
+#define MISC_BOOT_FLAG_ERR_ID GENMASK(22, 8)
+#define MISC_BOOT_FLAG_E_SHIFT 8
+#define MISC_BOOT_FLAG_REASON GENMASK(7, 0)
+ u32 bootflags;
+ /* Shutdown reason flags */
+#define MISC_SHUTDOWN_FLAG_VLD BIT(31)
+#define MISC_SHUTDOWN_FLAG_EXT_LEN GENMASK(30, 29)
+#define MISC_SHUTDOWN_FLAG_ORG_VLD BIT(28)
+#define MISC_SHUTDOWN_FLAG_ORIGIN GENMASK(27, 24)
+#define MISC_SHUTDOWN_FLAG_O_SHIFT 24
+#define MISC_SHUTDOWN_FLAG_ERR_VLD BIT(23)
+#define MISC_SHUTDOWN_FLAG_ERR_ID GENMASK(22, 8)
+#define MISC_SHUTDOWN_FLAG_E_SHIFT 8
+#define MISC_SHUTDOWN_FLAG_REASON GENMASK(7, 0)
+ u32 shutdownflags;
+ /* Array of extended info words */
+#define MISC_MAX_EXTINFO SCMI_ARRAY(16, u32)
+ u32 extInfo[MISC_MAX_EXTINFO];
+};
+
+#endif