Merge branch '2022-08-20-enforce-DM_ETH-migration'

Enforce requiring DM_ETH to be enabled for ethernet drivers, as the
migration deadline has well passed. To facilitate this, we remove some
non-migrated platforms and disable networking on a few others. Finally
we remove some of the now-useless non-DM_ETH code in some platforms as a
prerequisite for DM_ETH being set.

8 files changed, 0 insertions, 406 deletions

diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h
deleted file mode 100644
index 42e507bac0b..00000000000
--- a/include/configs/P3041DS.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * P3041 DS board configuration file
- *
- */
-#define CONFIG_SYS_DPAA_RMAN
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
-
-#include "corenet_ds.h"
diff --git a/include/configs/P4080DS.h b/include/configs/P4080DS.h
deleted file mode 100644
index fd558398e4a..00000000000
--- a/include/configs/P4080DS.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * P4080 DS board configuration file
- * Also supports P4040 DS
- */
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-#define CONFIG_SRIO_PCIE_BOOT_MASTER
-#define CONFIG_ICS307_REFCLK_HZ		33333000  /* ICS307 ref clk freq */
-
-#include "corenet_ds.h"
diff --git a/include/configs/P5040DS.h b/include/configs/P5040DS.h
deleted file mode 100644
index c8fc879d2f8..00000000000
--- a/include/configs/P5040DS.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2009-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * P5040 DS board configuration file
- *
- */
-
-#define CONFIG_ICS307_REFCLK_HZ		25000000  /* ICS307 ref clk freq */
-
-#include "corenet_ds.h"
diff --git a/include/configs/armadillo-800eva.h b/include/configs/armadillo-800eva.h
deleted file mode 100644
index da02a96889b..00000000000
--- a/include/configs/armadillo-800eva.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the bonito board
- *
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#ifndef __ARMADILLO_800EVA_H
-#define __ARMADILLO_800EVA_H
-
-#define CONFIG_SH_GPIO_PFC
-
-#include <asm/arch/rmobile.h>
-
-#define BOARD_LATE_INIT
-
-#define CONFIG_TMU_TIMER
-#define CONFIG_SYS_TIMER_COUNTS_DOWN
-#define CONFIG_SYS_TIMER_COUNTER	(TMU_BASE + 0xc)	/* TCNT0 */
-#define CONFIG_SYS_TIMER_RATE		(get_board_sys_clk() / 4)
-
-/* STACK */
-#define STACK_AREA_SIZE				0xC000
-#define LOW_LEVEL_MERAM_STACK	\
-		(SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
-
-/* MEMORY */
-#define ARMADILLO_800EVA_SDRAM_BASE	0x40000000
-#define ARMADILLO_800EVA_SDRAM_SIZE	(512 * 1024 * 1024)
-
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
-
-/* SCIF */
-#define SCIF0_BASE		0xe6c40000
-#define SCIF1_BASE		0xe6c50000
-#define SCIF2_BASE		0xe6c60000
-#define SCIF4_BASE		0xe6c80000
-#define	CONFIG_SCIF_A
-
-#undef	CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_SDRAM_BASE		(ARMADILLO_800EVA_SDRAM_BASE)
-#define CONFIG_SYS_SDRAM_SIZE		(ARMADILLO_800EVA_SDRAM_SIZE)
-
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
-
-/* FLASH */
-#define CONFIG_SYS_FLASH_BASE		0x00000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ (CONFIG_SYS_FLASH_BASE) }
-
-/* ENV setting */
-
-/* SH Ether */
-#define CONFIG_SH_ETHER_USE_PORT	0
-#define CONFIG_SH_ETHER_PHY_ADDR	0x0
-#define CONFIG_SH_ETHER_BASE_ADDR	0xe9a00000
-#define CONFIG_SH_ETHER_SH7734_MII	(0x01)
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-
-#endif	/* __ARMADILLO_800EVA_H */
diff --git a/include/configs/cm_t335.h b/include/configs/cm_t335.h
deleted file mode 100644
index 84b4271c36f..00000000000
--- a/include/configs/cm_t335.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Config file for Compulab CM-T335 board
- *
- * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
- *
- * Author: Ilya Ledvich <[email protected]>
- */
-
-#ifndef __CONFIG_CM_T335_H
-#define __CONFIG_CM_T335_H
-
-#include <configs/ti_am335x_common.h>
-
-#undef CONFIG_MAX_RAM_BANK_SIZE
-#define CONFIG_MAX_RAM_BANK_SIZE	(512 << 20)	/* 512MB */
-
-/* Clock Defines */
-#define V_OSCK				25000000  /* Clock output from T2 */
-#define V_SCLK				(V_OSCK)
-
-#define MMCARGS \
-	"mmcdev=0\0" \
-	"mmcroot=/dev/mmcblk0p2 rw rootwait\0" \
-	"mmcrootfstype=ext4\0" \
-	"mmcargs=setenv bootargs console=${console} " \
-		"root=${mmcroot} " \
-		"rootfstype=${mmcrootfstype}\0" \
-	"mmcboot=echo Booting from mmc ...; " \
-		"run mmcargs; " \
-		"bootm ${loadaddr}\0"
-
-#define NANDARGS \
-	"nandroot=ubi0:rootfs rw\0" \
-	"nandrootfstype=ubifs\0" \
-	"nandargs=setenv bootargs console=${console} " \
-		"root=${nandroot} " \
-		"rootfstype=${nandrootfstype} " \
-		"ubi.mtd=${rootfs_name}\0" \
-	"nandboot=echo Booting from nand ...; " \
-		"run nandargs; " \
-		"nboot ${loadaddr} nand0 900000; " \
-		"bootm ${loadaddr}\0"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"loadaddr=82000000\0" \
-	"console=ttyO0,115200n8\0" \
-	"rootfs_name=rootfs\0" \
-	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
-	"bootscript=echo Running bootscript from mmc ...; " \
-		"source ${loadaddr}\0" \
-	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
-	MMCARGS \
-	NANDARGS
-
-/* Serial console configuration */
-
-/* NS16550 Configuration */
-#define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
-#define CONFIG_SYS_NS16550_COM2		0x48022000	/* UART1 */
-
-/* I2C Configuration */
-
-/* SPL */
-
-/* Network. */
-
-/* NAND support */
-#define CONFIG_SYS_NAND_ECCPOS		{ 2, 3, 4, 5, 6, 7, 8, 9, \
-					 10, 11, 12, 13, 14, 15, 16, 17, \
-					 18, 19, 20, 21, 22, 23, 24, 25, \
-					 26, 27, 28, 29, 30, 31, 32, 33, \
-					 34, 35, 36, 37, 38, 39, 40, 41, \
-					 42, 43, 44, 45, 46, 47, 48, 49, \
-					 50, 51, 52, 53, 54, 55, 56, 57, }
-
-#define CONFIG_SYS_NAND_ECCSIZE		512
-#define CONFIG_SYS_NAND_ECCBYTES	14
-
-#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
-
-/* GPIO pin + bank to pin ID mapping */
-#define GPIO_PIN(_bank, _pin)		((_bank << 5) + _pin)
-
-/* Status LED */
-/* Status LED polarity is inversed, so init it in the "off" state */
-
-/* EEPROM */
-
-/*
- * Enable PCA9555 at I2C0-0x26.
- * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command.
- */
-#define CONFIG_PCA953X
-#define CONFIG_SYS_I2C_PCA953X_ADDR	0x26
-#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x26, 16} }
-
-#endif	/* __CONFIG_CM_T335_H */
diff --git a/include/configs/edminiv2.h b/include/configs/edminiv2.h
deleted file mode 100644
index d2f1cd5d5c8..00000000000
--- a/include/configs/edminiv2.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2010 Albert ARIBAUD <[email protected]>
- *
- * Based on original Kirkwood support which is
- * (C) Copyright 2009
- * Marvell Semiconductor <www.marvell.com>
- * Written-by: Prafulla Wadaskar <[email protected]>
- */
-
-#ifndef _CONFIG_EDMINIV2_H
-#define _CONFIG_EDMINIV2_H
-
-/*
- * SPL
- */
-
-#define CONFIG_SYS_UBOOT_BASE		0xfff90000
-#define CONFIG_SYS_UBOOT_START		0x00800000
-
-/*
- * High Level Configuration Options (easy to change)
- */
-
-#include <asm/arch/orion5x.h>
-/*
- * CLKs configurations
- */
-
-/*
- * Board-specific values for Orion5x MPP low level init:
- * - MPPs 12 to 15 are SATA LEDs (mode 5)
- * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
- *   MPP16 to MPP19, mode 0 for others
- */
-
-#define ORION5X_MPP0_7		0x00000003
-#define ORION5X_MPP8_15		0x55550000
-#define ORION5X_MPP16_23	0x00005555
-
-/*
- * Board-specific values for Orion5x GPIO low level init:
- * - GPIO3 is input (RTC interrupt)
- * - GPIO16 is Power LED control (0 = on, 1 = off)
- * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
- * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
- * - GPIO19 is SATA disk power toggle (toggles on 0-to-1)
- * - GPIO22 is SATA disk power status ()
- * - GPIO23 is supply status for SATA disk ()
- * - GPIO24 is supply control for board (write 1 to power off)
- * Last GPIO is 25, further bits are supposed to be 0.
- * Enable mask has ones for INPUT, 0 for OUTPUT.
- * Default is LED ON, board ON :)
- */
-
-#define ORION5X_GPIO_OUT_ENABLE		0xfef4f0ca
-#define ORION5X_GPIO_OUT_VALUE		0x00000000
-#define ORION5X_GPIO_IN_POLARITY	0x000000d0
-
-/*
- * NS16550 Configuration
- */
-
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
-#define CONFIG_SYS_NS16550_CLK		CONFIG_SYS_TCLK
-#define CONFIG_SYS_NS16550_COM1		ORION5X_UART0_BASE
-
-/*
- * Serial Port configuration
- * The following definitions let you select what serial you want to use
- * for your console driver.
- */
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
-	{ 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
-
-/*
- * FLASH configuration
- */
-
-#define CONFIG_SYS_FLASH_BASE		0xfff80000
-
-/* auto boot */
-
-/*
- * Network
- */
-
-#ifdef CONFIG_CMD_NET
-#define CONFIG_MVGBE_PORTS	{1}		/* enable port 0 only */
-#define CONFIG_SKIP_LOCAL_MAC_RANDOMIZATION	/* don't randomize MAC */
-#define CONFIG_PHY_BASE_ADR	0x8
-#endif
-
-/*
- * IDE
- */
-#ifdef CONFIG_IDE
-#define __io
-/* Data, registers and alternate blocks are at the same offset */
-/* Each 8-bit ATA register is aligned to a 4-bytes address */
-/* A single bus, a single device */
-/* ATA registers base is at SATA controller base */
-/* ATA bus 0 is orion5x port 1 on ED Mini V2 */
-/* end of IDE defines */
-#endif /* CMD_IDE */
-
-/*
- * Common USB/EHCI configuration
- */
-#ifdef CONFIG_CMD_USB
-#define ORION5X_USB20_HOST_PORT_BASE ORION5X_USB20_PORT0_BASE
-#endif /* CONFIG_CMD_USB */
-
-/*
- * I2C related stuff
- */
-#ifdef CONFIG_CMD_I2C
-#define CONFIG_I2C_MVTWSI_BASE0		ORION5X_TWSI_BASE
-#endif
-
-/*
- *  Environment variables configurations
- */
-
-/* Enable command line editing */
-
-/* provide extensive help */
-
-/* additions for new relocation code, must be added to all boards */
-#define CONFIG_SYS_SDRAM_BASE		0
-
-#endif /* _CONFIG_EDMINIV2_H */
diff --git a/include/configs/kzm9g.h b/include/configs/kzm9g.h
deleted file mode 100644
index 602c1c53919..00000000000
--- a/include/configs/kzm9g.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2012 Nobuhiro Iwamatsu <[email protected]>
- * Copyright (C) 2012 Renesas Solutions Corp.
- */
-
-#ifndef __KZM9G_H
-#define __KZM9G_H
-
-#define CONFIG_SH73A0
-
-#include <asm/arch/rmobile.h>
-
-/* MEMORY */
-#define KZM_SDRAM_BASE	(0x40000000)
-#define PHYS_SDRAM		KZM_SDRAM_BASE
-#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)
-
-/* NOR Flash */
-#define KZM_FLASH_BASE	(0x00000000)
-#define CONFIG_SYS_FLASH_BASE		(KZM_FLASH_BASE)
-
-/* prompt */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
-
-/* SCIF */
-
-#undef  CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#define CONFIG_SYS_INIT_RAM_ADDR	(0xE5600000) /* on MERAM */
-#define CONFIG_SYS_INIT_RAM_SIZE	(0x10000)
-#define LOW_LEVEL_MERAM_STACK		(CONFIG_SYS_INIT_RAM_ADDR - 4)
-#define CONFIG_SDRAM_OFFSET_FOR_RT	(16 * 1024 * 1024)
-#define CONFIG_SYS_SDRAM_BASE	(KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
-#define CONFIG_SYS_SDRAM_SIZE	(PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
-
-#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)
-
-#define CONFIG_STANDALONE_LOAD_ADDR	0x41000000
-
-/* FLASH */
-#define FLASH_SECTOR_SIZE	(256 * 1024)	/* 256 KB sectors */
-
-/* Timeout for Flash erase operations (in ms) */
-/* Timeout for Flash write operations (in ms) */
-/* Timeout for Flash set sector lock bit operations (in ms) */
-/* Timeout for Flash clear lock bit operations (in ms) */
-
-/* GPIO / PFC */
-#define CONFIG_SH_GPIO_PFC
-
-/* Clock */
-#define CONFIG_GLOBAL_TIMER
-#define CONFIG_SYS_CPU_CLK	(1196000000)
-#define TMU_CLK_DIVIDER		(4)	/* 4 (default), 16, 64, 256 or 1024 */
-
-#endif /* __KZM9G_H */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index d9a973c13fb..aaf28a346d0 100644
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -285,14 +285,6 @@
 #define TSEC1_PHYIDX			0
 #define TSEC2_PHYIDX			0
 #define TSEC3_PHYIDX			0
-
-#define CONFIG_FSL_SGMII_RISER		1
-#define SGMII_RISER_PHY_OFFSET		0x1b
-
-#ifdef CONFIG_FSL_SGMII_RISER
-#define CONFIG_SYS_TBIPA_VALUE		8
-#endif
-
 #endif
 
 #define CONFIG_PEN_ADDR_BIG_ENDIAN