sun6i: Restrict some register initialization to Allwinner A31 SoC

These days many Allwinner SoCs use clock_sun6i.c, although out of them
only the (original sun6i) A31 has a second MBUS clock register.
Also the requirement for setting up the PRCM PLL_CTLR1 register to provide
the proper voltage seems to be a property of older SoCs only as well.

Restrict the MBUS initialization to this SoC only to avoid writing bogus
values to (undefined) registers in other chips.
I can only verify that the PLL voltage setup is not needed for H3 and
A64, so for now we only spare those two SoCs.

Signed-off-by: Andre Przywara <[email protected]>
Reviewed-by: Alexander Graf <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>

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