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| author | Pierre-Clément Tosi <[email protected]> | 2021-08-27 18:04:10 +0200 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2021-09-23 08:55:06 -0400 |
| commit | 37479e65a353d6d5328092c092c8dc7dbcd4d001 (patch) | |
| tree | 6fcc08d95f57b7523b77b701e892a6e2ec86b12f /lib | |
| parent | f050bfacc54deda3598a99645ec90727742494eb (diff) | |
armv8/cache.S: Triple with single instruction
Replace the current 2-instruction 2-step tripling code by a
corresponding single instruction leveraging ARMv8-A's "flexible second
operand as a register with optional shift". This has the added benefit
(albeit arguably negligible) of reducing the final code size.
Fix the comment as the tripled cache level is placed in x12, not x0.
Signed-off-by: Pierre-Clément Tosi <[email protected]>
Diffstat (limited to 'lib')
0 files changed, 0 insertions, 0 deletions