diff options
| author | Yuri Tikhonov <[email protected]> | 2008-02-21 11:06:07 +0100 |
|---|---|---|
| committer | Wolfgang Denk <[email protected]> | 2008-02-21 11:25:47 +0100 |
| commit | 928d1d77f8623c120d8763e20e1ca58df9c5c4c6 (patch) | |
| tree | be7cd0f2d81a23a36bab87ca4533c6a3ff076b55 /post | |
| parent | b6f29c84c208a091f95a10cbc9852d729659ba20 (diff) | |
Fix CPU POST test failure
The CPU POST test code (run from cpu_post_exec_31()) doesn't follow the
ABI carefully, at least the CR3, CR4, and CR5 fields of CR are clobbered
by it. The gcc-4.2 with its more aggressive optimization exposes this fact.
This patch just saves the CR value before running the test code, so allowing
it to do anything it wants with CR.
Signed-off-by: Dmitry Rakhchev <[email protected]>
Acked-by: Yuri Tikhonov <[email protected]>
--
Diffstat (limited to 'post')
| -rw-r--r-- | post/lib_ppc/asm.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/post/lib_ppc/asm.S b/post/lib_ppc/asm.S index 5e72b3418f5..12791762ba2 100644 --- a/post/lib_ppc/asm.S +++ b/post/lib_ppc/asm.S @@ -308,7 +308,10 @@ cpu_post_exec_31: lwz r3, 0(r4) lwz r4, 0(r5) mr r6, r7 + + mfcr r7 blrl + mtcr r7 lwz r7, 8(r1) stw r3, 0(r7) |