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| author | Tom Rini <[email protected]> | 2026-05-25 09:43:44 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-05-25 09:43:44 -0600 |
| commit | 97208cb762aacb4a63297afa1ec34ef7dc82261a (patch) | |
| tree | 56ec980f6ddaf4e5f3ac2d554043488bc71dbe66 /scripts/Makefile.gcc-plugins | |
| parent | ba932756ca1518a98ead78980c9010f843b5319a (diff) | |
| parent | 8a5989acc6ff1430a2775178d2e6b0b5d4573247 (diff) | |
Merge tag 'xilinx-for-v2026.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.07-rc3
versal/fpga:
- Fix unaligned buffer handling
versal2:
- Fix buffer overflow in SOC name array
Diffstat (limited to 'scripts/Makefile.gcc-plugins')
0 files changed, 0 insertions, 0 deletions