arm: versal2: Map PCIe DBI and config regions when PCIe is enabled

The AMD Versal Gen 2 PCIe host controller places its DBI registers
(0x100000000000, 1 MB) and config space (0x100000100000, 255 MB)
above 1 TB. Without MMU entries covering these ranges, U-Boot faults
when the PCIe driver accesses them.

The two regions are merged into a single entry as these are
contiguous and share identical MMU attributes. Add this
entry under a CONFIG_IS_ENABLED(PCIE_DW_AMD) guard so it is only
included when the PCIe driver is configured. VERSAL2_MEM_MAP_USED is
adjusted from 5 to 6 accordingly, keeping the DRAM bank index correct.

Signed-off-by: Pranav Sanwal <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michal Simek <[email protected]>

0 files changed, 0 insertions, 0 deletions