net: zynq_gem: Clear stale speed bits in NWCFG before setting new ones

Commit ecba4380ad26 ("net: zynq_gem: Update the MDC clock divisor in the
probe function") changed zynq_gem_init() from a direct register write to
a read-modify-write pattern in order to preserve MDC clock divider bits.
However, the old speed selection bits (SPEED100/SPEED1000) are never
cleared before OR-ing in the new value.

When the PHY renegotiates at a different speed between successive calls
to zynq_gem_init() (e.g. link flapping from 1 Gbps to 100 Mbps on a
marginal cable), both SPEED100 and SPEED1000 end up set simultaneously
in NWCFG. This confuses the GEM hardware and no frames are received.

Fix by explicitly clearing both speed bits before merging the new
configuration, so only the currently negotiated speed is ever active.

Fixes: ecba4380ad26 ("net: zynq_gem: Update the MDC clock divisor in the probe function")
Signed-off-by: Rafał Hibner <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]

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