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| author | Tom Rini <[email protected]> | 2026-04-23 07:46:01 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-04-23 07:46:01 -0600 |
| commit | 03fcc16d580342667da61ac87ecb12c4f1995be7 (patch) | |
| tree | 9b7e479dfe8b55d1832f498c16f0e31a87a2a4b7 /scripts/basic | |
| parent | bfe90a308a94caa9d855440683521ff04122ae2a (diff) | |
| parent | 9e0511261221b63458bc0d4cfd08596f5c8840d4 (diff) | |
Merge tag 'xilinx-for-v2026.07-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
AMD/Xilinx/FPGA changes for v2026.07-rc1 v3. The biggest part is new
pcie driver for Versal Gen 2 SOC. Others are small fixes and
adjustments.
versal2:
- Wire PCIe IP
cmd/fpga:
- Fix loadb help text guarding
- Add support for skipping fpga ID check
zynqmp:
- Describe missing devices/IDs
- Fix issue around zu63dr_SE
clk/versal:
- Fix out-of-bounds parent id for DUMMY_PARENT
net/gem:
- Add support for 10GBE
- Clear stale speed bits in NWCFG
net/axi_emac:
- Filter out broadcast and multicast packets
pci:
- Add driver for AMD PCIe IP based on DesignWare core
Diffstat (limited to 'scripts/basic')
0 files changed, 0 insertions, 0 deletions