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authorMichal Simek <[email protected]>2020-11-26 14:25:01 +0100
committerMichal Simek <[email protected]>2021-06-23 09:48:35 +0200
commit767aa16d41a94cfc39acbb796c300e575d4e3d4d (patch)
tree3e2eb58be9839810b1ca2760dfe6082876927c10 /scripts/checkpatch.pl
parent351b9f5f9503c4441c9025162aced5c69025f084 (diff)
ARM: zynq: Rename bus to be align with simple-bus yaml
Rename amba to AXI. Based on Xilinx Zynq TRM (Chapter 5) chip is "AXI point-to-point channels for communicating addresses, data, and response transactions between master and slave clients. This ARM AMBA 3.0..." Issues are reported as: .. amba: $nodename:0: 'amba' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' >From schema: ../github.com/devicetree-org/dt-schema/dtschema/schemas/simple-bus.yaml Similar change has been done for Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/8a4bc80debfbb79c296e76fc1e4c173e62657286.1606397101.git.michal.simek@xilinx.com
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