diff options
| author | Bryan Brattlof <[email protected]> | 2022-06-21 16:36:03 -0500 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2022-07-06 14:30:51 -0400 |
| commit | 10c8bafbc3cd9a6434318b82b64444488b7dd677 (patch) | |
| tree | 8e648ee8a11b64aa1bee55d3cfcc34e3a794367c /scripts/checkstack.pl | |
| parent | fdd08f896bcfc513a4cb7799d0094e4fabc73531 (diff) | |
soc: soc_ti_k3: identify j7200 SR2.0 SoCs
Anytime a new revision of a chip is produced, Texas Instruments
will increment the 4 bit VARIANT section of the CTRLMMR_WKUP_JTAGID
register by one. Typically this will be decoded as SR1.0 -> SR2.0 ...
however a few TI SoCs do not follow this convention.
Rather than defining a revision string array for each SoC, use a
default revision string array for all TI SoCs that continue to follow
the typical 1.0 -> 2.0 revision scheme.
Signed-off-by: Bryan Brattlof <[email protected]>
Diffstat (limited to 'scripts/checkstack.pl')
0 files changed, 0 insertions, 0 deletions