diff options
| author | Fabio Estevam <[email protected]> | 2013-12-03 18:26:13 -0200 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2013-12-17 18:38:42 +0100 |
| commit | 89cfd0f5757413093ad179478b80367d7bd34ecc (patch) | |
| tree | 9d046959fc79a25c3d6fc3172854027bc8a72320 /scripts/checkstack.pl | |
| parent | 502a710f5b54bbb966db4c4516abf5d82f46dd47 (diff) | |
mx6: clock: Fix the calculation of PLL_ENET frequency
According to the mx6 quad reference manual, the DIV_SELECT field of register
CCM_ANALOG_PLL_ENETn has the following meaning:
"Controls the frequency of the ethernet reference clock.
- 00 - 25MHz
- 01 - 50MHz
- 10 - 100MHz
- 11 - 125MHz"
Current logic does not handle the 25MHz case correctly, so fix it.
Signed-off-by: Rabeeh Khoury <[email protected]>
Signed-off-by: Fabio Estevam <[email protected]>
Diffstat (limited to 'scripts/checkstack.pl')
0 files changed, 0 insertions, 0 deletions