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| author | Alif Zakuan Yuslaimi <[email protected]> | 2025-02-18 16:34:50 +0800 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-02-25 10:53:41 -0600 |
| commit | 58ef50ff9af1ac64fbfdc05188e8f053bef811c4 (patch) | |
| tree | 99fc160c852eac97a538530149068d9d7ba04d18 /scripts/cleanpatch | |
| parent | 9e7986e0610d4131592c5885aa669e607298e739 (diff) | |
drivers: clk: agilex5: Set PLL to asynchronous mode
PLL frequency would overshoot from the original target in
synchronous mode during low VCC voltage condition.
To resolve this issue, PLL is set to run on asynchronous mode
instead of enabling synchronous mode in the clock driver.
Signed-off-by: Muhammad Hazim Izzat Zamri <[email protected]>
Signed-off-by: Alif Zakuan Yuslaimi <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
Diffstat (limited to 'scripts/cleanpatch')
0 files changed, 0 insertions, 0 deletions