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| author | Ashok Reddy Soma <[email protected]> | 2020-10-23 04:59:02 -0600 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2020-10-27 08:13:34 +0100 |
| commit | 2e819a77b9f5c011fd4ec9ac575494f9b77b1ac7 (patch) | |
| tree | e56147df0a26e3b93a32e7e5b4ccbd275b5ba320 /scripts/const_structs.checkpatch | |
| parent | f4b297bbfde3ab53e5682ff779a13c61c6e12b37 (diff) | |
mmc: zynq_sdhci: Add clock phase delays for Versal
Define default values for input and output clock phase delays for
Versal. Also define functions for setting tapdelays based on these
clock phase delays.
Signed-off-by: Ashok Reddy Soma <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Diffstat (limited to 'scripts/const_structs.checkpatch')
0 files changed, 0 insertions, 0 deletions