clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code

On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value
from cpg_pll_configs table while PLL{20,21,30,31,4} use
different control offset. Introduce new types to handle
this and handle those types in the Gen3 clock code.

Based on "clk: renesas: Add support for R8A779A0 V3U PLLn"
by Hai Pham <[email protected]>

Signed-off-by: Marek Vasut <[email protected]>

0 files changed, 0 insertions, 0 deletions