xilinx: mbv: Update defconfigs as per memory map

U-Boot SPL should be executed from LMB BRAM, where its text
and data sections are located, while the heap and stack are
allocated in DDR memory.

Because on the MB-V platform, after power-up, reset, or FPGA
load, execution begins from LMB BRAM at address 0x0. Therefore,
the SPL binary must be placed in BRAM to support this boot flow.
Without it, the system can only be booted via JTAG.

A 64KB LMB BRAM region is allocated for U-Boot SPL, starting at
address 0x0. This region contains the SPL's text, data, and device
tree blob (DTB) sections. The .bss section is placed separately at
address 0xF000.

	_________________0xFFFF
	|BSS            |
	|_______________|0xF000
	|DTB            |
	|_______________|
	|Data           |
	|_______________|
	|Text           |
	|_______________|0x0000

A 2MB region of DDR memory is allocated for U-Boot SPL, with the
heap starting at address 0x80000000 and the stack at 0x80200000.

	_________________0xBFFFFFFF
	|Full U-Boot    |
	|_______________|0x80400000
	|Load FIT Image |
	|_______________|0x80200000
	|Stack          |
	|_______________|
	|Heap           |
	|_______________|0x80000000

Since LMB BRAM is a limited resource with a practical size
constraint of 64KB - it cannot accommodate all runtime data.
Therefore, the heap and stack are placed at the beginning of
DDR memory to ensure sufficient space for SPL execution.

Signed-off-by: Padmarao Begari <[email protected]>
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/ed4a3618875869287b87b6b57fd55f4c6a36f046.1765206211.git.michal.simek@amd.com

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