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authorLoic Poulain <[email protected]>2023-01-12 18:19:50 +0100
committerStefano Babic <[email protected]>2023-01-30 23:23:02 +0100
commit7150f56a85fd8d3b8ad162621026b0ba7bb6a367 (patch)
treee666ee09acee284d07d40b434cba5c90e6ac03de /scripts/env2string.awk
parent068027b1a0c1f445d9f4da88ab74b165f902b206 (diff)
serial: mxc: Wait for TX completion before reset
The u-boot console may show some corrupted characters when printing in board_init() due to reset or baudrate change of the UART (probe) before the TX FIFO has been completely drained. To fix this issue, and in case UART is still running, we now try to flush the FIFO before proceeding to UART reinitialization. For this we're waiting for Transmitter Complete bit, indicating that the FIFO and the shift register are empty. flushing has a 4ms timeout guard, which is normally more than enough to consume the FIFO @ low baudrate (9600bps). Signed-off-by: Loic Poulain <[email protected]> Tested-by: Lothar Waßmann <[email protected]> Acked-by: Pali Rohár <[email protected]> Reviewed-by: Fabio Estevam <[email protected]>
Diffstat (limited to 'scripts/env2string.awk')
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