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authorTudor Ambarus <[email protected]>2021-11-03 18:47:10 +0200
committerEugen Hristev <[email protected]>2021-12-07 08:55:22 +0200
commit2fd1b97f33c91e9878d24a0f251ba0d2104e9e71 (patch)
tree7dde154edcf6ae53d9f856dae6a2fa065bb3b28e /scripts/gcc-stack-usage.sh
parent7dc48b41f4f3e00d9865308605cb3831d7a6c1fb (diff)
spi: atmel-quadspi: Add support for SAMA7G5 QSPI
sama7g5 QSPI has: 1/ One Octal Serial Peripheral Interfaces (QSPI0) Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash and OctaFlash Protocols Supported 2/ One Quad Serial Peripheral Interfaces (QSPI1) Supporting Up to 90 MHz DDR/133 MHz SDR The QSPI controller of SAMA7G5 uses different clock domains, hence extra synchronization operations must be performed before accessing some registers. Differentiate between the versions of the IP using has_gclk. Differentiate between QSPI0 and QSPI1 with has_octal. Signed-off-by: Tudor Ambarus <[email protected]> Reviewed-by: Jagan Teki <[email protected]>
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