Exynos542x: Add workaround for ARM errata 798870

This patch adds workaround for ARM errata 798870 which says
"If back-to-back speculative cache line fills (fill A and fill B) are
issued from the L1 data cache of a CPU to the L2 cache, the second
request (fill B) is then cancelled, and the second request would have
detected a hazard against a recent write or eviction (write B) to the
same cache line as fill B then the L2 logic might deadlock."

Signed-off-by: Kimoon Kim <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>

0 files changed, 0 insertions, 0 deletions