clk: mediatek: mt7622: deduplicate clock gate drivers

MT7622 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.

Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. Clock gate controllers that share the same DM flags
and bind() callback can then share a single U_BOOT_DRIVER: the pciesys and
ethsys controllers, which both bind a reset controller at the same offset,
are merged into one driver, and the sgmiisys and ssusbsys controllers into
another.

This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-3-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]> (changed to CONFIG_IS_ENABLED)

0 files changed, 0 insertions, 0 deletions