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| author | Patrice Chotard <[email protected]> | 2017-10-26 13:23:19 +0200 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2017-11-17 07:44:13 -0500 |
| commit | 1543bf794f4cf863b4c70eb9debba5fc1d2ebd6b (patch) | |
| tree | e274e317b778b67e276832726a2c5de4284c8240 /scripts | |
| parent | 5829fe2d59d8c088dadc43dedb36a657d791970c (diff) | |
clk: clk_stm32f7: fix PLL clock division factor
Fix clock division factor initialization for RCC_PLLCFGR
registers.
PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared,
it's a forbidden value. So update RCC_PLLCFGR using
clrsetbits_le32() to set only necessary bits fields.
Signed-off-by: Patrice Chotard <[email protected]>
Reviewed-by: Simon Glass <[email protected]>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions