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| author | Tom Rini <[email protected]> | 2025-12-19 10:30:53 -0600 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-12-19 10:30:53 -0600 |
| commit | 2aeaa3c4f53b11b97e2797eb3a0a7b603f60dc72 (patch) | |
| tree | f815ca39666d1bb8b5be752afcf1f400695ed93b /scripts | |
| parent | adbbf5982d26801224b10cd847dc468f8b5e4095 (diff) | |
| parent | 0b880fc95dbaed88dd55060730857b8f52765c57 (diff) | |
Merge tag 'xilinx-for-v2026.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next
AMD/Xilinx/FPGA changes for v2026.04-rc1
xilinx:
- Sync ESRT with detected GUID
- DT cleanups
- Add logic for FRU information multiple times
- Enable more drivers pca9541, usb5744
- Enable more commands
- Cleanup firmware DT bindings
firmware:
- Add enhancement SMC format support
clk/versal:
- Various cleanups
- Add support for Versal Gen 2
i2c:
- cdns: Add timeout for RXDV status bit polling
spi:
- cadence: Remove cdns,is-dma DT property
- cadence: Remove duplicated return
- cadence_versal: Update flash reset delay
memtop:
- Update max memory reserved spaces to 64
Versal Gen 2:
- Aligned addresses with default memory map
- Add support for reading multiboot value
MB-V:
- Make SPL smaller
- Add support for SPI
- Move SPL to run out of BRAM
ZynqMP:
- Change default load address for BL32
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions