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authorEmanuele Ghidoli <[email protected]>2026-04-21 17:15:56 +0200
committerTom Rini <[email protected]>2026-04-27 11:19:51 -0600
commit550101b487ff2b3c9d4f9057bc21dca9ab90b49a (patch)
tree637fece9c2c335e51a49ad3b2ed7d0f261b5a6b3 /scripts
parent31c5d4f18094754b9e8e823184267bf42e59b7a9 (diff)
board: toradex: aquila-am69: Fix memory size setup logic
The hardware configuration pins are used both to select the DDR configuration and to determine the installed memory size. On Aquila AM69, the DDR timing patch is applied in the R5 SPL, while the memory size fixup for the next-stage U-Boot DT is done later in the A72 SPL path. The previous immplementation was not taking in account that the hw_cfg value is lost both during SPL execution (board_init_f and board_init_r) and between SPL and U-Boot proper. Fix this by reading the hardware configuration pins when the memory size is actually needed: - in the R5 SPL, to select the correct DDR configuration - in the A72 SPL, to fix up the U-Boot DT memory size and bank layout Fixes: 3f0528882c0d ("board: toradex: add aquila am69 support") Signed-off-by: Emanuele Ghidoli <[email protected]> Acked-by: Francesco Dolcini <[email protected]>
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