diff options
| author | Simon Glass <[email protected]> | 2014-11-12 22:42:04 -0700 |
|---|---|---|
| committer | Simon Glass <[email protected]> | 2014-11-21 07:24:12 +0100 |
| commit | 5c1b685e46756dc9504b919336321dad27dbcd9e (patch) | |
| tree | e4a3f61e5571d16f283863f6ca29e30f5a819a53 /scripts | |
| parent | a5eb04db1a8fac8c7691c87cbbb890c8174ab906 (diff) | |
x86: Allow timer calibration to work on ivybridge
Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method
seems to take up to 50ms which is much too long.
For this CPU we know the frequency, so add another special case for now.
Signed-off-by: Simon Glass <[email protected]>
Reviewed-by: Bin Meng <[email protected]>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions