rockchip: sdhci: rk3568: fix clock setting logic

mmc->tran_speed is max clock, but currently rk3568_sdhci_set_ios_post
uses it if its != 0, regardless of mmc->clock value, and it breaks
eMMC controller.

Without this patch 'mmc dev 0; mmc dev 1; mmc dev 0' is enough for
breaking eMMC, since first initialization sets mmc->mmc_tran speed
to non-zero value (26MHz in my case), and on subsequent re-init when
mmc layer asks for 400KHz it sets 26MHz instead.

Fix it by using MAX(mmc->tran_speed, mmc->clock)

Signed-off-by: Vasily Khoruzhick <[email protected]>
Reviewed-by: Kever Yang <[email protected]>

0 files changed, 0 insertions, 0 deletions