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authorRichard Genoud <[email protected]>2026-01-23 12:44:58 +0100
committerMichael Trimarchi <[email protected]>2026-02-03 21:45:18 +0100
commit7d1de98011519ebbb128f76f368724b62f3bc6eb (patch)
tree90b6c130a31afcb72a62527a08281abab2f9235b /scripts
parentf163da5e6d26904e5df509169ccc8cc91a0fb295 (diff)
mtd: rawnand: sunxi_spl: add support for H6/H616 nand controller
Introduce H6/H616 NAND controller support for SPL The H616 NAND controller has the same base as A10/A23, with some differences: - MDMA is based on chained buffers - its ECC supports up to 80bit per 1024bytes - some registers layouts are a bit different, mainly due do the stronger ECC. - it uses USER_DATA_LEN registers along USER_DATA registers. - it needs a specific clock for ECC and MBUS. For SPL, most of the work was setting the clocks, adding the new capability structure for H616 and supporting the new USER_DATA_LEN registers. Tested on Whatsminer H616 board (with and without scrambling, ECC) Signed-off-by: Richard Genoud <[email protected]> Signed-off-by: Michael Trimarchi <[email protected]>
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