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| author | Svyatoslav Ryhel <[email protected]> | 2024-11-29 08:14:21 +0200 |
|---|---|---|
| committer | Svyatoslav Ryhel <[email protected]> | 2025-02-12 10:35:17 +0200 |
| commit | c3d8c206dc62a79eda44b1492decfbace151d17e (patch) | |
| tree | e90cff7578cb1d07beee18e6a0b9529f40305e35 /scripts | |
| parent | e4f5741c6dc3ba5d867336244c53eb092b273f60 (diff) | |
ARM: tegra210: clock: implement PLLD2 support
PLLD2 is a simple clock (controlled by 2 registers) and appears starting
from T30. Primary use of PLLD2 is as main HDMI clock parent.
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions