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| author | Ye Li <[email protected]> | 2019-07-22 01:25:03 +0000 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2019-10-08 16:35:16 +0200 |
| commit | eae4e0f3c10967386382b848ef80d9f8852d67a1 (patch) | |
| tree | c66f5df45fa1f1cd87ce256a4ae160cb1486b145 /scripts | |
| parent | eb6d2e5920fa518fc924025e1e7987cd0dde73ad (diff) | |
i.MX7ULP: Workaround APLL PFD2 to 345.6Mhz
The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider
set to 1. This frequecy is out of ULP A0 spec. The MAX rate for GPU
is 350Mhz. So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28)
to workaround the problem. The correct fix should let GPU handle the
clock rate in kernel.
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Diffstat (limited to 'scripts')
0 files changed, 0 insertions, 0 deletions