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| author | Vincent Jardin <[email protected]> | 2026-05-20 17:00:21 +0200 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-07-01 12:42:41 -0600 |
| commit | e800cc67f5b6cb50a20f37c993ec1cd4063bdbd3 (patch) | |
| tree | 40832ba5018152abe0ecd1458e6a4c494057c735 /test/py/tests/test_cat | |
| parent | 3900903a588964555c9e76cca53ada7d217c00f7 (diff) | |
mtd: spi-nor: Add gd55lb02gf chipsnext
Add the GigaDevice GD55LB02GF (256 Mo) similar to gd55lb02ge with
the same read path flags.
SPI_NOR_HAS_LOCK and SPI_NOR_HAS_TB do not match this chip's
status register layout: the GD55LB02GF uses a 5-bit block protect
field BP0..BP4 plus a CMP bit in SR2 for direction (see datasheet
"Status Register Block Protection").
The generic stm-lock helpers drive only BP0..BP2 and assume SR1
bit 5 is TB, but on this part SR1 bit 5 is BP3.
Enabling either flag would leave BP3..BP4 unmanaged or corrupt
BP3 on every lock op.
A proper support needs a vendor specific lock callback, it is out
of scope for this table update.
Signed-off-by: Vincent Jardin <[email protected]>
Suggested-by: Takahiro Kuwano <[email protected]>
Reviewed-by: Takahiro Kuwano <[email protected]>
Diffstat (limited to 'test/py/tests/test_cat')
0 files changed, 0 insertions, 0 deletions