diff options
| author | Paul Burton <[email protected]> | 2015-01-29 01:28:03 +0000 |
|---|---|---|
| committer | Daniel Schwierzeck <[email protected]> | 2015-01-29 12:55:01 +0100 |
| commit | 8755d50706742e4d302a335f4e69dd6430ec12a2 (patch) | |
| tree | b7730ef7f29fc91b729413d7f447075972f3a2f3 /tools | |
| parent | dd7c72006e51f0d27e5cb1dcf60d5b9bf307565e (diff) | |
MIPS: clear TagLo select 2 during cache init
Current MIPS cores from Imagination Technologies use TagLo select 2 for
the data cache. The architecture requires that it is safe for software
to write to this register even if it isn't present, so take the trivial
option of clearing both selects 0 & 2.
Signed-off-by: Paul Burton <[email protected]>
Cc: Daniel Schwierzeck <[email protected]>
Diffstat (limited to 'tools')
0 files changed, 0 insertions, 0 deletions