diff options
571 files changed, 20687 insertions, 17909 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 4417ef4e5a5..5bda11a0309 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -146,7 +146,7 @@ stages: make tools-only_config envtools -j$(nproc) - job: utils - displayName: 'Run binman, buildman, dtoc, Kconfig and patman testsuites' + displayName: 'Run binman, buildman, dtoc and Kconfig testsuites' pool: vmImage: $(ubuntu_vm) container: @@ -163,8 +163,8 @@ stages: pip install -r test/py/requirements.txt \ -r tools/binman/requirements.txt \ -r tools/buildman/requirements.txt \ - -r tools/patman/requirements.txt \ - -r tools/u_boot_pylib/requirements.txt + -r tools/u_boot_pylib/requirements.txt \ + -r scripts/dtc/pylibfdt/requirements.txt export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only export PYTHONPATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt export PATH=${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH} @@ -177,7 +177,6 @@ stages: COVERAGE_FILE=/tmp/.coverage ./tools/binman/binman ${TOOLPATH} test -T ./tools/buildman/buildman -t ./tools/dtoc/dtoc -t - ./tools/patman/patman test make O=${UBOOT_TRAVIS_BUILD_DIR} testconfig - job: pylint @@ -196,8 +195,8 @@ stages: pip install -r test/py/requirements.txt \ -r tools/binman/requirements.txt \ -r tools/buildman/requirements.txt \ - -r tools/patman/requirements.txt \ -r tools/u_boot_pylib/requirements.txt \ + -r scripts/dtc/pylibfdt/requirements.txt \ asteval pylint==3.3.4 pyopenssl export PATH=${PATH}:~/.local/bin echo "[MASTER]" >> .pylintrc diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 245e422d72f..c2716af1904 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -206,7 +206,7 @@ Build allyesconfig, tools-only and envtools: make mrproper; make tools-only_config envtools -j$(nproc) -Run binman, buildman, dtoc, Kconfig and patman testsuites: +Run binman, buildman, dtoc and Kconfig testsuites: extends: .testsuites tags: - ${DEFAULT_AMD64_TAG} @@ -218,8 +218,9 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites: python3 -m venv /tmp/venv; . /tmp/venv/bin/activate; pip install -r test/py/requirements.txt -r tools/binman/requirements.txt - -r tools/buildman/requirements.txt -r tools/patman/requirements.txt - -r tools/u_boot_pylib/requirements.txt; + -r tools/buildman/requirements.txt + -r tools/u_boot_pylib/requirements.txt + -r scripts/dtc/pylibfdt/requirements.txt; export UBOOT_TRAVIS_BUILD_DIR=/tmp/tools-only; export PYTHONPATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc/pylibfdt"; export PATH="${UBOOT_TRAVIS_BUILD_DIR}/scripts/dtc:${PATH}"; @@ -233,7 +234,6 @@ Run binman, buildman, dtoc, Kconfig and patman testsuites: ./tools/binman/binman ${TOOLPATH} test -T; ./tools/buildman/buildman -t; ./tools/dtoc/dtoc -t; - ./tools/patman/patman test; make testconfig # Check for any pylint regressions @@ -244,8 +244,9 @@ Run pylint: - python3 -m venv /tmp/venv - . /tmp/venv/bin/activate - pip install -r test/py/requirements.txt -r tools/binman/requirements.txt - -r tools/buildman/requirements.txt -r tools/patman/requirements.txt - -r tools/u_boot_pylib/requirements.txt asteval pylint==3.3.4 pyopenssl + -r tools/buildman/requirements.txt + -r tools/u_boot_pylib/requirements.txt + -r scripts/dtc/pylibfdt/requirements.txt asteval pylint==3.3.4 pyopenssl - export PATH=${PATH}:~/.local/bin - echo "[MASTER]" >> .pylintrc - echo "load-plugins=pylint.extensions.docparams" >> .pylintrc @@ -15,7 +15,9 @@ # Proper Name <[email protected]> <[email protected]> # Proper Name <[email protected]> Commit Name <[email protected]> AKASHI Takahiro <[email protected]> <[email protected]> +Abbarapu Venkatesh Yadav <[email protected]> Venkatesh Yadav Abbarapu <[email protected]> Alexander Graf <[email protected]> <[email protected]> Allen Martin <[email protected]> Amanda Baze <[email protected]> <[email protected]> @@ -41,21 +43,21 @@ Chen-Yu Tsai <[email protected]> <[email protected]> Christian Kohn <[email protected]> <[email protected]> Christopher Obbard <[email protected]> <[email protected]> Dirk Behme <[email protected]> Durga Challa <[email protected]> <[email protected]> -Eugen Hristev <[email protected]> <[email protected]> -Eugen Hristev <[email protected]> <[email protected]> Eugen Hristev <[email protected]> <[email protected]> +Eugen Hristev <[email protected]> <[email protected]> +Eugen Hristev <[email protected]> <[email protected]> Fabio Estevam <[email protected]> Greg Malysa <[email protected]> <[email protected]> +Gregory CLEMENT <[email protected]> <[email protected]> Harini Katakam <[email protected]> <[email protected]> Harsha <[email protected]> <[email protected]> -Heiko Stuebner <[email protected]> <[email protected]> -Heiko Schocher <[email protected]> <[email protected]> -Heiko Schocher <[email protected]> <[email protected]> -Heiko Schocher <[email protected]> <[email protected]> Heiko Schocher <[email protected]> <[[email protected]]> +Heiko Schocher <[email protected]> <[email protected]> +Heiko Schocher <[email protected]> <[email protected]> Heiko Schocher <[email protected]> <hs@pollux.(none)> +Heiko Schocher <[email protected]> <[email protected]> +Heiko Stuebner <[email protected]> <[email protected]> Heinrich Schuchardt <[email protected]> <[email protected]> Ibai Erkiaga <[email protected]> <[email protected]> @@ -71,14 +73,13 @@ Jakob Unterwurzacher <[email protected]> <jakob.unterwurzacher@theo Javier Tia <[email protected]> <[email protected]> Jay Buddhabhatti <[email protected]> <[email protected]> Jernej Skrabec <[email protected]> <[email protected]> -Jerome Forissier <[email protected]> <[email protected]> Jerome Forissier <[email protected]> <[email protected]> +Jerome Forissier <[email protected]> <[email protected]> John Linn <[email protected]> <[email protected]> Jyotheeswar Reddy Mutthareddyvari <[email protected]> <[email protected]> Jyotheeswar Reddy Mutthareddyvari <[email protected]> <[email protected]> Kalyani Akula <[email protected]> <[email protected]> Klaus Goger <[email protected]> <[email protected]> -Masahisa Kojima <[email protected]> <[email protected]> Linus Walleij <[email protected]> <[email protected]> Love Kumar <[email protected]> <[email protected]> Lukasz Majewski <[email protected]> @@ -88,13 +89,15 @@ Marek Vasut <[email protected]> <[email protected]> Marek Vasut <[email protected]> <[email protected]> Marek Vasut <[email protected]> <marex at denx.de> Markus Klotzbuecher <[email protected]> -Masahiro Yamada <[email protected]> <[email protected]> Masahiro Yamada <[email protected]> <[email protected]> +Masahiro Yamada <[email protected]> <[email protected]> +Masahisa Kojima <[email protected]> <[email protected]> Mattijs Korpershoek <[email protected]> <[email protected]> Michal Simek <[email protected]> <[email protected]> Michal Simek <[email protected]> <[email protected]> Michal Simek <[email protected]> <[email protected]> Michal Simek <[email protected]> <[email protected]> +Miquel Raynal <[email protected]> <[email protected]> Mirza <[email protected]> Mounika Grace Akula <[email protected]> <[email protected]> Mubin Usman Sayyed <[email protected]> <[email protected]> @@ -104,8 +107,6 @@ Nava kishore Manne <[email protected]> <[email protected]> Neal Frager <[email protected]> <[email protected]> Neil Armstrong <[email protected]> <[email protected]> Nicolas Saenz Julienne <[email protected]> <[email protected]> -This contributor prefers not to receive mails <[email protected]> <[email protected]> -This contributor prefers not to receive mails <[email protected]> <[email protected]> Padmarao Begari <[email protected]> <[email protected]> Patrice Chotard <[email protected]> <[email protected]> Patrick Delaunay <[email protected]> <[email protected]> @@ -146,14 +147,17 @@ Stefan Roese <[email protected]> <stroese> Stefano Babic <[email protected]> Stefano Stabellini <[email protected]> <[email protected]> Sughosh Ganu <[email protected]> <[email protected]> -No generic patch CC mail please <[email protected]> <[email protected]> -No generic patch CC mail please <[email protected]> <[email protected]> Sumit Garg <[email protected]> <[email protected]> +This contributor prefers not to receive mails <[email protected]> <[email protected]> +This contributor prefers not to receive mails <[email protected]> <[email protected]> +This contributor prefers not to receive mails <[email protected]> <[email protected]> +This contributor prefers not to receive mails <[email protected]> <[email protected]> +Thomas Petazzoni <[email protected]> <[email protected]> Tom Rini <[email protected]> <[email protected]> Tomas Thoresen <[email protected]> <[email protected]> TsiChung Liew <[email protected]> Varalaxmi Bingi <[email protected]> <[email protected]> -Abbarapu Venkatesh Yadav <[email protected]> +Venkatesh Yadav Abbarapu <[email protected]> <[email protected]> Vikhyat Goyal <[email protected]> <[email protected]> Vishal Patel <[email protected]> <[email protected]> Wolfgang Denk <[email protected]> <[email protected]> diff --git a/.patman-defaults b/.patman-defaults new file mode 100644 index 00000000000..6b6063b05f4 --- /dev/null +++ b/.patman-defaults @@ -0,0 +1,32 @@ +# Default patman settings for the U-Boot tree +# +# patman is maintained separately; install it with: +# pip install patch-manager +# +# See https://deinde.dev/patman +# +# patman reads this file at the lowest priority, so anything set here is a +# default that you can override in your own ~/.patman, in a local .patman or +# on the command line. patman autodetects the U-Boot project and locates +# scripts/get_maintainer.pl on its own; the patchwork server and get-maintainer +# script are pinned here so U-Boot does not depend on patman's built-in +# defaults in case those change. + +[settings] +patchwork_url: https://patchwork.ozlabs.org +get_maintainer_script: scripts/get_maintainer.pl --norolestats + +# Other settings you might set here as project defaults: +# process_tags: True +# add_signoff: True +# check_patch: True +# verbose: False +# smtp_server: /path/to/sendmail + +# Aliases are recursive and are usually kept per-user in ~/.patman: +# [alias] +# me: Your Name <[email protected]> + +# Addresses known to bounce can be dropped from the recipient list: +# [bounces] +# someone: A Name <[email protected]> @@ -193,7 +193,7 @@ config FUZZ select ASAN help Enables the fuzzing infrastructure to generate fuzzing data and run - fuzz tests. + fuzz tests. config CC_HAS_ASM_INLINE def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x c - -c -o /dev/null) @@ -308,11 +308,11 @@ config SYS_MALLOC_F_LEN default 0x10000 if ARCH_IMX8 || ARCH_IMX8M default 0x2000 help - Size of the malloc() pool for use before relocation. If - this is defined, then a very simple malloc() implementation - will become available before relocation. The address is just - below the global data, and the stack is moved down to make - space. + Size of the malloc() pool for use before relocation. If + this is defined, then a very simple malloc() implementation + will become available before relocation. The address is just + below the global data, and the stack is moved down to make + space. This feature allocates regions with increasing addresses within the region. calloc() is supported, but realloc() @@ -420,7 +420,7 @@ menuconfig EXPERT Use this only if you really know what you are doing. if EXPERT - config SYS_MALLOC_CLEAR_ON_INIT +config SYS_MALLOC_CLEAR_ON_INIT bool "Init with zeros the memory reserved for malloc (slow)" default y help diff --git a/MAINTAINERS b/MAINTAINERS index 370bcff56c1..e53cb0a485c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -160,6 +160,7 @@ F: include/configs/apple.h ARM M: Tom Rini <[email protected]> +M: Ilias Apalodimas <[email protected]> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-arm.git F: arch/arm/ @@ -214,11 +215,13 @@ M: Chia-Wei Wang <[email protected]> R: Aspeed BMC SW team <[email protected]> R: Joel Stanley <[email protected]> S: Maintained +F: arch/arm/dts/ast* F: drivers/i2c/ast_i2c.[ch] F: drivers/net/ftgmac100.[ch] F: drivers/watchdog/ast_wdt.c N: aspeed N: ast2500 +N: ast2700 ARM AXIADO AX3005 SCM3005 M: Siu Ming Tong <[email protected]> @@ -288,21 +291,10 @@ F: drivers/spi/bcmstb_spi.c ARM CORTINA ACCESS CAxxxx M: Alex Nemirovsky <[email protected]> S: Supported -F: board/cortina/common/ -F: drivers/gpio/cortina_gpio.c -F: drivers/watchdog/cortina_wdt.c -F: drivers/serial/serial_cortina.c -F: drivers/led/led_cortina.c +N: cortina F: drivers/mmc/ca_dw_mmc.c F: drivers/spi/ca_sflash.c -F: drivers/i2c/i2c-cortina.c -F: drivers/i2c/i2c-cortina.h -F: drivers/mtd/nand/raw/cortina_nand.c -F: drivers/mtd/nand/raw/cortina_nand.h -F: drivers/net/cortina_ni.c -F: drivers/net/cortina_ni.h F: drivers/net/phy/ca_phy.c -F: configs/cortina_presidio-asic-pnand_defconfig ARM FF-A M: Abdellatif El Khlifi <[email protected]> @@ -563,45 +555,35 @@ F: drivers/usb/host/xhci-rcar* ARM ROCKCHIP M: Simon Glass <[email protected]> -M: Philipp Tomsich <[email protected]> +M: Quentin Schulz <[email protected]> M: Kever Yang <[email protected]> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-rockchip.git -F: arch/arm/dts/px30* -F: arch/arm/dts/rk3* -F: arch/arm/dts/rockchip* -F: arch/arm/dts/rv11* -F: arch/arm/include/asm/arch-rockchip/ -F: arch/arm/mach-rockchip/ -F: board/amarula/vyasa-rk3288/ -F: board/anbernic/rgxx3_rk3566/ -F: board/armsom/sige7-rk3588/ -F: board/chipspark/popmetal_rk3288 -F: board/engicam/px30_core/ -F: board/firefly/ -F: board/mqmaker/miqi_rk3288/ -F: board/phytec/phycore_rk3288 -F: board/pine64 +# Exclude from N: px5 matches +X: configs/kmsupx5_defconfig +N: px30 +N: px5 +# RK3xxx SoC family +N: rk3 +# RK8xx PMIC/regulator family +N: rk8 +N: rkmtd +N: rockchip +N: rockusb +# RV11xx SoC family +N: rv11 F: board/radxa/ -F: board/rockchip/ F: board/theobroma-systems -F: board/vamrs/rock960_rk3399/ -F: drivers/clk/rockchip/ F: drivers/gpio/rk_gpio.c -F: drivers/misc/rockchip-efuse.c -F: drivers/mmc/rockchip_sdhci.c -F: drivers/mmc/rockchip_dw_mmc.c -F: drivers/pinctrl/rockchip/ -F: drivers/ram/rockchip/ -F: drivers/sysreset/sysreset_rockchip.c -F: drivers/ufs/*rockchip* -F: drivers/video/rockchip/ +F: drivers/i2c/rk_i2c.c +F: drivers/pwm/rk_pwm.c +F: drivers/spi/rk_spi.[ch] F: tools/rkcommon.c F: tools/rkcommon.h F: tools/rkimage.c +F: tools/rkmux.py F: tools/rksd.c F: tools/rkspi.c -N: rockchip ARM SAMSUNG M: Minkyu Kang <[email protected]> @@ -889,72 +871,24 @@ T: git git://github.com/ARM-software/u-boot.git F: drivers/misc/vexpress_config.c N: vexpress -ARM ZYNQ +ARM ZYNQ and ZYNQMP M: Michal Simek <[email protected]> +M: Michal Simek <[email protected]> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git -F: arch/arm/mach-zynq/ F: doc/board/xilinx/ F: doc/device-tree-bindings/video/syncoam,seps525.txt -F: drivers/clk/clk_zynq.c -F: drivers/fpga/zynqpl.c -F: drivers/gpio/zynq_gpio.c -F: drivers/i2c/i2c-cdns.c -F: drivers/i2c/muxes/pca954x.c -F: drivers/i2c/zynq_i2c.c -F: drivers/mmc/zynq_sdhci.c -F: drivers/mtd/nand/raw/zynq_nand.c -F: drivers/net/phy/ethernet_id.c -F: drivers/net/phy/xilinx_phy.c -F: drivers/net/zynq_gem.c -F: drivers/pinctrl/pinctrl-zynqmp.c -F: drivers/serial/serial_zynq.c -F: drivers/spi/zynq_qspi.c -F: drivers/spi/zynq_spi.c -F: drivers/usb/host/ehci-zynq.c -F: drivers/watchdog/cdns_wdt.c -F: include/zynqpl.h -F: tools/zynqimage.c -N: zynq - -ARM ZYNQMP -M: Michal Simek <[email protected]> -S: Maintained -T: git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git -F: arch/arm/mach-zynqmp/ -F: drivers/bootcount/bootcount_zynqmp.c -F: drivers/clk/clk_zynqmp.c -F: driver/firmware/firmware-zynqmp.c -F: drivers/fpga/zynqpl.c F: drivers/gpio/gpio_slg7xl45106.c -F: drivers/gpio/zynq_gpio.c -F: drivers/gpio/zynqmp_gpio_modepin.c F: drivers/i2c/i2c-cdns.c F: drivers/i2c/muxes/pca954x.c -F: drivers/i2c/zynq_i2c.c -F: drivers/mailbox/zynqmp-ipi.c -F: drivers/mmc/zynq_sdhci.c -F: drivers/mtd/nand/raw/zynq_nand.c +F: drivers/net/phy/ethernet_id.c F: drivers/net/phy/xilinx_phy.c -F: drivers/net/zynq_gem.c -F: drivers/phy/phy-zynqmp.c -F: drivers/power/domain/zynqmp-power-domain.c F: drivers/pwm/pwm-cadence-ttc.c -F: drivers/serial/serial_zynq.c -F: drivers/reset/reset-zynqmp.c -F: drivers/rtc/zynqmp_rtc.c -F: drivers/soc/soc_xilinx_zynqmp.c -F: drivers/spi/zynq_qspi.c -F: drivers/spi/zynq_spi.c F: drivers/timer/cadence-ttc.c F: drivers/video/seps525.c -F: drivers/video/zynqmp/ F: drivers/watchdog/cdns_wdt.c -F: include/zynqmppl.h -F: include/zynqmp_firmware.h -F: tools/zynqmp* N: ultra96 -N: zynqmp +N: zynq ARM ZYNQMP R5 M: Michal Simek <[email protected]> @@ -1566,6 +1500,16 @@ M: Simon Glass <[email protected]> S: Maintained F: tools/patman/ +PCI +M: Neil Armstrong <[email protected]> +S: Maintained +F: cmd/pci.c +F: drivers/pci +F: include/pci.h +F: include/pci_ids.h +F: test/dm/pci.c +N: pci + PCIe DWC IMX M: Sumit Garg <[email protected]> S: Maintained @@ -3,7 +3,7 @@ VERSION = 2026 PATCHLEVEL = 07 SUBLEVEL = -EXTRAVERSION = -rc5 +EXTRAVERSION = NAME = # *DOCUMENTATION* @@ -2692,7 +2692,6 @@ pip pip_test pip_release: _pip _pip: scripts/make_pip.sh u_boot_pylib ${PIP_ARGS} - scripts/make_pip.sh patman ${PIP_ARGS} scripts/make_pip.sh buildman ${PIP_ARGS} scripts/make_pip.sh dtoc ${PIP_ARGS} scripts/make_pip.sh binman ${PIP_ARGS} diff --git a/arch/Kconfig b/arch/Kconfig index e28e4c4bce7..8d63afeb138 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -11,14 +11,14 @@ config HAVE_ARCH_IOREMAP config HAVE_SETJMP bool help - The architecture supports setjmp() and longjmp(). + The architecture supports setjmp() and longjmp(). config HAVE_INITJMP bool depends on HAVE_SETJMP help - The architecture supports initjmp(), a non-standard companion to - setjmp() and longjmp(). + The architecture supports initjmp(), a non-standard companion to + setjmp() and longjmp(). config SUPPORT_BIG_ENDIAN bool @@ -457,11 +457,11 @@ config SYS_CONFIG_NAME config SYS_DISABLE_DCACHE_OPS bool help - This option disables dcache flush and dcache invalidation - operations. For example, on coherent systems where cache - operatios are not required, enable this option to avoid them. - Note that, its up to the individual architectures to implement - this functionality. + This option disables dcache flush and dcache invalidation + operations. For example, on coherent systems where cache + operatios are not required, enable this option to avoid them. + Note that, its up to the individual architectures to implement + this functionality. config SYS_IMMR hex "Address for the Internal Memory-Mapped Registers (IMMR) window" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8047c5e1f87..1b474a346bf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -477,30 +477,30 @@ config SYS_THUMB_BUILD bool "Build U-Boot using the Thumb instruction set" depends on !ARM64 help - Use this flag to build U-Boot using the Thumb instruction set for - ARM architectures. Thumb instruction set provides better code - density. For ARM architectures that support Thumb2 this flag will - result in Thumb2 code generated by GCC. + Use this flag to build U-Boot using the Thumb instruction set for + ARM architectures. Thumb instruction set provides better code + density. For ARM architectures that support Thumb2 this flag will + result in Thumb2 code generated by GCC. config SPL_SYS_THUMB_BUILD bool "Build SPL using the Thumb instruction set" default y if SYS_THUMB_BUILD depends on !ARM64 && SPL help - Use this flag to build SPL using the Thumb instruction set for - ARM architectures. Thumb instruction set provides better code - density. For ARM architectures that support Thumb2 this flag will - result in Thumb2 code generated by GCC. + Use this flag to build SPL using the Thumb instruction set for + ARM architectures. Thumb instruction set provides better code + density. For ARM architectures that support Thumb2 this flag will + result in Thumb2 code generated by GCC. config TPL_SYS_THUMB_BUILD bool "Build TPL using the Thumb instruction set" default y if SYS_THUMB_BUILD depends on TPL && !ARM64 help - Use this flag to build TPL using the Thumb instruction set for - ARM architectures. Thumb instruction set provides better code - density. For ARM architectures that support Thumb2 this flag will - result in Thumb2 code generated by GCC. + Use this flag to build TPL using the Thumb instruction set for + ARM architectures. Thumb instruction set provides better code + density. For ARM architectures that support Thumb2 this flag will + result in Thumb2 code generated by GCC. config SYS_L2_PL310 bool "ARM PL310 L2 cache controller" @@ -1583,7 +1583,7 @@ config TARGET_HIKEY select PL01X_SERIAL select SPECIFY_CONSOLE_INDEX imply CMD_DM - help + help Support for HiKey 96boards platform. It features a HI6220 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. @@ -1596,7 +1596,7 @@ config TARGET_HIKEY960 select OF_CONTROL select PL01X_SERIAL imply CMD_DM - help + help Support for HiKey960 96boards platform. It features a HI3660 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM. @@ -1609,7 +1609,7 @@ config TARGET_POPLAR select OF_CONTROL select PL01X_SERIAL imply CMD_DM - help + help Support for Poplar 96boards EE platform. It features a HI3798cv200 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU making it capable of running any commercial set-top solution based on @@ -1667,10 +1667,10 @@ config TARGET_LS1012AFRWY imply SCSI imply SCSI_AHCI help - Support for Freescale LS1012AFRWY platform. - The LS1012A FRWY board (FRWY) is a high-performance - development platform that supports the QorIQ LS1012A - Layerscape Architecture processor. + Support for Freescale LS1012AFRWY platform. + The LS1012A FRWY board (FRWY) is a high-performance + development platform that supports the QorIQ LS1012A + Layerscape Architecture processor. config TARGET_LS1012AFRDM bool "Support ls1012afrdm" @@ -1778,9 +1778,9 @@ config TARGET_PG_WCOM_SELI8 select VENDOR_KM imply SCSI help - Support for Hitachi-Powergrids SELI8 service unit card. - SELI8 is a QorIQ LS1021a based service unit card used - in XMC20 and FOX615 product families. + Support for Hitachi-Powergrids SELI8 service unit card. + SELI8 is a QorIQ LS1021a based service unit card used + in XMC20 and FOX615 product families. config TARGET_PG_WCOM_EXPU1 bool "Support Hitachi-Powergrids EXPU1 service unit card" @@ -1796,9 +1796,9 @@ config TARGET_PG_WCOM_EXPU1 select VENDOR_KM imply SCSI help - Support for Hitachi-Powergrids EXPU1 service unit card. - EXPU1 is a QorIQ LS1021a based service unit card used - in XMC20 and FOX615 product families. + Support for Hitachi-Powergrids EXPU1 service unit card. + EXPU1 is a QorIQ LS1021a based service unit card used + in XMC20 and FOX615 product families. config TARGET_LS1021ATSN bool "Support ls1021atsn" @@ -2180,8 +2180,8 @@ config TARGET_POMELO select DM_SERIAL imply CMD_PCI help - Support for pomelo platform. - It has 8GB Sdram, uart and pcie. + Support for pomelo platform. + It has 8GB Sdram, uart and pcie. config TARGET_PE2201 bool "Support Phytium PE2201 Platform" diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index 3a3c1784e18..18e7aed94d9 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -13,19 +13,19 @@ config ARMV7_NONSEC bool "Enable support for booting in non-secure mode" if EXPERT depends on CPU_V7_HAS_NONSEC default y - ---help--- - Say Y here to enable support for booting in non-secure / SVC mode. + help + Say Y here to enable support for booting in non-secure / SVC mode. config ARMV7_BOOT_SEC_DEFAULT bool "Boot in secure mode by default" if EXPERT depends on ARMV7_NONSEC default y if ARCH_TEGRA - ---help--- - Say Y here to boot in secure mode by default even if non-secure mode - is supported. This option is useful to boot kernels which do not - suppport booting in non-secure mode. Only set this if you need it. - This can be overridden at run-time by setting the bootm_boot_mode env. - variable to "sec" or "nonsec". + help + Say Y here to boot in secure mode by default even if non-secure mode + is supported. This option is useful to boot kernels which do not + support booting in non-secure mode. Only set this if you need it. + This can be overridden at run-time by setting the bootm_boot_mode env. + variable to "sec" or "nonsec". config HAS_ARMV7_SECURE_BASE bool "Enable support for a hardware secure memory area" @@ -74,8 +74,8 @@ config ARMV7_VIRT bool "Enable support for hardware virtualization" if EXPERT depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC default y - ---help--- - Say Y here to boot in hypervisor (HYP) mode when booting non-secure. + help + Say Y here to boot in hypervisor (HYP) mode when booting non-secure. config ARMV7_PSCI bool "Enable PSCI support" if EXPERT @@ -115,9 +115,9 @@ config ARMV7_LPAE bool "Use LPAE page table format" if EXPERT depends on CPU_V7A default y if ARMV7_VIRT - ---help--- - Say Y here to use the long descriptor page table format. This is - required if U-Boot runs in HYP mode. + help + Say Y here to use the long descriptor page table format. This is + required if U-Boot runs in HYP mode. config ARMV7_SET_CORTEX_SMPEN bool diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 5c8839583aa..9ce94555ed0 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -100,9 +100,9 @@ config SYS_FSL_ERRATUM_A008407 config SYS_FSL_QSPI_SKIP_CLKSEL bool "Skip setting QSPI clock during SoC init" help - To improve startup times when booting from QSPI flash, the QSPI - frequency can be set very early in the boot process. If this option - is enabled, the QSPI frequency will not be changed by U-Boot during - SoC initialization. + To improve startup times when booting from QSPI flash, the QSPI + frequency can be set very early in the boot process. If this option + is enabled, the QSPI frequency will not be changed by U-Boot during + SoC initialization. endmenu diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index dfc4ce851c3..7e4e3bdd66c 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -23,11 +23,11 @@ config ARMV8_SPL_EXCEPTION_VECTORS and want to save some space at the cost of less debugging info. config ARMV8_MULTIENTRY - bool "Enable multiple CPUs to enter into U-Boot" + bool "Enable multiple CPUs to enter into U-Boot" config ARMV8_SET_SMPEN - bool "Enable data coherency with other cores in cluster" - help + bool "Enable data coherency with other cores in cluster" + help Say Y here if there is not any trust firmware to set CPUECTLR_EL1.SMPEN bit before U-Boot. @@ -79,12 +79,12 @@ config ARMV8_SEC_FIRMWARE_SUPPORT process brief. Note: Only FIT format image is supported. You should prepare and provide the below information: - - Address of secure firmware. - - Address to hold the return address from secure firmware. - - Secure firmware FIT image related information. - Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME - - The target exception level that secure monitor firmware will - return to. + - Address of secure firmware. + - Address to hold the return address from secure firmware. + - Secure firmware FIT image related information. + Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMWARE_FIT_CNF_NAME + - The target exception level that secure monitor firmware will + return to. config SPL_ARMV8_SEC_FIRMWARE_SUPPORT bool "Enable ARMv8 secure monitor firmware framework support for SPL" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 4c5b38e3b65..2335c776c2e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -440,8 +440,8 @@ config MAX_CPUS config EMC2305 bool "Fan controller" help - Enable the EMC2305 fan controller for configuration of fan - speed. + Enable the EMC2305 fan controller for configuration of fan + speed. config QSPI_AHB_INIT bool "Init the QSPI AHB bus" @@ -548,7 +548,7 @@ config SYS_FSL_PCLK_DIV help This is the divider that is used to derive Platform clock from Platform PLL, in another word: - Platform_clk = Platform_PLL_freq / this_divider + Platform_clk = Platform_PLL_freq / this_divider config SYS_FSL_DSPI_CLK_DIV int "DSPI clock divider" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a29d1807e71..25234697e6a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1024,6 +1024,8 @@ dtb-$(CONFIG_ASPEED_AST2600) += \ ast2600-evb.dtb \ ast2600-sbp1.dtb \ ast2600-x4tf.dtb +dtb-$(CONFIG_ASPEED_AST2700) += \ + ast2700-evb.dtb dtb-$(CONFIG_STM32MP15X) += \ stm32mp157c-odyssey.dtb diff --git a/arch/arm/dts/ast2700-evb.dts b/arch/arm/dts/ast2700-evb.dts new file mode 100644 index 00000000000..e7222d9691f --- /dev/null +++ b/arch/arm/dts/ast2700-evb.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; + +#include "ast2700.dtsi" +#include "ast2700-u-boot.dtsi" + +/ { + model = "AST2700 EVB"; + compatible = "aspeed,ast2700-evb", "aspeed,ast2700"; + + memory@400000000 { + device_type = "memory"; + reg = <0x4 0x00000000 0x0 0x20000000>; + }; + + chosen { + stdout-path = &uart12; + }; + +}; + +&uart12 { + status = "okay"; +}; + +&mdio0 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + ethphy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mdio1 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + ethphy1: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mac0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; +}; + +&mac1 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <ðphy1>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; +}; + +&fmc { + status = "okay"; + + flash@0 { + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + + flash@1 { + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + + flash@2 { + status = "okay"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&wdt0 { + status = "okay"; +}; diff --git a/arch/arm/dts/ast2700-u-boot.dtsi b/arch/arm/dts/ast2700-u-boot.dtsi new file mode 100644 index 00000000000..8830eca3a43 --- /dev/null +++ b/arch/arm/dts/ast2700-u-boot.dtsi @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ + +&soc0 { + bootph-all; +}; + +&sdrammc { + bootph-all; +}; + +&syscon0 { + bootph-all; +}; + +&uart12 { + bootph-all; +}; + +&soc1 { + bootph-all; +}; + +&syscon1 { + bootph-all; +}; diff --git a/arch/arm/dts/ast2700.dtsi b/arch/arm/dts/ast2700.dtsi new file mode 100644 index 00000000000..3dd6826fd0c --- /dev/null +++ b/arch/arm/dts/ast2700.dtsi @@ -0,0 +1,693 @@ +// SPDX-License-Identifier: GPL-2.0+ +#include <dt-bindings/clock/aspeed,ast2700-scu.h> +#include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/reset/aspeed,ast2700-scu.h> + +/ { + model = "Aspeed BMC"; + compatible = "aspeed,ast2700"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + serial6 = &uart6; + serial7 = &uart7; + serial8 = &uart8; + serial9 = &uart9; + serial10 = &uart10; + serial11 = &uart11; + serial12 = &uart12; + mmc0 = &emmc; + mmc1 = &sdhci; + ethernet0 = &mac0; + ethernet1 = &mac1; + ethernet2 = &mac2; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x2>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x3>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + }; + + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + gic: interrupt-controller@12200000 { + compatible = "arm,gic-v3"; + reg = <0 0x12200000 0 0x10000>, /* GICD */ + <0 0x12280000 0 0x80000>, /* GICR */ + <0 0x40440000 0 0x1000>; /* GICC */ + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + atf: trusted-firmware-a@430000000 { + reg = <0x4 0x30000000 0x0 0x80000>; + no-map; + }; + + optee_core: optee-core@430080000 { + reg = <0x4 0x30080000 0x0 0x1000000>; + no-map; + }; + }; + + soc0: soc@10000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x10000000 0x0 0x10000000 0x0 0x4000000>; + + uhci0: usb@12040000 { + compatible = "aspeed,ast2700-uhci", "generic-uhci"; + reg = <0x0 0x12040000 0x0 0x100>; + #ports = <2>; + clocks = <&syscon0 SCU0_CLK_GATE_UHCICLK>; + resets = <&syscon0 SCU0_RESET_UHCI>; + status = "disabled"; + }; + + ehci0: usb@12061000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x12061000 0x0 0x100>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTA_VHUB_EHCI>; + status = "disabled"; + }; + + vhuba0: usb-vhub@12060000 { + compatible = "aspeed,ast2700-usb-vhuba0"; + reg = <0 0x12060000 0 0x350>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTA_VHUB_EHCI>; + status = "disabled"; + }; + + vhubb0: usb-vhub@12062000 { + compatible = "aspeed,ast2700-usb-vhubb0"; + reg = <0x0 0x12062000 0x0 0x350>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTBUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTB_VHUB_EHCI>; + status = "disabled"; + }; + + ehci1: usb@12063000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x12063000 0x0 0x100>; + clocks = <&syscon0 SCU0_CLK_GATE_PORTBUSB2CLK>; + resets = <&syscon0 SCU0_RESET_PORTB_VHUB_EHCI>; + status = "disabled"; + }; + + emmc_controller: sdc@12090000 { + compatible = "aspeed,ast2700-sd-controller"; + reg = <0 0x12090000 0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0x12090000 0x10000>; + clocks = <&syscon0 SCU0_CLK_GATE_EMMCCLK>; + resets = <&syscon0 SCU0_RESET_EMMC>; + status = "disable"; + + emmc: sdhci@100 { + compatible = "aspeed,ast2700-sdhci"; + reg = <0x100 0x100>; + sdhci,auto-cmd12; + clocks = <&syscon0 SCU0_CLK_GATE_EMMCCLK>; + status = "disable"; + }; + }; + + intc0: interrupt-controller@12100000 { + compatible = "aspeed,ast2700-intc0"; + reg = <0x0 0x12100000 0x0 0x3c00>; + interrupt-controller; + interrupt-parent = <&gic>; + #interrupt-cells = <1>; + }; + + sdrammc: sdrammc@12c00000 { + compatible = "aspeed,ast2700-sdrammc"; + reg = <0 0x12c00000 0 0x3000 0 0x13000000 0 0x300 >; + clocks = <&syscon0 SCU0_CLK_MPLL>; + resets = <&syscon0 SCU0_RESET_SDRAM>; + aspeed,scu0 = <&syscon0>; + aspeed,scu1 = <&syscon1>; + }; + + syscon0: syscon@12c02000 { + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg = <0x0 0x12c02000 0x0 0x1000>; + ranges = <0x0 0x0 0x12c02000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + + pinctrl0: pinctrl@400 { + compatible = "aspeed,ast2700-soc0-pinctrl"; + reg = <0x400 0x318>; + }; + }; + + gpio0: gpio@12c11000 { + compatible = "aspeed,ast2700-gpio"; + reg = <0x0 0x12c11000 0x0 0x1000>; + gpio-ranges = <&pinctrl0 0 0 12>; + ngpios = <12>; + clocks = <&syscon0 SCU0_CLK_APB>; + }; + + uart4: serial@12c1a000 { + compatible = "ns16550a"; + reg = <0x0 0x12c1a000 0x0 0x1000>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon0 SCU0_CLK_GATE_UART4CLK>; + no-loopback-test; + status = "disabled"; + }; + + mbox0: mbox@12c1c200 { + compatible = "aspeed,ast2700-mailbox"; + reg = <0x0 0x12c1c200 0x0 0x100>, <0x0 0x12c1c300 0x0 0x100>; + reg-names = "tx", "rx"; + #mbox-cells = <1>; + }; + + mbox1: mbox@12c1c600 { + compatible = "aspeed,ast2700-mailbox"; + reg = <0x0 0x12c1c600 0x0 0x100>, <0x0 0x12c1c700 0x0 0x100>; + reg-names = "tx", "rx"; + #mbox-cells = <1>; + }; + }; + + soc1: soc@14000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x14000000 0x0 0x14000000 0x2 0xec000000>; + + fmc: spi@14000000 { + reg = <0x0 0x14000000 0x0 0xc4>, <0x1 0x00000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-fmc"; + status = "disabled"; + clocks = <&syscon1 SCU1_CLK_AHB>; + num-cs = <3>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + + flash@1 { + reg = <1>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + + flash@2 { + reg = <2>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi0: spi@14010000 { + reg = <0x0 0x14010000 0x0 0xc4>, <0x1 0x80000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-spi"; + status = "disabled"; + clocks = <&syscon1 SCU1_CLK_AHB>; + num-cs = <2>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + + flash@1 { + reg = <1>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi1: spi@14020000 { + reg = <0x0 0x14020000 0x0 0xc4>, <0x2 0x00000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-spi"; + status = "disabled"; + clocks = <&syscon1 SCU1_CLK_AHB>; + num-cs = <2>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + + flash@1 { + reg = <1>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + spi2: spi@14030000 { + reg = <0x0 0x14030000 0x0 0xc4>, <0x2 0x80000000 0x0 0x80000000>; + #address-cells = <1>; + #size-cells = <0>; + compatible = "aspeed,ast2700-spi"; + status = "disabled"; + clocks = <&syscon1 SCU1_CLK_AHB>; + resets = <&syscon1 SCU1_RESET_SPI2>; + num-cs = <2>; + + flash@0 { + reg = <0>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + + flash@1 { + reg = <1>; + compatible = "jedec,spi-nor"; + status = "disabled"; + }; + }; + + mdio0: mdio@14040000 { + compatible = "aspeed,ast2700-mdio"; + reg = <0 0x14040000 0 0x8>; + resets = <&syscon1 SCU1_RESET_MII>; + status = "disabled"; + }; + + mdio1: mdio@14040008 { + compatible = "aspeed,ast2700-mdio"; + reg = <0 0x14040008 0 0x8>; + resets = <&syscon1 SCU1_RESET_MII>; + status = "disabled"; + }; + + mdio2: mdio@14040010 { + compatible = "aspeed,ast2700-mdio"; + reg = <0 0x14040010 0 0x8>; + resets = <&syscon1 SCU1_RESET_MII>; + status = "disabled"; + }; + + mac0: ftgmac@14050000 { + compatible = "aspeed,ast2700-mac", "faraday,ftgmac100"; + reg = <0x0 0x14050000 0x0 0x200>; + clocks = <&syscon1 SCU1_CLK_GATE_MAC0CLK>; + resets = <&syscon1 SCU1_RESET_MAC0>; + status = "disabled"; + }; + + mac1: ftgmac@14060000 { + compatible = "aspeed,ast2700-mac", "faraday,ftgmac100"; + reg = <0x0 0x14060000 0x0 0x200>; + clocks = <&syscon1 SCU1_CLK_GATE_MAC1CLK>; + resets = <&syscon1 SCU1_RESET_MAC1>; + status = "disabled"; + }; + + mac2: ftgmac@14070000 { + compatible = "aspeed,ast2700-mac", "faraday,ftgmac100"; + reg = <0x0 0x14070000 0x0 0x200>; + clocks = <&syscon1 SCU1_CLK_GATE_MAC2CLK>; + resets = <&syscon1 SCU1_RESET_MAC2>; + status = "disabled"; + }; + + sdio_controller: sdc@14080000 { + compatible = "aspeed,ast2700-sd-controller"; + reg = <0 0x14080000 0 0x100>; + #address-cells = <1>; + #size-cells = <1>; + clocks = <&syscon1 SCU1_CLK_GATE_SDCLK>; + resets = <&syscon1 SCU1_RESET_SD>; + ranges = <0 0 0x14080000 0x10000>; + status = "disable"; + + sdhci: sdhci@100 { + compatible = "aspeed,ast2700-sdhci"; + reg = <0x100 0x100>; + sdhci,auto-cmd12; + clocks = <&syscon1 SCU1_CLK_GATE_SDCLK>; + }; + }; + + uhci1: usb@14110000 { + compatible = "aspeed,ast2700-uhci", "generic-uhci"; + reg = <0x0 0x14110000 0x0 0x100>; + #ports = <2>; + clocks = <&syscon1 SCU1_CLK_GATE_UHCICLK>; + resets = <&syscon1 SCU1_RESET_UHCI>; + status = "disabled"; + }; + + vhubc: usb-vhub@14120000 { + compatible = "aspeed,ast2700-usb-vhub"; + reg = <0x0 0x14120000 0x0 0x820>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTCUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTC_VHUB_EHCI>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + status = "disabled"; + }; + + ehci2: usb@14121000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x14121000 0x0 0x100>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTCUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTC_VHUB_EHCI>; + status = "disabled"; + }; + + vhubd: usb-vhub@14122000 { + compatible = "aspeed,ast2700-usb-vhub"; + reg = <0x0 0x14122000 0x0 0x820>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTDUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTD_VHUB_EHCI>; + aspeed,vhub-downstream-ports = <7>; + aspeed,vhub-generic-endpoints = <21>; + status = "disabled"; + }; + + ehci3: usb@14123000 { + compatible = "aspeed,ast2700-ehci", "generic-ehci"; + reg = <0x0 0x14123000 0x0 0x100>; + clocks = <&syscon1 SCU1_CLK_GATE_PORTDUSB2CLK>; + resets = <&syscon1 SCU1_RESET_PORTD_VHUB_EHCI>; + status = "disabled"; + }; + + syscon1: syscon@14c02000 { + compatible = "aspeed,ast2700-scu1", "syscon", "simple-mfd"; + reg = <0x0 0x14c02000 0x0 0x1000>; + ranges = <0x0 0x0 0x14c02000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + + pinctrl1: pinctrl@400 { + compatible = "aspeed,ast2700-soc1-pinctrl"; + reg = <0x400 0x2a0>; + }; + }; + + gpio1: gpio@14c0b000 { + compatible = "aspeed,ast2700-gpio"; + reg = <0x0 0x14c0b000 0x0 0x1000>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pinctrl1 0 0 216>; + ngpios = <216>; + clocks = <&syscon1 SCU1_CLK_AHB>; + }; + + intc1: interrupt-controller@14c18000 { + compatible = "aspeed,ast2700-intc1"; + reg = <0 0x14c18000 0 0x400>; + interrupt-controller; + interrupt-parent = <&intc0>; + #interrupt-cells = <1>; + }; + + uart0: serial@14c33000 { + compatible = "ns16550a"; + reg = <0x0 0x14c33000 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART0CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart1: serial@14c33100 { + compatible = "ns16550a"; + reg = <0x0 0x14c33100 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART1CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart2: serial@14c33200 { + compatible = "ns16550a"; + reg = <0x0 0x14c33200 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART2CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart3: serial@14c33300 { + compatible = "ns16550a"; + reg = <0x0 0x14c33300 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART3CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart5: serial@14c33400 { + compatible = "ns16550a"; + reg = <0x0 0x14c33400 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART5CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart6: serial@14c33500 { + compatible = "ns16550a"; + reg = <0x0 0x14c33500 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART6CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart7: serial@14c33600 { + compatible = "ns16550a"; + reg = <0x0 0x14c33600 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART7CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart8: serial@14c33700 { + compatible = "ns16550a"; + reg = <0x0 0x14c33700 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART8CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart9: serial@14c33800 { + compatible = "ns16550a"; + reg = <0x0 0x14c33800 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART9CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart10: serial@14c33900 { + compatible = "ns16550a"; + reg = <0x0 0x14c33900 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART10CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart11: serial@14c33a00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33a00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART11CLK>; + no-loopback-test; + status = "disabled"; + }; + + uart12: serial@14c33b00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33b00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_GATE_UART12CLK>; + clock-frequency = <1846154>; + no-loopback-test; + status = "disabled"; + }; + + uart13: serial@14c33c00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33c00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_UART13>; + no-loopback-test; + status = "disabled"; + }; + + uart14: serial@14c33d00 { + compatible = "ns16550a"; + reg = <0x0 0x14c33d00 0x0 0x100>; + reg-shift = <2>; + reg-io-width = <4>; + clocks = <&syscon1 SCU1_CLK_UART14>; + no-loopback-test; + status = "disabled"; + }; + + wdt0: watchdog@14c37000 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37000 0x0 0x80>; + status = "disabled"; + }; + + wdt1: watchdog@14c37080 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37080 0x0 0x80>; + status = "disabled"; + }; + + wdt2: watchdog@14c37100 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37100 0x0 0x80>; + status = "disabled"; + }; + + wdt3: watchdog@14c37180 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37180 0x0 0x80>; + status = "disabled"; + }; + + wdt4: watchdog@14c37200 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37200 0x0 0x80>; + status = "disabled"; + }; + + wdt5: watchdog@14c37280 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37280 0x0 0x80>; + status = "disabled"; + }; + + wdt6: watchdog@14c37300 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37300 0x0 0x80>; + status = "disabled"; + }; + + wdt7: watchdog@14c37380 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37380 0x0 0x80>; + status = "disabled"; + }; + + wdt_abr: watchdog@14c37400 { + compatible = "aspeed,ast2700-wdt"; + reg = <0x0 0x14c37400 0x0 0x80>; + status = "disabled"; + }; + + mbox2: mbox@14c39200 { + compatible = "aspeed,ast2700-mailbox"; + reg = <0x0 0x14c39200 0x0 0x100>, <0x0 0x14c39300 0x0 0x100>; + reg-names = "tx", "rx"; + #mbox-cells = <1>; + }; + + }; +}; diff --git a/arch/arm/dts/en7523-u-boot.dtsi b/arch/arm/dts/en7523-u-boot.dtsi index 62d1a724678..7866a3552e6 100644 --- a/arch/arm/dts/en7523-u-boot.dtsi +++ b/arch/arm/dts/en7523-u-boot.dtsi @@ -2,6 +2,9 @@ #include <dt-bindings/reset/airoha,en7523-reset.h> +/delete-node/ &gpio0; +/delete-node/ &gpio1; + / { reserved-memory { #address-cells = <1>; @@ -22,6 +25,26 @@ #reset-cells = <1>; }; + system-controller@1fbf0200 { + compatible = "syscon", "simple-mfd"; + reg = <0x1fbf0200 0xc0>; + + en7523_pinctrl: pinctrl { + compatible = "airoha,en7523-pinctrl"; + + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&en7523_pinctrl 0 12 30>; + }; + }; + eth: ethernet@1fb50000 { compatible = "airoha,en7523-eth"; reg = <0x1fb50000 0x2600>, diff --git a/arch/arm/dts/imx8mm-u-boot.dtsi b/arch/arm/dts/imx8mm-u-boot.dtsi index ab135fc8a47..50ecb6cad39 100644 --- a/arch/arm/dts/imx8mm-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-u-boot.dtsi @@ -82,25 +82,25 @@ }; ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; align-end = <4>; type = "blob-ext"; }; diff --git a/arch/arm/dts/imx8mn-u-boot.dtsi b/arch/arm/dts/imx8mn-u-boot.dtsi index 8993605af3c..690f56e65bb 100644 --- a/arch/arm/dts/imx8mn-u-boot.dtsi +++ b/arch/arm/dts/imx8mn-u-boot.dtsi @@ -137,7 +137,7 @@ ddr-1d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_imem.bin"; + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; #elif CONFIG_IMX8M_DDR4 filename = "ddr4_imem_1d_201810.bin"; #else @@ -149,7 +149,7 @@ ddr-1d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_1d_dmem.bin"; + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; #elif CONFIG_IMX8M_DDR4 filename = "ddr4_dmem_1d_201810.bin"; #else @@ -162,7 +162,7 @@ #if defined(CONFIG_IMX8M_LPDDR4) || defined(CONFIG_IMX8M_DDR4) ddr-2d-imem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_imem.bin"; + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; #else filename = "ddr4_imem_2d_201810.bin"; #endif @@ -172,7 +172,7 @@ ddr-2d-dmem-fw { #ifdef CONFIG_IMX8M_LPDDR4 - filename = "lpddr4_pmu_train_2d_dmem.bin"; + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; #else filename = "ddr4_dmem_2d_201810.bin"; #endif diff --git a/arch/arm/dts/imx8mq-u-boot.dtsi b/arch/arm/dts/imx8mq-u-boot.dtsi index ed2c704f2e5..b4deaa92160 100644 --- a/arch/arm/dts/imx8mq-u-boot.dtsi +++ b/arch/arm/dts/imx8mq-u-boot.dtsi @@ -96,25 +96,25 @@ }; ddr-1d-imem-fw { - filename = "lpddr4_pmu_train_1d_imem.bin"; + filename = "lpddr4_pmu_train_1d_imem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-1d-dmem-fw { - filename = "lpddr4_pmu_train_1d_dmem.bin"; + filename = "lpddr4_pmu_train_1d_dmem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-2d-imem-fw { - filename = "lpddr4_pmu_train_2d_imem.bin"; + filename = "lpddr4_pmu_train_2d_imem_202006.bin"; align-end = <4>; type = "blob-ext"; }; ddr-2d-dmem-fw { - filename = "lpddr4_pmu_train_2d_dmem.bin"; + filename = "lpddr4_pmu_train_2d_dmem_202006.bin"; align-end = <4>; type = "blob-ext"; }; diff --git a/arch/arm/dts/imx93-u-boot.dtsi b/arch/arm/dts/imx93-u-boot.dtsi index a84cdf2bc45..bd970c955cf 100644 --- a/arch/arm/dts/imx93-u-boot.dtsi +++ b/arch/arm/dts/imx93-u-boot.dtsi @@ -69,6 +69,9 @@ container; image0 = "a55", "bl31.bin", "0x204E0000"; image1 = "a55", "u-boot.bin", "0x80200000"; +#if defined(CONFIG_OPTEE) + image2 = "a55", "tee.bin", "0x96000000"; +#endif }; }; }; diff --git a/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi b/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi new file mode 100644 index 00000000000..92ec0d3efa3 --- /dev/null +++ b/arch/arm/dts/imx95-aquila-dev-u-boot.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* Copyright (c) Toradex */ + +#include "imx95-u-boot.dtsi" + +/ { + sysinfo { + compatible = "toradex,sysinfo"; + }; +}; + +&lpuart1 { + bootph-pre-ram; +}; + +&pinctrl_uart1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1 { + bootph-pre-ram; +}; + +&pinctrl_usdhc1_200mhz { + bootph-pre-ram; +}; + +&usb3 { + bootph-pre-ram; +}; + +&usb3_dwc3 { + bootph-pre-ram; + compatible = "fsl,imx95a-dwc3", "fsl,imx8mq-dwc3", "snps,dwc3"; +}; + +&usdhc1 { + bootph-pre-ram; +}; + diff --git a/arch/arm/dts/imx95-aquila-dev.dts b/arch/arm/dts/imx95-aquila-dev.dts new file mode 100644 index 00000000000..3df17700b63 --- /dev/null +++ b/arch/arm/dts/imx95-aquila-dev.dts @@ -0,0 +1,389 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + * https://www.toradex.com/products/carrier-board/aquila-development-board-kit + */ + +/dts-v1/; + +#include <dt-bindings/pwm/pwm.h> +#include <dt-bindings/usb/pd.h> +#include "imx95-aquila.dtsi" + +/ { + model = "Aquila iMX95 on Aquila Development Board"; + compatible = "toradex,aquila-imx95-dev", + "toradex,aquila-imx95", + "fsl,imx95"; + + aliases { + eeprom1 = &carrier_eeprom; + }; + + dp_1_connector: dp0-connector { + compatible = "dp-connector"; + dp-pwr-supply = <®_dp_3p3v>; + type = "full-size"; + + port { + dp_1_connector_in: endpoint { + remote-endpoint = <&dsi2dp_out>; + }; + }; + }; + + reg_carrier_1p8v: regulator-carrier-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-carrier 1V8"; + }; + + reg_dp_3p3v: regulator-dp-3p3v { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_21_dp>; + /* Aquila GPIO_21_DP */ + gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "DP_3V3"; + startup-delay-us = <10000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,mclk-fs = <256>; + simple-audio-card,name = "aquila-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack", + "IN1R", "Digital Mic"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Microphone", "Digital Mic", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + status = "okay"; +}; + +/* Aquila CTRL_WAKE1_MICO# */ +&aquila_key_wake { + status = "okay"; +}; + +&dsi2dp_out { + remote-endpoint = <&dp_1_connector_in>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + status = "okay"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + status = "okay"; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + status = "okay"; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-0 = <&pinctrl_flexspi1_4bit>, + <&pinctrl_qspi_cs1>; + + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <66000000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_8>; +}; + +&gpio4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_1>, + <&pinctrl_gpio_2>, + <&pinctrl_gpio_3>, + <&pinctrl_gpio_4>, + <&pinctrl_gpio_5>, + <&pinctrl_gpio_6>, + <&pinctrl_gpio_7>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + status = "okay"; + + fan_controller: fan@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + #pwm-cells = <2>; + + fan { + cooling-levels = <255>; + pwms = <&fan_controller 40000 PWM_POLARITY_INVERTED>; + }; + }; + + wm8904_1a: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2_mclk>; + clocks = <&scmi_clk IMX95_CLK_SAI2>; + clock-names = "mclk"; + #sound-dai-cells = <0>; + AVDD-supply = <®_carrier_1p8v>; + CPVDD-supply = <®_carrier_1p8v>; + DBVDD-supply = <®_carrier_1p8v>; + DCVDD-supply = <®_carrier_1p8v>; + MICVDD-supply = <®_carrier_1p8v>; + wlf,drc-cfg-names = "default", "peaklimiter"; + /* + * Config registers per name, respectively: + * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1 + * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1 + */ + wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>, + /bits/ 16 <0x04af 0x324b 0x0010 0x0408>; + /* GPIO1 = DMIC_CLK, don't touch others */ + wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>; + wlf,in1r-as-dmicdat2; + }; + + /* Current measurement into module VCC */ + hwmon@41 { + compatible = "ti,ina226"; + reg = <0x41>; + shunt-resistor = <5000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp1075"; + reg = <0x4f>; + }; + + /* USB-C OTG (TCPC USB PD PHY) */ + tcpc@52 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x52>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + + connector { + compatible = "usb-c-connector"; + data-role = "dual"; + op-sink-microwatt = <0>; + power-role = "dual"; + self-powered; + sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; + try-power-role = "sink"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec_con_hs: endpoint { + remote-endpoint = <&usb1_con_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec_con_ss: endpoint { + remote-endpoint = <&usb1_con_ss>; + }; + }; + }; + }; + }; + + carrier_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_2 */ +&i3c2 { + status = "okay"; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + status = "okay"; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + status = "okay"; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + /* I2C on DSI Connector Pin #4 and #6 */ + i2c_dsi_0: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* I2C on DSI Connector Pin #52 and #54 */ + i2c_dsi_1: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + status = "okay"; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + status = "okay"; +}; + +/* Aquila UART_4 */ +&lpuart2 { + status = "okay"; +}; + +/* Aquila UART_1 */ +&lpuart3 { + status = "okay"; +}; + +/* Aquila UART_2 as RS485 */ +&lpuart7 { + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; + + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + status = "okay"; +}; + +/* Aquila PWM_1 */ +&tpm3 { + status = "okay"; +}; + +/* Aquila PWM_2 */ +&tpm6 { + status = "okay"; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + status = "okay"; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + status = "okay"; +}; + +/* Aquila USB_1 */ +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + status = "okay"; + + port { + usb1_con_hs: endpoint { + remote-endpoint = <&typec_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + + status = "okay"; + + port { + usb1_con_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; + +/* Aquila SD_1 */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm/dts/imx95-aquila.dtsi b/arch/arm/dts/imx95-aquila.dtsi new file mode 100644 index 00000000000..69dc962a24a --- /dev/null +++ b/arch/arm/dts/imx95-aquila.dtsi @@ -0,0 +1,1160 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) Toradex + * + * https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 + */ + +#include <dt-bindings/net/ti-dp83867.h> +#include "imx95.dtsi" + +/ { + aliases { + can0 = &flexcan1; + can1 = &flexcan2; + can2 = &flexcan3; + can3 = &flexcan4; + eeprom0 = &som_eeprom; + ethernet0 = &enetc_port0; + i2c0 = &lpi2c3; + i2c1 = &lpi2c2; + i2c2 = &i3c2; + i2c3 = &lpi2c8; + i2c4 = &lpi2c4; + i2c6 = &lpi2c5; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + rtc0 = &rtc_i2c; + rtc1 = &scmi_bbm; + serial0 = &lpuart3; + serial1 = &lpuart7; + serial2 = &lpuart1; + serial3 = &lpuart2; + usb0 = &usb3; + usb1 = &usb2; + }; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + aquila_key_wake: gpio-key-wakeup { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_wake1_mico>; + + status = "disabled"; + + key-wakeup { + /* Aquila CTRL_WAKE1_MICO# */ + gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + label = "Wake Up"; + wakeup-source; + linux,code = <KEY_WAKEUP>; + }; + }; + + clk_dsi2dp_refclk: clock-dsi2dp-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + }; + + clk_dsi2dp_refclk_en: clock-dsi2dp-refclk-en { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ctrl_dp_clk_en>; + clocks = <&clk_dsi2dp_refclk>; + #clock-cells = <0>; + /* CTRL_DP_CLK_EN */ + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + }; + + clk_serdes_eth_ref: clock-serdes-eth-ref { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + /* CTRL_ETH_REF_CLK_STBY */ + enable-gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_LOW>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "On-module +V1.8"; + }; + + reg_dp_1p2v: regulator-dp-1p2v { + compatible = "regulator-fixed"; + /* CTRL_DP_BRIDGE_EN */ + gpios = <&som_gpio_expander_0 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "On-module +V1.2_DP"; + vin-supply = <®_1p8v>; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_1_EN */ + gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_1_EN"; + }; + + reg_usb2_vbus: regulator-usb2-vbus { + compatible = "regulator-fixed"; + /* Aquila USB_2_EN */ + gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-name = "USB_2_H_EN"; + }; + + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1_pwr_en>; + /* Aquila SD_1_PWR_EN */ + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "SD_1_PWR_EN"; + startup-delay-us = <20000>; + }; + + reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { + compatible = "regulator-gpio"; + /* PMIC_SD_1_VSEL */ + gpios = <&som_gpio_expander_1 9 GPIO_ACTIVE_HIGH>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + regulator-name = "PMIC_SD_1_VSEL"; + states = <1800000 0x1>, + <3300000 0x0>; + }; + + remoteproc-cm7 { + compatible = "fsl,imx95-cm7"; + mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>; + mbox-names = "tx", "rx", "rxdb"; + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux_cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0 0x3c000000>; + alloc-ranges = <0 0x80000000 0 0x7f000000>; + linux,cma-default; + }; + + m7_reserved: memory@80000000 { + reg = <0 0x80000000 0 0x1000000>; + no-map; + }; + + rsc_table: rsc-table@88220000 { + reg = <0 0x88220000 0 0x1000>; + no-map; + }; + + vdev0vring0: vdev0vring0@88000000 { + reg = <0 0x88000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@88008000 { + reg = <0 0x88008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@88010000 { + reg = <0 0x88010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@88018000 { + reg = <0 0x88018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer@88020000 { + compatible = "shared-dma-pool"; + reg = <0 0x88020000 0 0x100000>; + no-map; + }; + }; +}; + +/* Aquila ADC_[1-4] */ +&adc1 { + vref-supply = <®_1p8v>; +}; + +/* Aquila ETH_1 */ +&enetc_port0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enetc0>; + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; +}; + +/* Aquila CAN_1 */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Aquila CAN_2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* Aquila CAN_3 */ +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; +}; + +/* Aquila CAN_4 */ +&flexcan4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan4>; +}; + +/* Aquila QSPI_1 */ +&flexspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi1_8bit>, + <&pinctrl_qspi_cs1>; +}; + +&gpio1 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_C24", /* 10 */ + "", + "AQUILA_B17", + "CTRL_GPIO_EXP_INT#", + "AQUILA_B18"; + + status = "okay"; +}; + +&gpio2 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "AQUILA_B42", + "", + "AQUILA_B43"; +}; + +&gpio3 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "", + "", + "AQUILA_A11", + "", /* 20 */ + "AQUILA_B57", + "AQUILA_B19"; +}; + +&gpio4 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "", + "", + "", + "", + "AQUILA_C22", + "AQUILA_C21", + "AQUILA_C20", + "", /* 20 */ + "", + "", + "AQUILA_C23", + "AQUILA_D23", + "AQUILA_D24", + "", + "AQUILA_D25"; +}; + +&gpio5 { + gpio-line-names = "", /* 0 */ + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", /* 10 */ + "", + "", + "AQUILA_B44", + "AQUILA_B45"; +}; + +/* Aquila I2C_2 */ +&i3c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c2>; + i2c-scl-hz = <100000>; +}; + +/* Aquila I2C_1 */ +&lpi2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c2>; + pinctrl-1 = <&pinctrl_lpi2c2_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* On-module I2C - I2C_SOM */ +&lpi2c3 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c3>, <&pinctrl_ctrl_gpio_exp_int>; + pinctrl-1 = <&pinctrl_lpi2c3_gpio>, <&pinctrl_ctrl_gpio_exp_int>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + + status = "okay"; + + som_gpio_expander_0: gpio@20 { + compatible = "nxp,pcal6408"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C38", /* 0 */ + "PCIE_2_RESET#", + "AQUILA_B77", + "USB_2_H_EN", + "BT_DISABLE#", + "WIFI_DISABLE#", + "CTRL_ETH_REF_CLK_STBY", + "CTRL_DP_BRIDGE_EN"; + }; + + som_gpio_expander_1: gpio@21 { + compatible = "nxp,pcal6416"; + reg = <0x21>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gpio1>; + interrupts = <13 IRQ_TYPE_LEVEL_LOW>; + #gpio-cells = <2>; + gpio-controller; + gpio-line-names = + "AQUILA_C1", /* 0 */ + "AQUILA_C2", + "AQUILA_C3", + "AQUILA_C4", + "AQUILA_C36", + "AQUILA_B74", + "AQUILA_B75", + "USB_2_H_OC#", + "AQUILA_B81", + "PMIC_SD_1_VSEL", + "ETH_1_INT#", /* 10 */ + "CTRL_TPM_INT#", + "SPI_2_CS2_TPM", + "PCIE_WAKE_WIFI#", + "WIFI_WAKE_BT", + "WIFI_WAKEUP_HOST"; + }; + + som_dsi2dp_bridge: bridge@2c { + compatible = "ti,sn65dsi86"; + reg = <0x2c>; + clocks = <&clk_dsi2dp_refclk_en>; + clock-names = "refclk"; + vcc-supply = <®_dp_1p2v>; + vcca-supply = <®_dp_1p2v>; + vccio-supply = <®_1p8v>; + vpll-supply = <®_1p8v>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dsi2dp_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + + dsi2dp_out: endpoint { + data-lanes = <3 2 1 0>; + }; + }; + }; + }; + + rtc_i2c: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + temperature-sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + + som_eeprom: eeprom@50 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Aquila I2C_4_CSI1 */ +&lpi2c4 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c4>; + pinctrl-1 = <&pinctrl_lpi2c4_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_6 */ +&lpi2c5 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila I2C_3_DSI1/I2C_5_CSI2 */ +&lpi2c8 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_lpi2c8>; + pinctrl-1 = <&pinctrl_lpi2c8_gpio>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + scl-gpios = <&gpio2 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio2 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +/* Aquila SPI_2 */ +&lpspi4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi4>; + cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>, + <&som_gpio_expander_1 12 GPIO_ACTIVE_LOW>; + + status = "okay"; + + som_tpm: tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0x1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; + /* + * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz + * here as lpspi4's per-clock (2x the max speed) is 24 MHz. + */ + spi-max-frequency = <12000000>; + }; +}; + +/* Aquila SPI_1 */ +&lpspi6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi6>; + cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +}; + +/* Aquila UART_3, used as the Linux Console */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +/* Aquila UART_4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; +}; + +/* Aquila UART_1 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; +}; + +/* Aquila UART_2 */ +&lpuart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + uart-has-rtscts; +}; + +&mu7 { + status = "okay"; +}; + +/* Aquila ETH_2_XGMII_MDIO, shared between all ethernet ports */ +&netc_emdio { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_emdio>; + + status = "okay"; + + ethphy1: ethernet-phy@1 { + reg = <1>; + interrupt-parent = <&som_gpio_expander_1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; + }; +}; + +&netcmix_blk_ctrl { + status = "okay"; +}; + +&netc_blk_ctrl { + status = "okay"; +}; + +&netc_timer { + status = "okay"; +}; + +/* Aquila PCIE_1 */ +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpios = <&som_gpio_expander_0 0 GPIO_ACTIVE_LOW>; +}; + +/* On-module Wi-Fi or Aquila PCIE_2 */ +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + +/* Aquila I2S_1 */ +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>, + <&scmi_clk IMX95_CLK_AUDIOPLL2>, + <&scmi_clk IMX95_CLK_SAI2>; + assigned-clock-parents = <0>, <0>, <0>, <0>, + <&scmi_clk IMX95_CLK_AUDIOPLL1>; + assigned-clock-rates = <3932160000>, + <3612672000>, <393216000>, + <361267200>, <12288000>; + #sound-dai-cells = <0>; + fsl,sai-mclk-direction-output; +}; + +&scmi_bbm { + linux,code = <KEY_POWER>; +}; + +&thermal_zones { + /* PF09 Main PMIC */ + pf09-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 2>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_ARM PMIC */ + pf53-arm-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 4>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; + + /* PF53 VDD_SOC PMIC */ + pf53-soc-thermal { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&scmi_sensor 3>; + + trips { + trip0 { + hysteresis = <2000>; + temperature = <155000>; + type = "critical"; + }; + }; + }; +}; + +/* Aquila PWM_1 */ +&tpm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +/* Aquila PWM_2 */ +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; +}; + +/* Aquila PWM_3_DSI and PWM_4_DP */ +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3_dsi>, <&pinctrl_pwm4_dp>; +}; + +/* Aquila USB_2, optional Bluetooth USB */ +&usb2 { + dr_mode = "host"; + vbus-supply = <®_usb2_vbus>; +}; + +/* Aquila USB_1 */ +&usb3 { + fsl,disable-port-power-control; +}; + +&usb3_dwc3 { + dr_mode = "otg"; + adp-disable; + hnp-disable; + srp-disable; + usb-role-switch; +}; + +&usb3_phy { + vbus-supply = <®_usb1_vbus>; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + no-sdio; + no-sd; + + status = "okay"; +}; + +/* Aquila SD_1 */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_sd1_cd_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_sd1_cd_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_sd1_cd_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_usdhc2_vqmmc>; +}; + +&wdog3 { + fsl,ext-reset-output; + + status = "okay"; +}; + +&scmi_iomuxc { + /* Aquila CTRL_WAKE1_MICO# */ + pinctrl_ctrl_wake1_mico: ctrlwake1micogrp { + fsl,pins = <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x31e>; /* Aquila D6 */ + }; + + pinctrl_ctrl_dp_clk_en: dpclkengrp { + fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x11e>; /* CTRL_DP_CLK_EN */ + }; + + /* Aquila ETH_2_XGMII_MDIO */ + pinctrl_emdio: emdiogrp { + fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x57e>, /* Aquila B90 */ + <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x97e>; /* Aquila B89 */ + }; + + /* Aquila ETH_1 */ + pinctrl_enetc0: enetc0grp { + fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */ + <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */ + <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */ + <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */ + <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */ + <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */ + <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */ + <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */ + <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */ + <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */ + <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */ + <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */ + }; + + /* Aquila CAN_1 */ + pinctrl_flexcan1: flexcan1grp { + fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* Aquila B48 */ + <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* Aquila B49 */ + }; + + /* Aquila CAN_2 */ + pinctrl_flexcan2: flexcan2grp { + fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* Aquila B50 */ + <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* Aquila B51 */ + }; + + /* Aquila CAN_3 */ + pinctrl_flexcan3: flexcan3grp { + fsl,pins = <IMX95_PAD_CCM_CLKO3__CAN3_TX 0x39e>, /* Aquila B53 */ + <IMX95_PAD_CCM_CLKO4__CAN3_RX 0x39e>; /* Aquila B54 */ + }; + + /* Aquila CAN_4 */ + pinctrl_flexcan4: flexcan4grp { + fsl,pins = <IMX95_PAD_GPIO_IO04__CAN4_TX 0x39e>, /* Aquila B55 */ + <IMX95_PAD_GPIO_IO05__CAN4_RX 0x39e>; /* Aquila B56 */ + }; + + /* Aquila QSPI_1 (4 bit) */ + pinctrl_flexspi1_4bit: flexspi14bitgrp { + fsl,pins = <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>, /* Aquila B65 */ + <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>, /* Aquila B68 */ + <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>, /* Aquila B67 */ + <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>, /* Aquila B61 */ + <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>, /* Aquila B60 */ + <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>; /* Aquila B63 */ + }; + + /* Aquila QSPI_1 (8 bit) */ + pinctrl_flexspi1_8bit: flexspi18bitgrp { + fsl,pins = <IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x3fe>, /* Aquila B65 */ + <IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x3fe>, /* Aquila B68 */ + <IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x3fe>, /* Aquila B67 */ + <IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x3fe>, /* Aquila B61 */ + <IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x3fe>, /* Aquila B60 */ + <IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x3fe>, /* Aquila B70 */ + <IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x3fe>, /* Aquila B71 */ + <IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x3fe>, /* Aquila B72 */ + <IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x3fe>, /* Aquila B73 */ + <IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x3fe>; /* Aquila B63 */ + }; + + /* Aquila GPIO_01 */ + pinctrl_gpio_1: gpio1grp { + fsl,pins = <IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x31e>; /* Aquila D23 */ + }; + + /* Aquila GPIO_02 */ + pinctrl_gpio_2: gpio2grp { + fsl,pins = <IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x31e>; /* Aquila D24 */ + }; + + /* Aquila GPIO_03 */ + pinctrl_gpio_3: gpio3grp { + fsl,pins = <IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x31e>; /* Aquila D25 */ + }; + + /* Aquila GPIO_04 */ + pinctrl_gpio_4: gpio4grp { + fsl,pins = <IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x31e>; /* Aquila C20 */ + }; + + /* Aquila GPIO_05 */ + pinctrl_gpio_5: gpio5grp { + fsl,pins = <IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x31e>; /* Aquila C21 */ + }; + + /* Aquila GPIO_06 */ + pinctrl_gpio_6: gpio6grp { + fsl,pins = <IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x31e>; /* Aquila C22 */ + }; + + /* Aquila GPIO_07 */ + pinctrl_gpio_7: gpio7grp { + fsl,pins = <IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x31e>; /* Aquila C23 */ + }; + + /* Aquila GPIO_08 */ + pinctrl_gpio_8: gpio8grp { + fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x31e>; /* Aquila C24 */ + }; + + /* Aquila GPIO_09_CSI_1 */ + pinctrl_gpio_9_csi_1: gpio9csi1grp { + fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x31e>; /* Aquila B17 */ + }; + + /* Aquila GPIO_10_CSI_1 */ + pinctrl_gpio_10_csi_1: gpio10csi1grp { + fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* Aquila B18 */ + }; + + /* Aquila GPIO_11_CSI_1 */ + pinctrl_gpio_11_csi_1: gpio11csi1grp { + fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x31e>; /* Aquila A11*/ + }; + + /* Aquila GPIO_12_CSI_1 */ + pinctrl_gpio_12_csi_1: gpio12csi1grp { + fsl,pins = <IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x31e>; /* Aquila B19 */ + }; + + /* Aquila GPIO_17_DSI_1 */ + pinctrl_gpio_17_dsi_1: gpio17dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x31e>; /* Aquila B42 */ + }; + + /* Aquila GPIO_18_DSI_1 */ + pinctrl_gpio_18_dsi_1: gpio18dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x31e>; /* Aquila B43 */ + }; + + /* Aquila GPIO_19_DSI_1 */ + pinctrl_gpio_19_dsi_1: gpio19dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x31e>; /* Aquila B44 */ + }; + + /* Aquila GPIO_20_DSI_1 */ + pinctrl_gpio_20_dsi_1: gpio20dsi1grp { + fsl,pins = <IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x31e>; /* Aquila B45 */ + }; + + /* Aquila GPIO_21_DP */ + pinctrl_gpio_21_dp: gpio21dpgrp { + fsl,pins = <IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x31e>; /* Aquila B57 */ + }; + + pinctrl_ctrl_gpio_exp_int: gpioexpintgrp { + fsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x31e>; /* CTRL_GPIO_EXP_INT# */ + }; + + /* Aquila I2C_2 */ + pinctrl_i3c2: i3c2cgrp { + fsl,pins = <IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40001186>, /* Aquila C17 */ + <IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40001186>; /* Aquila C16 */ + }; + + /* Aquila I2C_1 as GPIOs */ + pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* Aquila D8 */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* Aquila D7 */ + }; + + /* Aquila I2C_1 */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* Aquila D8 */ + <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* Aquila D7 */ + }; + + /* On-module I2C as GPIOs */ + pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* I2C_SOM_SDA */ + <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* I2C_SOM_SCL */ + }; + + /* On-module I2C */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* I2C_SOM_SDA */ + <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* I2C_SOM_SCL */ + }; + + /* Aquila I2C_4_CSI1 as GPIO */ + pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>, /* Aquila A12 */ + <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>; /* Aquila A13 */ + }; + + /* Aquila I2C_4_CSI1 */ + pinctrl_lpi2c4: lpi2c4grp { + fsl,pins = <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>, /* Aquila A12 */ + <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>; /* Aquila A13 */ + }; + + /* Aquila I2C_6 as GPIO */ + pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* Aquila C18 */ + <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* Aquila C19 */ + }; + + /* Aquila I2C_6 */ + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* Aquila C18 */ + <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* Aquila C19 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 as GPIO */ + pinctrl_lpi2c8_gpio: lpi2c8gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x40001b9e>, /* Aquila C5/B40 */ + <IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x40001b9e>; /* Aquila C6/B41 */ + }; + + /* Aquila I2C_3_DSI1/I2C_5_CSI2 */ + pinctrl_lpi2c8: lpi2c8grp { + fsl,pins = <IMX95_PAD_GPIO_IO12__LPI2C8_SDA 0x40001b9e>, /* Aquila C5/B40 */ + <IMX95_PAD_GPIO_IO13__LPI2C8_SCL 0x40001b9e>; /* Aquila C6/B41 */ + }; + + /* Aquila SPI_2 */ + pinctrl_lpspi4: lpspi4grp { + fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x3fe>, /* Aquila D16 */ + <IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x3fe>, /* Aquila D15 */ + <IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x3fe>, /* Aquila D17 */ + <IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x3fe>; /* Aquila D14 */ + }; + + /* Aquila SPI_1 */ + pinctrl_lpspi6: lpspi6grp { + fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x3fe>, /* Aquila D9 */ + <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* Aquila D10 */ + <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* Aquila D11 */ + <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* Aquila D12 */ + }; + + /* Aquila PCIE_1 */ + pinctrl_pcie0: pcie0grp { + fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40001b1e>; /* Aquila C37 */ + }; + + /* Aquila PCIE_2 */ + pinctrl_pcie1: pcie1grp { + fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x40001b1e>; /* Aquila C34 */ + }; + + /* Aquila QSPI_1_CS1# */ + pinctrl_qspi_cs1: qspics1grp { + fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>; /* Aquila B66 */ + }; + + /* Aquila QSPI_1_CS2# as GPIO */ + pinctrl_qspi_cs2_gpio: qspics2gpiogrp { + fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x3fe>; /* Aquila B62 */ + }; + + /* Aquila I2S_1 */ + pinctrl_sai2: sai2grp { + fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x11e>, /* Aquila B21 */ + <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x11e>, /* Aquila B20 */ + <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x11e>, /* Aquila B23 */ + <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x11e>; /* Aquila B22 */ + }; + + pinctrl_sai2_mclk: sai2mclkgrp { + fsl,pins = <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x31e>; /* Aquila B24 */ + }; + + /* Aquila SD_1_CD# as GPIO */ + pinctrl_sd1_cd_gpio: sd1cdgpiogrp { + fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* Aquila A1 */ + }; + + /* Aquila SD_1_PWR_EN */ + pinctrl_sd1_pwr_en: sd1pwrengpiogrp { + fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* Aquila A6 */ + }; + + /* Aquila PWM_1 */ + pinctrl_pwm1: tpm3ch3grp { + fsl,pins = <IMX95_PAD_GPIO_IO24__TPM3_CH3 0x11e>; /* Aquila C25 */ + }; + + /* Aquila PWM_3_DSI as GPIO */ + pinctrl_pwm3_dsi_gpio: tpm5ch0gpiogrp { + fsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x11e>; /* Aquila B46 */ + }; + + /* Aquila PWM_3_DSI */ + pinctrl_pwm3_dsi: tpm5ch0grp { + fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* Aquila B46 */ + }; + + /* Aquila PWM_4_DP */ + pinctrl_pwm4_dp: tpm5ch3grp { + fsl,pins = <IMX95_PAD_GPIO_IO26__TPM5_CH3 0x11e>; /* Aquila B58 */ + }; + + /* Aquila PWM_2 */ + pinctrl_pwm2: tpm6ch0grp { + fsl,pins = <IMX95_PAD_GPIO_IO08__TPM6_CH0 0x11e>; /* Aquila C26 */ + }; + + /* Aquila UART_3 */ + pinctrl_uart1: uart1grp { + fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, /* Aquila D20 */ + <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>; /* Aquila D19 */ + }; + + /* Aquila UART_4 */ + pinctrl_uart2: uart2grp { + fsl,pins = <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>, /* Aquila D22 */ + <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>; /* Aquila D21 */ + }; + + /* Aquila UART_1 */ + pinctrl_uart3: uart3grp { + fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX 0x31e>, /* Aquila B37 */ + <IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>, /* Aquila B35 */ + <IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 0x31e>, /* Aquila B36 */ + <IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 0x31e>; /* Aquila B38 */ + }; + + /* Aquila UART_2 */ + pinctrl_uart7: uart7grp { + fsl,pins = <IMX95_PAD_GPIO_IO36__LPUART7_TX 0x31e>, /* Aquila B33 */ + <IMX95_PAD_GPIO_IO37__LPUART7_RX 0x31e>, /* Aquila B31 */ + <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e>, /* Aquila B32 */ + <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>; /* Aquila B34 */ + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* eMMC_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* eMMC_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* eMMC_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* eMMC_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* eMMC_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* eMMC_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* eMMC_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* eMMC_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* eMMC_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* eMMC_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* eMMC_STROBE */ + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* eMMC_CLK */ + <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* eMMC_CMD */ + <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* eMMC_DATA0 */ + <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* eMMC_DATA1 */ + <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* eMMC_DATA2 */ + <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* eMMC_DATA3 */ + <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* eMMC_DATA4 */ + <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* eMMC_DATA5 */ + <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* eMMC_DATA6 */ + <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* eMMC_DATA7 */ + <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* eMMC_STROBE */ + }; + + /* Aquila SD_1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* Aquila A5 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* Aquila A7 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* Aquila A3 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* Aquila A2 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* Aquila A10 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* Aquila A8 */ + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* Aquila A5 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* Aquila A7 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* Aquila A3 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* Aquila A2 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* Aquila A10 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* Aquila A8 */ + }; + + pinctrl_usdhc2_sleep: usdhc2-sleepgrp { + fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* Aquila A5 */ + <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* Aquila A7 */ + <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* Aquila A3 */ + <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* Aquila A2 */ + <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* Aquila A10 */ + <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* Aquila A8 */ + }; +}; diff --git a/arch/arm/dts/imx952-u-boot.dtsi b/arch/arm/dts/imx952-u-boot.dtsi index 28f47244356..80399e6ff2a 100644 --- a/arch/arm/dts/imx952-u-boot.dtsi +++ b/arch/arm/dts/imx952-u-boot.dtsi @@ -181,12 +181,7 @@ bootph-all; }; -&gpio1 { - reg = <0 0x47400000 0 0x1000>, <0 0x47400040 0 0x40>; -}; - &gpio2 { - reg = <0 0x43810000 0 0x1000>, <0 0x43810040 0 0x40>; bootph-pre-ram; /* * Use one SPL/U-Boot for mx952evk and mx952evkrpmsg, since GPIO2 @@ -196,17 +191,14 @@ }; &gpio3 { - reg = <0 0x43820000 0 0x1000>, <0 0x43820040 0 0x40>; bootph-pre-ram; }; &gpio4 { - reg = <0 0x43840000 0 0x1000>, <0 0x43840040 0 0x40>; bootph-pre-ram; }; &gpio5 { - reg = <0 0x43850000 0 0x1000>, <0 0x43850040 0 0x40>; bootph-pre-ram; }; diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts index e3d363a8e39..d1fe7efd006 100644 --- a/arch/arm/dts/k3-am642-r5-evm.dts +++ b/arch/arm/dts/k3-am642-r5-evm.dts @@ -23,3 +23,13 @@ clocks = <&clk_200mhz>; clock-names = "clk_xin"; }; + +&main_uart1_pins_default { + bootph-pre-ram; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + bootph-pre-ram; + status="okay"; +}; diff --git a/arch/arm/dts/k3-am642-r5-sk.dts b/arch/arm/dts/k3-am642-r5-sk.dts index 27f3e87fb90..19435cd1f5c 100644 --- a/arch/arm/dts/k3-am642-r5-sk.dts +++ b/arch/arm/dts/k3-am642-r5-sk.dts @@ -18,3 +18,13 @@ &serdes_wiz0 { status = "okay"; }; + +&main_uart1_pins_default { + bootph-pre-ram; +}; + +/* Main UART1 is used for TIFS firmware logs */ +&main_uart1 { + bootph-pre-ram; + status="okay"; +}; diff --git a/arch/arm/dts/rk3528-u-boot.dtsi b/arch/arm/dts/rk3528-u-boot.dtsi index a18d33b3d36..31345df6295 100644 --- a/arch/arm/dts/rk3528-u-boot.dtsi +++ b/arch/arm/dts/rk3528-u-boot.dtsi @@ -23,7 +23,7 @@ reg = <0x0 0xffc50000 0x0 0x200>; }; - otp: nvmem@ffce0000 { + otp: efuse@ffce0000 { compatible = "rockchip,rk3528-otp"; reg = <0x0 0xffce0000 0x0 0x4000>; }; diff --git a/arch/arm/dts/rk356x-u-boot.dtsi b/arch/arm/dts/rk356x-u-boot.dtsi index 738b9673d35..d09dab35b31 100644 --- a/arch/arm/dts/rk356x-u-boot.dtsi +++ b/arch/arm/dts/rk356x-u-boot.dtsi @@ -21,15 +21,9 @@ bootph-all; }; - otp: nvmem@fe38c000 { + otp: efuse@fe38c000 { compatible = "rockchip,rk3568-otp"; reg = <0x0 0xfe38c000 0x0 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - - cpu_id: id@a { - reg = <0x0a 0x10>; - }; }; }; diff --git a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi index dcda4f99d6e..0fbbb50fc5a 100644 --- a/arch/arm/dts/rk3588-jaguar-u-boot.dtsi +++ b/arch/arm/dts/rk3588-jaguar-u-boot.dtsi @@ -21,6 +21,12 @@ bootph-some-ram; }; +&gpio0 { + /* Need gpio0 in SPL for spl_board_init() to control GPIO0_D0 */ + /* TODO: once we have a U-Boot TPL, use bootph-pre-sram; */ + bootph-pre-ram; +}; + &gpio2 { bootph-pre-ram; bootph-some-ram; diff --git a/arch/arm/dts/zynqmp-clk-ccf.dtsi b/arch/arm/dts/zynqmp-clk-ccf.dtsi index 482f432ba7f..877962df2b3 100644 --- a/arch/arm/dts/zynqmp-clk-ccf.dtsi +++ b/arch/arm/dts/zynqmp-clk-ccf.dtsi @@ -3,7 +3,7 @@ * Clock specification for Xilinx ZynqMP * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -49,6 +49,14 @@ clock-frequency = <27000000>; clock-output-names = "aux_ref_clk"; }; + + rtc_clk: rtc-clk { + bootph-all; + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "rtc_clk"; + }; }; &zynqmp_firmware { @@ -302,3 +310,8 @@ <&zynqmp_clk DP_AUDIO_REF>, <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */ }; + +&rtc { + clocks = <&rtc_clk>; + clock-names = "rtc"; +}; diff --git a/arch/arm/dts/zynqmp-dlc21-revA.dts b/arch/arm/dts/zynqmp-dlc21-revA.dts index d48b6f3a8ec..83c39ce1a26 100644 --- a/arch/arm/dts/zynqmp-dlc21-revA.dts +++ b/arch/arm/dts/zynqmp-dlc21-revA.dts @@ -90,6 +90,9 @@ status = "okay"; phy-handle = <&phy0>; phy-mode = "sgmii"; /* DTG generates this properly 1512 */ + nvmem-cells = <ð_mac>; + nvmem-cell-names = "mac-address"; + mdio: mdio { #address-cells = <1>; #size-cells = <0>; @@ -119,10 +122,10 @@ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */ "", "", /* 78 - 79 */ - "", "", "", "", "", /* 80 - 84 */ - "", "", "", "", "", /* 85 - 89 */ - "", "", "", "", "", /* 90 - 94 */ - "", "VCCO_500_RBIAS", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ + "", "", "", "", "PMOD_0", /* 80 - 84 */ + "PMOD_1", "PMOD_2", "PMOD_3", "PMOD_4", "PMOD_5", /* 85 -89 */ + "PMOD_6", "PMOD_7", "", "", "", /* 90 - 94 */ + "", "", "VCCO_501_RBIAS", "VCCO_502_RBIAS", "VCCO_500_RBIAS_LED", /* 95 - 99 */ "VCCO_501_RBIAS_LED", "VCCO_502_RBIAS_LED", "SYSCTLR_VCCINT_EN", "SYSCTLR_VCC_IO_SOC_EN", "SYSCTLR_VCC_PMC_EN", /* 100 - 104 */ "", "", "", "", "", /* 105 - 109 */ "SYSCTLR_VCCO_500_EN", "SYSCTLR_VCCO_501_EN", "SYSCTLR_VCCO_502_EN", "SYSCTLR_VCCO_503_EN", "SYSCTLR_VCC1V8_EN", /* 110 - 114 */ @@ -153,6 +156,12 @@ eeprom: eeprom@50 { /* u46 */ compatible = "atmel,24c32"; reg = <0x50>; + #address-cells = <1>; + #size-cells = <1>; + + eth_mac: mac-address@20 { + reg = <0x20 0x6>; + }; }; /* u138 - TUSB320IRWBR - for USB-C */ }; diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index aebceb20736..824d189d246 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -51,83 +51,103 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vcc-soc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>; }; ina226-vcc-pmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc-pslp { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>; }; ina226-vcc-psfp { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>; }; ina226-vccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>; }; ina226-vccaux-pmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>; }; ina226-vcco-500 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>; }; ina226-vcco-501 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>; }; ina226-vcco-502 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>; }; ina226-vcco-503 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>; }; ina226-vcc-1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>; }; ina226-vcc-3v3 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>; }; ina226-vcc-1v2-ddr4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>; }; ina226-vcc-1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtyavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>; }; ina226-mgtyavtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>; }; ina226-mgtyvccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>; }; }; diff --git a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts index 7c9764c31f7..bf4ea35067c 100644 --- a/arch/arm/dts/zynqmp-g-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-g-a2197-00-revA.dts @@ -40,26 +40,32 @@ ina226-u74 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; ina226-u78 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u82 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u82 0>, <&u82 1>, <&u82 2>, <&u82 3>; }; ina226-u84 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts index f9d7528ff2e..2bf6af9c065 100644 --- a/arch/arm/dts/zynqmp-m-a2197-01-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-01-revA.dts @@ -45,27 +45,33 @@ ina226-vcc-aux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; ina226-vcc0v6-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc0v6_lp4 0>, <&vcc0v6_lp4 1>, <&vcc0v6_lp4 2>, <&vcc0v6_lp4 3>; }; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts index b4da0d341c3..fbeae394c62 100644 --- a/arch/arm/dts/zynqmp-m-a2197-02-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-02-revA.dts @@ -45,22 +45,27 @@ ina226-vcc-aux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; diff --git a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts index 729efd4098c..33a86fad604 100644 --- a/arch/arm/dts/zynqmp-m-a2197-03-revA.dts +++ b/arch/arm/dts/zynqmp-m-a2197-03-revA.dts @@ -45,22 +45,27 @@ ina226-vcc-aux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_aux 0>, <&vcc_aux 1>, <&vcc_aux 2>, <&vcc_aux 3>; }; ina226-vcc-ram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>; }; ina226-vcc1v1-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>; }; ina226-vcc1v2-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2_lp4 0>, <&vcc1v2_lp4 1>, <&vcc1v2_lp4 2>, <&vcc1v2_lp4 3>; }; ina226-vdd1-1v8-lp4 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vdd1_1v8_lp4 0>, <&vdd1_1v8_lp4 1>, <&vdd1_1v8_lp4 2>, <&vdd1_1v8_lp4 3>; }; diff --git a/arch/arm/dts/zynqmp-sc-revB.dts b/arch/arm/dts/zynqmp-sc-revB.dts index 6181072c1da..afaecfa5a27 100644 --- a/arch/arm/dts/zynqmp-sc-revB.dts +++ b/arch/arm/dts/zynqmp-sc-revB.dts @@ -136,7 +136,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <1>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; @@ -194,93 +193,97 @@ /* QSPI should also have PINCTRL setup */ flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <40000000>; /* 40MHz */ - partition@0 { - label = "Image Selector"; - reg = <0x0 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@80000 { - label = "Image Selector Golden"; - reg = <0x80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@100000 { - label = "Persistent Register"; - reg = <0x100000 0x20000>; /* 128KB */ - }; - partition@120000 { - label = "Persistent Register Backup"; - reg = <0x120000 0x20000>; /* 128KB */ - }; - partition@140000 { - label = "Open_1"; - reg = <0x140000 0xc0000>; /* 768KB */ - }; - partition@200000 { - label = "Image A (FSBL, PMU, ATF, U-Boot)"; - reg = <0x200000 0xd00000>; /* 13MB */ - }; - partition@f00000 { - label = "ImgSel Image A Catch"; - reg = <0xf00000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@f80000 { - label = "Image B (FSBL, PMU, ATF, U-Boot)"; - reg = <0xf80000 0xd00000>; /* 13MB */ - }; - partition@1c80000 { - label = "ImgSel Image B Catch"; - reg = <0x1c80000 0x80000>; /* 512KB */ - read-only; - lock; - }; - partition@1d00000 { - label = "Open_2"; - reg = <0x1d00000 0x100000>; /* 1MB */ - }; - partition@1e00000 { - label = "Recovery Image"; - reg = <0x1e00000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2000000 { - label = "Recovery Image Backup"; - reg = <0x2000000 0x200000>; /* 2MB */ - read-only; - lock; - }; - partition@2200000 { - label = "U-Boot storage variables"; - reg = <0x2200000 0x20000>; /* 128KB */ - }; - partition@2220000 { - label = "U-Boot storage variables backup"; - reg = <0x2220000 0x20000>; /* 128KB */ - }; - partition@2240000 { - label = "SHA256"; - reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ - read-only; - lock; - }; - partition@2280000 { - label = "Secure OS Storage"; - reg = <0x2280000 0x20000>; /* 128KB */ - }; - partition@22a0000 { - label = "User"; - reg = <0x22a0000 0x1d60000>; /* 29.375 MB */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "Image Selector"; + reg = <0x0 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@80000 { + label = "Image Selector Golden"; + reg = <0x80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@100000 { + label = "Persistent Register"; + reg = <0x100000 0x20000>; /* 128KB */ + }; + partition@120000 { + label = "Persistent Register Backup"; + reg = <0x120000 0x20000>; /* 128KB */ + }; + partition@140000 { + label = "Open_1"; + reg = <0x140000 0xc0000>; /* 768KB */ + }; + partition@200000 { + label = "Image A (FSBL, PMU, ATF, U-Boot)"; + reg = <0x200000 0xd00000>; /* 13MB */ + }; + partition@f00000 { + label = "ImgSel Image A Catch"; + reg = <0xf00000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@f80000 { + label = "Image B (FSBL, PMU, ATF, U-Boot)"; + reg = <0xf80000 0xd00000>; /* 13MB */ + }; + partition@1c80000 { + label = "ImgSel Image B Catch"; + reg = <0x1c80000 0x80000>; /* 512KB */ + read-only; + lock; + }; + partition@1d00000 { + label = "Open_2"; + reg = <0x1d00000 0x100000>; /* 1MB */ + }; + partition@1e00000 { + label = "Recovery Image"; + reg = <0x1e00000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2000000 { + label = "Recovery Image Backup"; + reg = <0x2000000 0x200000>; /* 2MB */ + read-only; + lock; + }; + partition@2200000 { + label = "U-Boot storage variables"; + reg = <0x2200000 0x20000>; /* 128KB */ + }; + partition@2220000 { + label = "U-Boot storage variables backup"; + reg = <0x2220000 0x20000>; /* 128KB */ + }; + partition@2240000 { + label = "SHA256"; + reg = <0x2240000 0x40000>; /* 256B but 256KB sector */ + read-only; + lock; + }; + partition@2280000 { + label = "Secure OS Storage"; + reg = <0x2280000 0x20000>; /* 128KB */ + }; + partition@22a0000 { + label = "User"; + reg = <0x22a0000 0x1d60000>; /* 29.375 MB */ + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-sc-revC.dts b/arch/arm/dts/zynqmp-sc-revC.dts index 530a4a5f080..b9b192f0986 100644 --- a/arch/arm/dts/zynqmp-sc-revC.dts +++ b/arch/arm/dts/zynqmp-sc-revC.dts @@ -23,7 +23,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { /* ADI1300 */ - #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <1>; adi,rx-internal-delay-ps = <2400>; diff --git a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso index e94b784e8e1..7212ee9df86 100644 --- a/arch/arm/dts/zynqmp-sc-vek280-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vek280-revA.dtso @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP VEK280 revA * - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -13,8 +13,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-vek280-revA", - "xlnx,zynqmp-vek280", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vek280-revA", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso index a3983f330d0..a57e9b50b20 100644 --- a/arch/arm/dts/zynqmp-sc-vek280-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vek280-revB.dtso @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP VEK280 revB * - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -10,6 +10,5 @@ #include "zynqmp-sc-vek280-revA.dtso" &{/} { - compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-vek280-revB", - "xlnx,zynqmp-vek280", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vek280-revB", "xlnx,zynqmp-sc-vek280", "xlnx,zynqmp"; }; diff --git a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso index fd25731b0b4..2fe35596143 100644 --- a/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vhk158-revA.dtso @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP VHK158 revA * * (C) Copyright 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-vhk158-revA", - "xlnx,zynqmp-vhk158", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vhk158-revA", "xlnx,zynqmp-sc-vhk158", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso index 4d0f10e13c3..58be0e1c890 100644 --- a/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vm-p-m1369-00-revA.dtso @@ -2,7 +2,7 @@ /* * dts file for Xilinx ZynqMP VM-P-M1369-00 * - * Copyright (C) 2024, Advanced Micro Devices, Inc. + * Copyright (C) 2024-2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -18,66 +18,82 @@ ina226-u19 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_soc_ina 0>, <&vcc_soc_ina 1>, <&vcc_soc_ina 2>; }; ina226-u287 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>; }; ina226-u288 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_pslp_ina 0>, <&vcc_pslp_ina 1>, <&vcc_pslp_ina 2>; }; ina226-u289 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>; }; ina226-u290 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_pmc_ina 0>, <&vccaux_pmc_ina 1>, <&vccaux_pmc_ina 2>; }; ina226-u291 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>; }; ina226-u292 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>; }; ina226-u293 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>; }; ina226-u294 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>; }; ina226-u295 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ddr5_rdimm_ina 0>, <&vcc_ddr5_rdimm_ina 1>, <&vcc_ddr5_rdimm_ina 2>; }; ina226-u298 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&lp5_1v0_ina 0>, <&lp5_1v0_ina 1>, <&lp5_1v0_ina 2>; }; ina226-u296 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_fmc_ina 0>, <&vcc_fmc_ina 1>, <&vcc_fmc_ina 2>; }; ina226-u299 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>; }; ina226-u300 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>; }; ina226-u301 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>; }; ina226-u297 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_mipi_ina 0>, <&vcc_mipi_ina 1>, <&vcc_mipi_ina 2>; }; }; @@ -393,7 +409,7 @@ }; /* connected via J425 connector - ucd90320: power-sequencer@73 { // u16 + ucd90320: power-sequencer@73 { // u16 compatible = "ti,ucd90320"; reg = <0x73>; };*/ diff --git a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso index 5a4e5f09250..39be25be8f6 100644 --- a/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vn-p-b2197-00-revA.dtso @@ -22,66 +22,82 @@ ina226-u1700 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_ram_ina 0>, <&vcc_ram_ina 1>, <&vcc_ram_ina 2>; }; ina226-u1732 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc_lpd_ina 0>, <&vcc_lpd_ina 1>, <&vcc_lpd_ina 2>; }; ina226-u1733 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_ina 0>, <&vccaux_ina 1>, <&vccaux_ina 2>; }; ina226-u1736 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccaux_lpd_ina 0>, <&vccaux_lpd_ina 1>, <&vccaux_lpd_ina 2>; }; ina226-u1737 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_500_ina 0>, <&vcco_500_ina 1>, <&vcco_500_ina 2>; }; ina226-u1739 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_501_ina 0>, <&vcco_501_ina 1>, <&vcco_501_ina 2>; }; ina226-u1741 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_502_ina 0>, <&vcco_502_ina 1>, <&vcco_502_ina 2>; }; ina226-u1743 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_503_ina 0>, <&vcco_503_ina 1>, <&vcco_503_ina 2>; }; ina226-u1745 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_700_ina 0>, <&vcco_700_ina 1>, <&vcco_700_ina 2>; }; ina226-u1747 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcco_706_ina 0>, <&vcco_706_ina 1>, <&vcco_706_ina 2>; }; ina226-u1750 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>yp_avcc_ina 0>, <>yp_avcc_ina 1>, <>yp_avcc_ina 2>; }; ina226-u1752 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>yp_avtt_ina 0>, <>yp_avtt_ina 1>, <>yp_avtt_ina 2>; }; ina226-u1754 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>yp_avccaux_ina 0>, <>yp_avccaux_ina 1>, <>yp_avccaux_ina 2>; }; ina226-u1756 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avcc_ina 0>, <>m_avcc_ina 1>, <>m_avcc_ina 2>; }; ina226-u1758 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avtt_ina 0>, <>m_avtt_ina 1>, <>m_avtt_ina 2>; }; ina226-u1760 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <>m_avccaux_ina 0>, <>m_avccaux_ina 1>, <>m_avccaux_ina 2>; }; diff --git a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso index 29b3a73fde0..ae0691c0127 100644 --- a/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk120-revB.dtso @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP VPK120 revB * * (C) Copyright 2021 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-vpk120-revB", - "xlnx,zynqmp-vpk120", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vpk120-revB", "xlnx,zynqmp-sc-vpk120", "xlnx,zynqmp"; }; &i2c0 { diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso index 10466ce99de..9b6534f6383 100644 --- a/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk180-revA.dtso @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP VPK180 revA * * (C) Copyright 2021 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-vpk180-revA", - "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vpk180-revA", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso index 74e1c5c6dc9..941d26c025a 100644 --- a/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso +++ b/arch/arm/dts/zynqmp-sc-vpk180-revB.dtso @@ -1,9 +1,9 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for Xilinx ZynqMP VPK180 revA + * dts file for Xilinx ZynqMP VPK180 revB * * (C) Copyright 2021 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -14,8 +14,7 @@ /plugin/; &{/} { - compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-vpk180-revB", - "xlnx,zynqmp-vpk180", "xlnx,zynqmp"; + compatible = "xlnx,zynqmp-sc-vpk180-revB", "xlnx,zynqmp-sc-vpk180", "xlnx,zynqmp"; vc7_xin: vc7-xin { compatible = "fixed-clock"; diff --git a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso index 8342479b108..a32073fa040 100644 --- a/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kd-g-revA.dtso @@ -50,6 +50,24 @@ gpio-controller; gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &can0 { @@ -76,7 +94,6 @@ slg7xl45106: gpio@11 { /* u13 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "", @@ -124,6 +141,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -148,7 +167,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@8 { /* Adin u31 */ - #phy-cells = <1>; compatible = "ethernet-phy-id0283.bc30"; reg = <8>; adi,rx-internal-delay-ps = <2000>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index db042ffb4f3..31b3c3582c2 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -66,6 +66,7 @@ #clock-cells = <0>; clock-frequency = <25000000>; }; + dpcon { compatible = "dp-connector"; label = "P11"; @@ -85,6 +86,24 @@ gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>, <&slg7xl45106 4 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -105,7 +124,6 @@ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", @@ -196,6 +214,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub_1>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -233,6 +253,8 @@ peer-hub = <&hub1_3_0>; i2c-bus = <&hub_2>; reset-gpios = <&slg_delay 1 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -265,7 +287,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@4 { /* u81 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <4>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; @@ -277,7 +298,6 @@ reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; phy1: ethernet-phy@8 { /* u36 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <8>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index e3567d0abfe..f1114a35aae 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -86,6 +86,24 @@ gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>, <&slg7xl45106 4 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */ @@ -106,7 +124,6 @@ slg7xl45106: gpio@11 { /* u19 - reset logic */ compatible = "dlg,slg7xl45106"; reg = <0x11>; - label = "resetchip"; gpio-controller; #gpio-cells = <2>; gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B", @@ -197,6 +214,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub_1>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -234,6 +253,8 @@ peer-hub = <&hub1_3_0>; i2c-bus = <&hub_2>; reset-gpios = <&slg_delay 1 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -266,7 +287,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@4 { /* u81 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <4>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; @@ -278,7 +298,6 @@ reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>; }; phy1: ethernet-phy@8 { /* u36 */ - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <8>; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index f93c7460a55..967548744d5 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -85,6 +85,24 @@ gpio-controller; gpios = <&gpio 44 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -169,6 +187,8 @@ reg = <1>; peer-hub = <&hub_3_0>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -209,7 +229,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { - #phy-cells = <1>; reg = <1>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; @@ -227,23 +246,23 @@ status = "okay"; pinctrl_gpio0_default: gpio0-default { - conf { - groups = "gpio0_38_grp"; - bias-pull-up; - power-source = <IO_STANDARD_LVCMOS18>; - }; + conf { + groups = "gpio0_38_grp"; + bias-pull-up; + power-source = <IO_STANDARD_LVCMOS18>; + }; - mux { - groups = "gpio0_38_grp"; - function = "gpio0"; - }; + mux { + groups = "gpio0_38_grp"; + function = "gpio0"; + }; - conf-tx { - pins = "MIO38"; - bias-disable; - output-enable; - }; - }; + conf-tx { + pins = "MIO38"; + bias-disable; + output-enable; + }; + }; pinctrl_uart1_default: uart1-default { conf { @@ -402,9 +421,9 @@ }; &gpio { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio0_default>; + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio0_default>; }; &uart1 { diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index 70de6933600..0fa5a990adc 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * dts file for KV260 revA Carrier Card + * dts file for KV260 revB Carrier Card * * (C) Copyright 2020 - 2022, Xilinx, Inc. * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. @@ -81,6 +81,24 @@ gpio-controller; gpios = <&gpio 44 GPIO_ACTIVE_LOW>; }; + + vdd_usb_hub: regulator-vdd-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb_hub"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd2_usb_hub: regulator-vdd2-usb-hub { + compatible = "regulator-fixed"; + regulator-name = "vdd2_usb_hub"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + }; }; &i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */ @@ -156,6 +174,8 @@ peer-hub = <&hub_3_0>; i2c-bus = <&hub>; reset-gpios = <&slg_delay 0 10000 10000>; + vdd-supply = <&vdd_usb_hub>; + vdd2-supply = <&vdd2_usb_hub>; }; /* 3.0 hub on port 2 */ @@ -200,7 +220,6 @@ #size-cells = <0>; phy0: ethernet-phy@1 { - #phy-cells = <1>; reg = <1>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; diff --git a/arch/arm/dts/zynqmp-sm-k24-revA.dts b/arch/arm/dts/zynqmp-sm-k24-revA.dts index 653bd936226..34ee6af801d 100644 --- a/arch/arm/dts/zynqmp-sm-k24-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k24-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SM-K24 RevA * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2022, Advanced Micro Devices, Inc. + * (C) Copyright 2022-2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -21,3 +21,8 @@ reg = <0 0 0 0x80000000>; }; }; + +&cma { + size = <0x0 0x4000000>; + alignment = <0x0 0x4000000>; +}; diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 0abec77b3f3..c7fe253244f 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP SM-K26 rev2/1/B/A * * (C) Copyright 2020 - 2021, Xilinx, Inc. - * (C) Copyright 2023 - 2024, Advanced Micro Devices, Inc. + * (C) Copyright 2023 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -61,6 +61,15 @@ reg = <0x0 0x7ff00000 0x0 0x100000>; no-map; }; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; }; gpio-keys { diff --git a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts index 2037686b9b4..1dc0414b33d 100644 --- a/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts +++ b/arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts @@ -63,23 +63,27 @@ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <166000000>; - #address-cells = <1>; - #size-cells = <1>; - partition@0 { - label = "qspi-boot-bin"; - reg = <0x00000 0x60000>; - }; - partition@60000 { - label = "qspi-u-boot-itb"; - reg = <0x60000 0x100000>; - }; - partition@160000 { - label = "qspi-u-boot-env"; - reg = <0x160000 0x20000>; - }; - partition@200000 { - label = "qspi-rootfs"; - reg = <0x200000 0x1e00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "qspi-boot-bin"; + reg = <0x00000 0x60000>; + }; + partition@60000 { + label = "qspi-u-boot-itb"; + reg = <0x60000 0x100000>; + }; + partition@160000 { + label = "qspi-u-boot-env"; + reg = <0x160000 0x20000>; + }; + partition@200000 { + label = "qspi-rootfs"; + reg = <0x200000 0x1e00000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts index e9c6d249a8d..94167770ed6 100644 --- a/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts +++ b/arch/arm/dts/zynqmp-vp-x-a2785-00-revA.dts @@ -88,15 +88,19 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* u285 - mt25qu512abb8e12 512Mib */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; /* maybe 4 here */ spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; - partition@0 { /* for testing purpose */ - label = "qspi"; - reg = <0 0x4000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi"; + reg = <0 0x4000000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-vpk120-revA.dts b/arch/arm/dts/zynqmp-vpk120-revA.dts index bd1e2557187..3e461d9c4d0 100644 --- a/arch/arm/dts/zynqmp-vpk120-revA.dts +++ b/arch/arm/dts/zynqmp-vpk120-revA.dts @@ -88,15 +88,19 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* mt25qu512abb8e12 512Mib */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; - partition@0 { /* for testing purpose */ - label = "qspi"; - reg = <0 0x4000000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi"; + reg = <0 0x4000000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1232-revA.dts b/arch/arm/dts/zynqmp-zc1232-revA.dts index 9dcb9095371..f0e2a0b4588 100644 --- a/arch/arm/dts/zynqmp-zc1232-revA.dts +++ b/arch/arm/dts/zynqmp-zc1232-revA.dts @@ -31,6 +31,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { @@ -40,28 +55,32 @@ &qspi { status = "okay"; flash@0 { - compatible = "m25p80", "jedec,spi-nor"; /* 32MB FIXME */ - #address-cells = <1>; - #size-cells = <1>; + compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1254-revA.dts b/arch/arm/dts/zynqmp-zc1254-revA.dts index cf3e9583204..e92caefd3aa 100644 --- a/arch/arm/dts/zynqmp-zc1254-revA.dts +++ b/arch/arm/dts/zynqmp-zc1254-revA.dts @@ -32,6 +32,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { @@ -42,27 +57,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts index 32f317f3df4..2897c423f82 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP zc1751-xm015-dc1 * * (C) Copyright 2015 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -41,6 +41,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + clock_si5338_0: clk27 { /* u55 SI5338-GM */ compatible = "fixed-clock"; #clock-cells = <0>; @@ -357,28 +372,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts index e3d5cf972e8..0b1185d862c 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm016-dc2.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP zc1751-xm016-dc2 * * (C) Copyright 2015 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -39,6 +39,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &can0 { @@ -138,8 +153,6 @@ nand@0 { reg = <0x0>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; @@ -147,35 +160,39 @@ nand-ecc-strength = <24>; nand-on-flash-bbt; - partition@0 { /* for testing purpose */ - label = "nand-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; nand@1 { reg = <0x1>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; @@ -183,29 +200,35 @@ nand-ecc-strength = <24>; nand-on-flash-bbt; - partition@0 { /* for testing purpose */ - label = "nand1-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand1-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand1-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand1-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand1-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand1-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; }; @@ -503,15 +526,18 @@ pinctrl-0 = <&pinctrl_spi0_default>; spi0_flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "sst,sst25wf080", "jedec,spi-nor"; spi-max-frequency = <50000000>; reg = <0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "spi0-data"; - reg = <0x0 0x100000>; + partition@0 { + label = "spi0-data"; + reg = <0x0 0x100000>; + }; }; }; }; @@ -523,15 +549,18 @@ pinctrl-0 = <&pinctrl_spi1_default>; spi1_flash0: flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash"; spi-max-frequency = <20000000>; reg = <0>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; - partition@0 { - label = "spi1-data"; - reg = <0x0 0x84000>; + partition@0 { + label = "spi1-data"; + reg = <0x0 0x84000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts index a8856c20f5b..bfcc92cedfa 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm017-dc3.dts @@ -39,6 +39,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + clock_si5338_2: clk26 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -133,8 +148,6 @@ nand@0 { reg = <0x0>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-0"; @@ -142,65 +155,74 @@ nand-ecc-strength = <24>; nand-on-flash-bbt; - partition@0 { /* for testing purpose */ - label = "nand-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "nand-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; nand@1 { reg = <0x1>; - #address-cells = <0x2>; - #size-cells = <0x1>; nand-ecc-mode = "hw"; nand-rb = <0>; label = "main-storage-1"; nand-ecc-step-size = <1024>; nand-ecc-strength = <24>; nand-on-flash-bbt; + partitions { + compatible = "fixed-partitions"; + #address-cells = <2>; + #size-cells = <1>; - partition@0 { /* for testing purpose */ - label = "nand1-fsbl-uboot"; - reg = <0x0 0x0 0x400000>; - }; - partition@1 { /* for testing purpose */ - label = "nand1-linux"; - reg = <0x0 0x400000 0x1400000>; - }; - partition@2 { /* for testing purpose */ - label = "nand1-device-tree"; - reg = <0x0 0x1800000 0x400000>; - }; - partition@3 { /* for testing purpose */ - label = "nand1-rootfs"; - reg = <0x0 0x1c00000 0x1400000>; - }; - partition@4 { /* for testing purpose */ - label = "nand1-bitstream"; - reg = <0x0 0x3000000 0x400000>; - }; - partition@5 { /* for testing purpose */ - label = "nand1-misc"; - reg = <0x0 0x3400000 0xfcc00000>; + partition@0 { /* for testing purpose */ + label = "nand1-fsbl-uboot"; + reg = <0x0 0x0 0x400000>; + }; + partition@1 { /* for testing purpose */ + label = "nand1-linux"; + reg = <0x0 0x400000 0x1400000>; + }; + partition@2 { /* for testing purpose */ + label = "nand1-device-tree"; + reg = <0x0 0x1800000 0x400000>; + }; + partition@3 { /* for testing purpose */ + label = "nand1-rootfs"; + reg = <0x0 0x1c00000 0x1400000>; + }; + partition@4 { /* for testing purpose */ + label = "nand1-bitstream"; + reg = <0x0 0x3000000 0x400000>; + }; + partition@5 { /* for testing purpose */ + label = "nand1-misc"; + reg = <0x0 0x3400000 0xfcc00000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts index 3b03b39e456..9b59952993f 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts @@ -38,6 +38,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &can0 { @@ -174,27 +189,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts index 53aa3dca1dc..722b2e833b4 100644 --- a/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts +++ b/arch/arm/dts/zynqmp-zc1751-xm019-dc5.dts @@ -37,6 +37,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &fpd_dma_chan1 { diff --git a/arch/arm/dts/zynqmp-zcu100-revC.dts b/arch/arm/dts/zynqmp-zcu100-revC.dts index 4ec8a400494..81353b60b38 100644 --- a/arch/arm/dts/zynqmp-zcu100-revC.dts +++ b/arch/arm/dts/zynqmp-zcu100-revC.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU100 revC * * (C) Copyright 2016 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> * Nathalie Chan King Choy @@ -47,6 +47,21 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -61,6 +76,7 @@ iio-hwmon { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>, <&xilinx_ams 3>, <&xilinx_ams 4>, <&xilinx_ams 5>, <&xilinx_ams 6>, <&xilinx_ams 7>, <&xilinx_ams 8>, @@ -120,6 +136,7 @@ ina226 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index 6b1aea95e65..4d5f4754171 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU102 RevA * * (C) Copyright 2015 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -45,6 +45,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -68,74 +83,92 @@ ina226-u76 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; @@ -217,7 +250,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@21 { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <21>; ti,rx-internal-delay = <0x8>; @@ -987,28 +1019,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts index 3c28130909b..bad59d7b1d2 100644 --- a/arch/arm/dts/zynqmp-zcu102-revB.dts +++ b/arch/arm/dts/zynqmp-zcu102-revB.dts @@ -19,7 +19,6 @@ phy-handle = <&phyc>; mdio: mdio { phyc: ethernet-phy@c { - #phy-cells = <0x1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu104-revA.dts b/arch/arm/dts/zynqmp-zcu104-revA.dts index 0bfeed4293c..4479ff73514 100644 --- a/arch/arm/dts/zynqmp-zcu104-revA.dts +++ b/arch/arm/dts/zynqmp-zcu104-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -43,6 +43,21 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + clock_8t49n287_5: clk125 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -126,7 +141,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; @@ -453,27 +467,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu104-revC.dts b/arch/arm/dts/zynqmp-zcu104-revC.dts index a7387f4a0e6..0f1b1fd92a7 100644 --- a/arch/arm/dts/zynqmp-zcu104-revC.dts +++ b/arch/arm/dts/zynqmp-zcu104-revC.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU104 * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -43,8 +43,24 @@ reg = <0x0 0x0 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + ina226 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>; }; @@ -131,7 +147,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; @@ -465,27 +480,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 7b1097579fc..ad76159084e 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU106 * * (C) Copyright 2016 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -45,6 +45,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -68,74 +83,92 @@ ina226-u76 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>; }; ina226-u77 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u78 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>; }; ina226-u87 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>; }; ina226-u85 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>; }; ina226-u86 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>; }; ina226-u93 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>; }; ina226-u88 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>; }; ina226-u15 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>; }; ina226-u92 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; ina226-u81 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>; }; ina226-u80 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>; }; ina226-u84 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>; }; ina226-u16 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>; }; ina226-u65 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u74 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>; }; ina226-u75 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>; }; @@ -217,7 +250,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; reg = <0xc>; compatible = "ethernet-phy-id2000.a231"; ti,rx-internal-delay = <0x8>; @@ -981,28 +1013,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x4000000 0x4000000>; /* 64MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu111-revA.dts b/arch/arm/dts/zynqmp-zcu111-revA.dts index ba1b6339100..a9a47360237 100644 --- a/arch/arm/dts/zynqmp-zcu111-revA.dts +++ b/arch/arm/dts/zynqmp-zcu111-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU111 * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -45,6 +45,21 @@ /* Another 4GB connected to PL */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -68,58 +83,72 @@ ina226-u67 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>; }; ina226-u59 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>; }; ina226-u61 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>; }; ina226-u60 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>; }; ina226-u64 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>; }; ina226-u69 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>; }; ina226-u66 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>; }; ina226-u65 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>; }; ina226-u63 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>; }; ina226-u3 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>; }; ina226-u71 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>; }; ina226-u77 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>; }; ina226-u73 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>; }; ina226-u79 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>; }; @@ -189,7 +218,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; @@ -804,28 +832,32 @@ num-cs = <2>; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0>, <1>; parallel-memories = /bits/ 64 <0x10000000 0x10000000>; /* 256MB */ spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu1275-revA.dts b/arch/arm/dts/zynqmp-zcu1275-revA.dts index cc9f5b16025..1a49ae3ba4e 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revA.dts @@ -32,6 +32,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { @@ -46,27 +61,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu1275-revB.dts b/arch/arm/dts/zynqmp-zcu1275-revB.dts index f78da036280..1b6f7a605d6 100644 --- a/arch/arm/dts/zynqmp-zcu1275-revB.dts +++ b/arch/arm/dts/zynqmp-zcu1275-revB.dts @@ -35,6 +35,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { @@ -73,27 +88,31 @@ status = "okay"; flash@0 { compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ - #address-cells = <1>; - #size-cells = <1>; reg = <0x0>; spi-tx-bus-width = <1>; spi-rx-bus-width = <1>; spi-max-frequency = <108000000>; /* Based on DC1 spec */ - partition@0 { /* for testing purpose */ - label = "qspi-fsbl-uboot"; - reg = <0x0 0x100000>; - }; - partition@100000 { /* for testing purpose */ - label = "qspi-linux"; - reg = <0x100000 0x500000>; - }; - partition@600000 { /* for testing purpose */ - label = "qspi-device-tree"; - reg = <0x600000 0x20000>; - }; - partition@620000 { /* for testing purpose */ - label = "qspi-rootfs"; - reg = <0x620000 0x5e0000>; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { /* for testing purpose */ + label = "qspi-fsbl-uboot"; + reg = <0x0 0x100000>; + }; + partition@100000 { /* for testing purpose */ + label = "qspi-linux"; + reg = <0x100000 0x500000>; + }; + partition@600000 { /* for testing purpose */ + label = "qspi-device-tree"; + reg = <0x600000 0x20000>; + }; + partition@620000 { /* for testing purpose */ + label = "qspi-rootfs"; + reg = <0x620000 0x5e0000>; + }; }; }; }; diff --git a/arch/arm/dts/zynqmp-zcu1285-revA.dts b/arch/arm/dts/zynqmp-zcu1285-revA.dts index 86a3217f9ab..b2d71f0f455 100644 --- a/arch/arm/dts/zynqmp-zcu1285-revA.dts +++ b/arch/arm/dts/zynqmp-zcu1285-revA.dts @@ -36,6 +36,21 @@ device_type = "memory"; reg = <0x0 0x0 0x0 0x80000000>; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; }; &dcc { diff --git a/arch/arm/dts/zynqmp-zcu208-revA.dts b/arch/arm/dts/zynqmp-zcu208-revA.dts index 888f711aad9..60231d7d3a2 100644 --- a/arch/arm/dts/zynqmp-zcu208-revA.dts +++ b/arch/arm/dts/zynqmp-zcu208-revA.dts @@ -43,6 +43,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -66,61 +81,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; @@ -176,7 +205,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu216-revA.dts b/arch/arm/dts/zynqmp-zcu216-revA.dts index ccdbf8967aa..bfe6f97a760 100644 --- a/arch/arm/dts/zynqmp-zcu216-revA.dts +++ b/arch/arm/dts/zynqmp-zcu216-revA.dts @@ -43,6 +43,21 @@ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -66,61 +81,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; @@ -183,7 +212,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu670-revA.dts b/arch/arm/dts/zynqmp-zcu670-revA.dts index 058d6b2e648..08e88745477 100644 --- a/arch/arm/dts/zynqmp-zcu670-revA.dts +++ b/arch/arm/dts/zynqmp-zcu670-revA.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU670 (67DR) * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -46,6 +46,21 @@ /* Another 4GB connected to PL */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -69,61 +84,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; @@ -185,7 +214,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp-zcu670-revB.dts b/arch/arm/dts/zynqmp-zcu670-revB.dts index 010d412b202..5c9195239f1 100644 --- a/arch/arm/dts/zynqmp-zcu670-revB.dts +++ b/arch/arm/dts/zynqmp-zcu670-revB.dts @@ -3,7 +3,7 @@ * dts file for Xilinx ZynqMP ZCU670 (67DR) revB * * (C) Copyright 2017 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2026, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -46,6 +46,21 @@ /* Another 4GB connected to PL */ }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + cma: linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x8000000>; + alignment = <0x0 0x8000000>; + alloc-ranges = <0x0 0x0 0x0 0x80000000>; + linux,cma-default; + }; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -69,61 +84,75 @@ ina226-vccint { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; }; ina226-vccint-io-bram { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>; }; ina226-vcc1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>; }; ina226-vcc1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>; }; ina226-vadj-fmc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>; }; ina226-mgtavcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>; }; ina226-mgt1v2 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>; }; ina226-mgt1v8 { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>; }; ina226-vccint-ams { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>; }; ina226-dac-avtt { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>; }; ina226-dac-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>; }; ina226-adc-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>; }; ina226-adc-avccaux { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>; }; ina226-dac-avcc { compatible = "iio-hwmon"; + status = "disabled"; io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>; }; @@ -185,7 +214,6 @@ #address-cells = <1>; #size-cells = <0>; phy0: ethernet-phy@c { - #phy-cells = <1>; compatible = "ethernet-phy-id2000.a231"; reg = <0xc>; ti,rx-internal-delay = <0x8>; diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 13cfca66657..c225eb219f4 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1006,7 +1006,6 @@ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "alarm", "sec"; - calibration = <0x7FFF>; }; sata: ahci@fd0c0000 { diff --git a/arch/arm/include/asm/arch-aspeed/fmc_hdr.h b/arch/arm/include/asm/arch-aspeed/fmc_hdr.h new file mode 100644 index 00000000000..c60277e1a81 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/fmc_hdr.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#ifndef __ASM_AST2700_FMC_HDR_H__ +#define __ASM_AST2700_FMC_HDR_H__ + +#include <linux/types.h> + +#define HDR_MAGIC 0x48545341 /* ASTH */ +#define HDR_PB_MAX 30 + +enum prebuilt_type { + PBT_END_MARK = 0x0, + + PBT_DDR4_PMU_TRAIN_IMEM, + PBT_DDR4_PMU_TRAIN_DMEM, + PBT_DDR4_2D_PMU_TRAIN_IMEM, + PBT_DDR4_2D_PMU_TRAIN_DMEM, + PBT_DDR5_PMU_TRAIN_IMEM, + PBT_DDR5_PMU_TRAIN_DMEM, + PBT_DP_FW, + PBT_UEFI_X64_AST2700, + + PBT_NUM +}; + +struct fmc_hdr_preamble { + u32 magic; + u32 version; +}; + +struct fmc_hdr_body { + u32 fmc_size; + union { + struct { + u32 type; + u32 size; + } pbs[0]; + u32 raz[29]; + }; +}; + +struct fmc_hdr { + struct fmc_hdr_preamble preamble; + struct fmc_hdr_body body; +} __packed; + +int fmc_hdr_get_prebuilt(u32 type, u32 *ofst, u32 *size); + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/platform.h b/arch/arm/include/asm/arch-aspeed/platform.h index 589abd4a3f6..82699c03c00 100644 --- a/arch/arm/include/asm/arch-aspeed/platform.h +++ b/arch/arm/include/asm/arch-aspeed/platform.h @@ -18,8 +18,36 @@ #define ASPEED_DRAM_BASE 0x80000000 #define ASPEED_SRAM_BASE 0x10000000 #define ASPEED_SRAM_SIZE 0x16000 +#elif defined(CONFIG_ASPEED_AST2700) +#define ASPEED_CPU_AHBC_BASE 0x12000000 +#define ASPEED_CPU_REVISION_ID 0x12C02000 +#define ASPEED_CPU_SCU_BASE 0x12C02000 +#define ASPEED_CPU_HW_STRAP1 0x12C02010 +#define ASPEED_CPU_RESET_LOG1 0x12C02050 +#define ASPEED_CPU_RESET_LOG2 0x12C02060 +#define ASPEED_CPU_RESET_LOG3 0x12C02070 +#define ASPEED_MAC_COUNT 3 +#define ASPEED_DRAM_BASE 0x400000000 +#define ASPEED_SRAM_BASE 0x10000000 +#define ASPEED_SRAM_SIZE 0x20000 +#define ASPEED_FMC_REG_BASE 0x14000000 +#define ASPEED_FMC_CS0_BASE 0x100000000 +#define ASPEED_FMC_CS0_SIZE 0x80000000 +#define ASPEED_IO_MAC0_BASE 0x14050000 +#define ASPEED_IO_MAC1_BASE 0x14060000 +#define ASPEED_IO_AHBC_BASE 0x140b0000 +#define ASPEED_IO_REVISION_ID 0x14C02000 +#define CHIP_AST2700A1_ID_MASK BIT(16) +#define ASPEED_IO_SCU_BASE 0x14C02000 +#define ASPEED_IO_HW_STRAP1 0x14C02010 +#define ASPEED_IO_RESET_LOG1 0x14C02050 +#define ASPEED_IO_RESET_LOG2 0x14C02060 +#define ASPEED_IO_RESET_LOG3 0x14C02070 +#define ASPEED_IO_RESET_LOG4 0x14C02080 +#define ASPEED_IO_GPIO_BASE 0x14C0B000 +#define ASPEED_WDTA_BASE 0x14C37400 #else -#err "Unrecognized Aspeed platform." +#error "Unrecognized Aspeed platform." #endif #endif diff --git a/arch/arm/include/asm/arch-aspeed/scu.h b/arch/arm/include/asm/arch-aspeed/scu.h new file mode 100644 index 00000000000..1aa7d38bace --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/scu.h @@ -0,0 +1,145 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef __ASM_AST2700_SCU_H__ +#define __ASM_AST2700_SCU_H__ + +/* SCU0: CPU-die SCU */ +#define SCU0_HWSTRAP 0x010 +#define SCU0_HWSTRAP_DIS_RVAS BIT(30) +#define SCU0_HWSTRAP_DIS_WDTFULL BIT(25) +#define SCU0_HWSTRAP_DISARMICE_TZ BIT(22) +#define SCU0_HWSTRAP_DISABLE_XHCI BIT(21) +#define SCU0_HWSTRAP_BOOTEMMCSPEED BIT(20) +#define SCU0_HWSTRAP_VGA_CC BIT(18) +#define SCU0_HWSTRAP_EN_OPROM BIT(17) +#define SCU0_HWSTRAP_DISARMICE BIT(16) +#define SCU0_HWSTRAP_TSPRSNTSEL BIT(9) +#define SCU0_HWSTRAP_DISDEBUG BIT(8) +#define SCU0_HWSTRAP_HCLKHPLL BIT(7) +#define SCU0_HWSTRAP_HCLKSEL GENMASK(6, 5) +#define SCU0_HWSTRAP_CPUHPLL BIT(4) +#define SCU0_HWSTRAP_HPLLFREQ GENMASK(3, 2) +#define SCU0_HWSTRAP_BOOTSPI BIT(1) +#define SCU0_HWSTRAP_HWSTRAP_DISCPU BIT(0) +#define SCU0_DBGCTL 0x0c8 +#define SCU0_DBGCTL_MASK GENMASK(14, 0) +#define SCU0_DBGCTL_UARTDBG BIT(1) +#define SCU0_RSTCTL1 0x200 +#define SCU0_RSTCTL1_EMMC BIT(17) +#define SCU0_RSTCTL1_HACE BIT(4) +#define SCU0_RSTCTL1_CLR 0x204 +#define SCU0_RSTCTL1_CLR_EMMC BIT(17) +#define SCU0_RSTCTL1_CLR_HACE BIT(4) +#define SCU0_CLKGATE1 0x240 +#define SCU0_CLKGATE1_EMMC BIT(27) +#define SCU0_CLKGATE1_HACE BIT(13) +#define SCU0_CLKGATE1_DDRPHY BIT(11) +#define SCU0_CLKGATE1_CLR 0x244 +#define SCU0_CLKGATE1_CLR_EMMC BIT(27) +#define SCU0_CLKGATE1_CLR_HACE BIT(13) +#define SCU0_CLKGATE1_CLR_DDRPHY BIT(11) +#define SCU0_VGA0_SCRATCH 0x900 +#define SCU0_VGA0_SCRATCH_DRAM_INIT BIT(6) +#define SCU0_PCI_MISC70 0xa70 +#define SCU0_PCI_MISC70_EN_PCIEXHCI0 BIT(3) +#define SCU0_PCI_MISC70_EN_PCIEEHCI0 BIT(2) +#define SCU0_PCI_MISC70_EN_PCIEVGA0 BIT(0) +#define SCU0_PCI_MISC80 0xa80 +#define SCU0_PCI_MISC80_EN_PCIEXHCI1 BIT(3) +#define SCU0_PCI_MISC80_EN_PCIEEHCI1 BIT(2) +#define SCU0_PCI_MISC80_EN_PCIEVGA1 BIT(0) +#define SCU0_PCI_MISCF0 0xaf0 +#define SCU0_PCI_MISCF0_EN_PCIEXHCI1 BIT(3) +#define SCU0_PCI_MISCF0_EN_PCIEEHCI1 BIT(2) +#define SCU0_PCI_MISCF0_EN_PCIEVGA1 BIT(0) +#define SCU0_WPROT1 0xe04 +#define SCU0_WPROT1_0C8 BIT(18) + +/* SCU1: IO-die SCU */ +#define SCU1_REVISION 0x000 +#define SCU1_REVISION_HWID GENMASK(23, 16) +#define SCU1_REVISION_CHIP_EFUSE GENMASK(15, 8) +#define SCU1_HWSTRAP1 0x010 +#define SCU1_HWSTRAP1_DIS_CPTRA BIT(30) +#define SCU1_HWSTRAP1_RECOVERY_USB_PORT GENMASK(29, 28) +#define SCU1_HWSTRAP1_RECOVERY_INTERFACE GENMASK(27, 26) +#define SCU1_HWSTRAP1_RECOVERY_I3C (BIT(26) | BIT(27)) +#define SCU1_HWSTRAP1_RECOVERY_I2C BIT(27) +#define SCU1_HWSTRAP1_RECOVERY_USB BIT(26) +#define SCU1_HWSTRAP1_SPI_FLASH_4_BYTE_MODE BIT(25) +#define SCU1_HWSTRAP1_SPI_FLASH_WAIT_READY BIT(24) +#define SCU1_HWSTRAP1_BOOT_UFS BIT(23) +#define SCU1_HWSTRAP1_DIS_ROM BIT(22) +#define SCU1_HWSTRAP1_DIS_CPTRAJTAG BIT(20) +#define SCU1_HWSTRAP1_UARTDBGSEL BIT(19) +#define SCU1_HWSTRAP1_DIS_UARTDBG BIT(18) +#define SCU1_HWSTRAP1_DIS_WDTFULL BIT(17) +#define SCU1_HWSTRAP1_DISDEBUG1 BIT(16) +#define SCU1_HWSTRAP1_LTPI0_IO_DRIVING GENMASK(15, 14) +#define SCU1_HWSTRAP1_ACPI_1 BIT(13) +#define SCU1_HWSTRAP1_ACPI_0 BIT(12) +#define SCU1_HWSTRAP1_BOOT_EMMC_UFS BIT(11) +#define SCU1_HWSTRAP1_DDR4 BIT(10) +#define SCU1_HWSTRAP1_LOW_SECURE BIT(8) +#define SCU1_HWSTRAP1_EN_EMCS BIT(7) +#define SCU1_HWSTRAP1_EN_GPIOPT BIT(6) +#define SCU1_HWSTRAP1_EN_SECBOOT BIT(5) +#define SCU1_HWSTRAP1_EN_RECOVERY_BOOT BIT(4) +#define SCU1_HWSTRAP1_LTPI0_EN BIT(3) +#define SCU1_HWSTRAP1_LTPI_IDX BIT(2) +#define SCU1_HWSTRAP1_LTPI1_EN BIT(1) +#define SCU1_HWSTRAP1_LTPI_MODE BIT(0) +#define SCU1_HWSTRAP2 0x030 +#define SCU1_HWSTRAP2_FMC_ABR_SINGLE_FLASH BIT(29) +#define SCU1_HWSTRAP2_FMC_ABR_CS_SWAP_DIS BIT(28) +#define SCU1_HWSTRAP2_SPI_TPM_PCR_EXT_EN BIT(27) +#define SCU1_HWSTRAP2_SPI_TPM_HASH_ALGO GENMASK(26, 25) +#define SCU1_HWSTRAP2_BOOT_SPI_FREQ GENMASK(24, 23) +#define SCU1_HWSTRAP2_RESERVED GENMASK(22, 19) +#define SCU1_HWSTRAP2_FWSPI_CRTM GENMASK(18, 17) +#define SCU1_HWSTRAP2_EN_FWSPIAUX BIT(16) +#define SCU1_HWSTRAP2_FWSPISIZE GENMASK(15, 13) +#define SCU1_HWSTRAP2_DIS_REC BIT(12) +#define SCU1_HWSTRAP2_EN_CPTRA_DBG BIT(11) +#define SCU1_HWSTRAP2_TPM_PCR_INDEX GENMASK(6, 2) +#define SCU1_HWSTRAP2_ROM_CLEAR_SRAM BIT(1) +#define SCU1_HWSTRAP2_ABR BIT(0) +#define SCU1_RSTLOG0 0x050 +#define SCU1_RSTLOG0_BMC_CPU BIT(12) +#define SCU1_RSTLOG0_ABR BIT(2) +#define SCU1_RSTLOG0_EXTRSTN BIT(1) +#define SCU1_RSTLOG0_SRST BIT(0) +#define SCU1_MISC1 0x0c0 +#define SCU1_MISC1_UARTDBG_ROUTE GENMASK(23, 22) +#define SCU1_MISC1_UART12_ROUTE GENMASK(21, 20) +#define SCU1_DBGCTL 0x0c8 +#define SCU1_DBGCTL_MASK GENMASK(7, 0) +#define SCU1_DBGCTL_UARTDBG BIT(6) +#define SCU1_RNG_DATA 0x0f4 +#define SCU1_RSTCTL1 0x200 +#define SCU1_RSTCTL1_I3C(x) (BIT(16) << (x)) +#define SCU1_RSTCTL1_CLR 0x204 +#define SCU1_RSTCTL1_CLR_I3C(x) (BIT(16) << (x)) +#define SCU1_RSTCTL2 0x220 +#define SCU1_RSTCTL2_LTPI1 BIT(22) +#define SCU1_RSTCTL2_LTPI0 BIT(20) +#define SCU1_RSTCTL2_I2C BIT(15) +#define SCU1_RSTCTL2_CPTRA BIT(9) +#define SCU1_RSTCTL2_CLR 0x224 +#define SCU1_RSTCTL2_CLR_I2C BIT(15) +#define SCU1_RSTCTL2_CLR_CPTRA BIT(9) +#define SCU1_CLKGATE1 0x240 +#define SCU1_CLKGATE1_I3C(x) (BIT(16) << (x)) +#define SCU1_CLKGATE1_I2C BIT(15) +#define SCU1_CLKGATE1_CLR 0x244 +#define SCU1_CLKGATE1_CLR_I3C(x) (BIT(16) << (x)) +#define SCU1_CLKGATE1_CLR_I2C BIT(15) +#define SCU1_CLKGATE2 0x260 +#define SCU1_CLKGATE2_LTPI1_TX BIT(19) +#define SCU1_CLKGATE2_LTPI_AHB BIT(10) +#define SCU1_CLKGATE2_LTPI0_TX BIT(9) +#define SCU1_CLKGATE2_CLR 0x264 + +#endif diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2700.h b/arch/arm/include/asm/arch-aspeed/scu_ast2700.h new file mode 100644 index 00000000000..b973fcc6610 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2700.h @@ -0,0 +1,514 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef _ASM_ARCH_SCU_AST2700_H +#define _ASM_ARCH_SCU_AST2700_H + +#include <linux/types.h> + +/* SoC0 SCU Register */ +#define SCU_CPU_REVISION_ID_HW GENMASK(23, 16) +#define SCU_CPU_REVISION_ID_EFUSE GENMASK(15, 8) + +#define SCU_CPU_HWSTRAP_DIS_RVAS BIT(30) +#define SCU_CPU_HWSTRAP_DP_SRC BIT(29) +#define SCU_CPU_HWSTRAP_DAC_SRC BIT(28) +#define SCU_CPU_HWSTRAP_VRAM_SIZE GENMASK(11, 10) +#define SCU_CPU_HWSTRAP_DIS_CPU BIT(0) + +#define SCU_CPU_MISC_DP_RESET_SRC BIT(11) +#define SCU_CPU_MISC_XDMA_CLIENT_EN BIT(4) +#define SCU_CPU_MISC_2D_CLIENT_EN BIT(3) + +#define SCU_CPU_RST_SSP BIT(30) +#define SCU_CPU_RST_DPMCU BIT(29) +#define SCU_CPU_RST_DP BIT(28) +#define SCU_CPU_RST_XDMA1 BIT(26) +#define SCU_CPU_RST_XDMA0 BIT(25) +#define SCU_CPU_RST_EMMC BIT(17) +#define SCU_CPU_RST_EN_DP_PCI BIT(15) +#define SCU_CPU_RST_CRT BIT(13) +#define SCU_CPU_RST_RVAS1 BIT(10) +#define SCU_CPU_RST_RVAS0 BIT(9) +#define SCU_CPU_RST_2D BIT(7) +#define SCU_CPU_RST_VIDEO BIT(6) +#define SCU_CPU_RST_SOC BIT(5) +#define SCU_CPU_RST_DDRPHY BIT(1) + +#define SCU_CPU_RST2_VGA BIT(12) +#define SCU_CPU_RST2_E2M1 BIT(11) +#define SCU_CPU_RST2_E2M0 BIT(10) +#define SCU_CPU_RST2_TSP BIT(9) + +#define SCU_CPU_VGA_FUNC_DAC_OUTPUT GENMASK(11, 10) +#define SCU_CPU_VGA_FUNC_DP_OUTPUT GENMASK(9, 8) +#define SCU_CPU_VGA_FUNC_DAC_DISABLE BIT(7) + +#define SCU_CPU_PCI_MISC0C_FB_SIZE GENMASK(4, 0) + +#define SCU_CPU_PCI_MISC70_EN_XHCI BIT(3) +#define SCU_CPU_PCI_MISC70_EN_EHCI BIT(2) +#define SCU_CPU_PCI_MISC70_EN_IPMI BIT(1) +#define SCU_CPU_PCI_MISC70_EN_VGA BIT(0) + +#define SCU_CPU_HPLL_P GENMASK(22, 19) +#define SCU_CPU_HPLL_N GENMASK(18, 13) +#define SCU_CPU_HPLL_M GENMASK(12, 0) + +#define SCU_CPU_HPLL2_LOCK BIT(31) +#define SCU_CPU_HPLL2_BWADJ GENMASK(11, 0) + +#define SCU_CPU_SSP_TSP_RESET_STS BIT(8) +#define SCU_CPU_SSP_TSP_SRAM_SD BIT(7) +#define SCU_CPU_SSP_TSP_SRAM_DSLP BIT(6) +#define SCU_CPU_SSP_TSP_SRAM_SLP BIT(5) +#define SCU_CPU_SSP_TSP_NIDEN BIT(4) +#define SCU_CPU_SSP_TSP_DBGEN BIT(3) +#define SCU_CPU_SSP_TSP_DBG_ENABLE BIT(2) +#define SCU_CPU_SSP_TSP_RESET BIT(1) +#define SCU_CPU_SSP_TSP_ENABLE BIT(0) + +/* SoC1 SCU Register */ +#define SCU_IO_HWSTRAP_UFS BIT(23) +#define SCU_IO_HWSTRAP_EMMC BIT(11) +#define SCU_IO_HWSTRAP_SECBOOT BIT(5) +#define SCU_IO_HWSTRAP_LTPI0_EN BIT(3) +#define SCU_IO_HWSTRAP_LTPI1_EN BIT(1) + +/* CLK information */ +#define CLKIN_25M 25000000UL + +#define SCU_CPU_CLKGATE1_RVAS1 BIT(28) +#define SCU_CPU_CLKGATE1_RVAS0 BIT(25) +#define SCU_CPU_CLKGATE1_E2M1 BIT(19) +#define SCU_CPU_CLKGATE1_DP BIT(18) +#define SCU_CPU_CLKGATE1_DAC BIT(17) +#define SCU_CPU_CLKGATE1_E2M0 BIT(12) +#define SCU_CPU_CLKGATE1_VGA1 BIT(10) +#define SCU_CPU_CLKGATE1_VGA0 BIT(5) + +/* + * Clock divider/multiplier configuration struct. + * For H-PLL and M-PLL the formula is + * (Output Frequency) = CLKIN * ((M + 1) / (N + 1)) / (P + 1) + * M - Numerator + * N - Denumerator + * P - Post Divider + * They have the same layout in their control register. + * + */ +union ast2700_pll_reg { + u32 w; + struct { + uint16_t m : 13; /* bit[12:0] */ + uint8_t n : 6; /* bit[18:13] */ + uint8_t p : 4; /* bit[22:19] */ + uint8_t off : 1; /* bit[23] */ + uint8_t bypass : 1; /* bit[24] */ + uint8_t reset : 1; /* bit[25] */ + uint8_t reserved : 6; /* bit[31:26] */ + } b; +}; + +struct ast2700_pll_cfg { + union ast2700_pll_reg reg; + unsigned int ext_reg; +}; + +struct ast2700_pll_desc { + u32 in; + u32 out; + struct ast2700_pll_cfg cfg; +}; + +struct aspeed_clks { + ulong id; + const char *name; +}; + +#ifndef __ASSEMBLY__ +struct ast2700_scu0 { + u32 chip_id1; /* 0x000 */ + u32 rsv_0x04[3]; /* 0x004 ~ 0x00C */ + u32 hwstrap1; /* 0x010 */ + u32 hwstrap1_clr; /* 0x014 */ + u32 rsv_0x18[2]; /* 0x018 ~ 0x01C */ + u32 hwstrap1_lock; /* 0x020 */ + u32 hwstrap1_sec1; /* 0x024 */ + u32 hwstrap1_sec2; /* 0x028 */ + u32 hwstrap1_sec3; /* 0x02C */ + u32 rsv_0x30[8]; /* 0x030 ~ 0x4C */ + u32 sysrest_log1; /* 0x050 */ + u32 sysrest_log1_sec1; /* 0x054 */ + u32 sysrest_log1_sec2; /* 0x058 */ + u32 sysrest_log1_sec3; /* 0x05C */ + u32 sysrest_log2; /* 0x060 */ + u32 sysrest_log2_sec1; /* 0x064 */ + u32 sysrest_log2_sec2; /* 0x068 */ + u32 sysrest_log2_sec3; /* 0x06C */ + u32 sysrest_log3; /* 0x070 */ + u32 sysrest_log3_sec1; /* 0x074 */ + u32 sysrest_log3_sec2; /* 0x078 */ + u32 sysrest_log3_sec3; /* 0x07C */ + u32 rsv_0x80[8]; /* 0x080 ~ 0x9C */ + u32 probe_sig_select; /* 0x0A0 */ + u32 probe_sig_enable1; /* 0x0A4 */ + u32 probe_sig_enable2; /* 0x0A8 */ + u32 uart_dbg_rate; /* 0x0AC */ + u32 rsv_0xB0[4]; /* 0x0B0 ~ 0xBC*/ + u32 misc; /* 0x0C0 */ + u32 rsv_0xC4; /* 0x0C4 */ + u32 debug_ctrl; /* 0x0C8 */ + u32 rsv_0xCC[5]; /* 0x0CC ~ 0x0DC */ + u32 free_counter_read_low; /* 0x0E0 */ + u32 free_counter_read_high; /* 0x0E4 */ + u32 rsv_0xE8[2]; /* 0x0E8 ~ 0x0EC */ + u32 random_num_ctrl; /* 0x0F0 */ + u32 random_num_data; /* 0x0F4 */ + u32 rsv_0xF8[10]; /* 0x0F8 ~ 0x11C */ + u32 ssp_ctrl_1; /* 0x120 */ + u32 ssp_ctrl_2; /* 0x124 */ + u32 ssp_ctrl_3; /* 0x128 */ + u32 ssp_ctrl_4; /* 0x12C */ + u32 ssp_ctrl_5; /* 0x130 */ + u32 ssp_ctrl_6; /* 0x134 */ + u32 ssp_ctrl_7; /* 0x138 */ + u32 rsv_0x13c[1]; /* 0x13C */ + u32 ssp_remap0_base; /* 0x140 */ + u32 ssp_remap0_size; /* 0x144 */ + u32 ssp_remap1_base; /* 0x148 */ + u32 ssp_remap1_size; /* 0x14c */ + u32 ssp_remap2_base; /* 0x150 */ + u32 ssp_remap2_size; /* 0x154 */ + u32 rsv_0x158[2]; /* 0x158 ~ 0x15C */ + u32 tsp_ctrl_1; /* 0x160 */ + u32 rsv_0x164[1]; /* 0x164 */ + u32 tsp_ctrl_3; /* 0x168 */ + u32 tsp_ctrl_4; /* 0x16C */ + u32 tsp_ctrl_5; /* 0x170 */ + u32 tsp_ctrl_6; /* 0x174 */ + u32 tsp_ctrl_7; /* 0x178 */ + u32 rsv_0x17c[6]; /* 0x17C ~ 0x190 */ + u32 tsp_remap_size; /* 0x194 */ + u32 rsv_0x198[26]; /* 0x198 ~ 0x1FC */ + u32 modrst1_ctrl; /* 0x200 */ + u32 modrst1_clr; /* 0x204 */ + u32 rsv_0x208[2]; /* 0x208 ~ 0x20C */ + u32 modrst1_lock; /* 0x210 */ + u32 modrst1_prot1; /* 0x214 */ + u32 modrst1_prot2; /* 0x218 */ + u32 modrst1_prot3; /* 0x21C */ + u32 modrst2_ctrl; /* 0x220 */ + u32 modrst2_clr; /* 0x224 */ + u32 rsv_0x228[2]; /* 0x228 ~ 0x22C */ + u32 modrst2_lock; /* 0x230 */ + u32 modrst2_prot1; /* 0x234 */ + u32 modrst2_prot2; /* 0x238 */ + u32 modrst2_prot3; /* 0x23C */ + u32 clkgate_ctrl; /* 0x240 */ + u32 clkgate_clr; /* 0x244 */ + u32 rsv_0x248[2]; /* 0x248 */ + u32 clkgate_lock; /* 0x250 */ + u32 clkgate_secure1; /* 0x254 */ + u32 clkgate_secure2; /* 0x258 */ + u32 clkgate_secure3; /* 0x25c */ + u32 rsv_0x260[8]; /* 0x260 */ + u32 clk_sel1; /* 0x280 */ + u32 clk_sel2; /* 0x284 */ + u32 clk_sel3; /* 0x288 */ + u32 rsv_0x28c; /* 0x28c */ + u32 clk_sel1_lock; /* 0x290 */ + u32 clk_sel2_lock; /* 0x294 */ + u32 clk_sel3_lock; /* 0x298 */ + u32 rsv_0x29c; /* 0x29c */ + u32 clk_sel1_secure1; /* 0x2a0 */ + u32 clk_sel1_secure2; /* 0x2a4 */ + u32 clk_sel1_secure3; /* 0x2a8 */ + u32 rsv_0x2ac; /* 0x2ac */ + u32 clk_sel2_secure1; /* 0x2b0 */ + u32 clk_sel2_secure2; /* 0x2b4 */ + u32 clk_sel2_secure3; /* 0x2b8 */ + u32 rsv_0x2bc; /* 0x2bc */ + u32 clk_sel3_secure1; /* 0x2c0 */ + u32 clk_sel3_secure2; /* 0x2c4 */ + u32 clk_sel3_secure3; /* 0x2c8 */ + u32 rsv_0x2cc[9]; /* 0x2cc */ + u32 extrst_sel; /* 0x2f0 */ + u32 rsv_0x2f4[3]; /* 0x2f4 */ + u32 hpll; /* 0x300 */ + u32 hpll_ext; /* 0x304 */ + u32 dpll; /* 0x308 */ + u32 dpll_ext; /* 0x30C */ + u32 mpll; /* 0x310 */ + u32 mpll_ext; /* 0x314 */ + u32 rsv_0x318[2]; /* 0x318 ~ 0x31C */ + u32 d1clk_para; /* 0x320 */ + u32 rsv_0x324[3]; /* 0x324 ~ 0x32C */ + u32 d2clk_para; /* 0x330 */ + u32 rsv_0x334[3]; /* 0x334 ~ 0x33C */ + u32 crt1clk_para; /* 0x340 */ + u32 rsv_0x344[3]; /* 0x344 ~ 0x34C */ + u32 crt2clk_para; /* 0x350 */ + u32 rsv_0x354[3]; /* 0x354 ~ 0x35C */ + u32 mphyclk_para; /* 0x360 */ + u32 rsv_0x364[7]; /* 0x364 ~ 0x37C */ + u32 clkduty_meas_ctrl; /* 0x380 */ + u32 clkduty1; /* 0x384 */ + u32 clkduty2; /* 0x368 */ + u32 clkduty_meas_res; /* 0x38c */ + u32 rsv_0x390[4]; /* 0x390 ~ 0x39C */ + u32 freq_counter_ctrl; /* 0x3a0 */ + u32 freq_counter_cmp; /* 0x3a4 */ + u32 prog_delay_ring_ctrl0; /* 0x3a8 */ + u32 prog_delay_ring_ctrl1; /* 0x3ac */ + u32 freq_counter_readback; /* 0x3b0 */ + u32 rsv_0x3b4[19]; /* 0x3b4 */ + u32 pinmux1; /* 0x400 */ + u32 pinmux2; /* 0x404 */ + u32 pinmux3; /* 0x408 */ + u32 rsv_0x40c; /* 0x40C */ + u32 pinmux4; /* 0x410 */ + u32 vga_func_ctrl; /* 0x414 */ + u32 rsv_0x418[2]; /* 0x418 */ + u32 pinmux_lock0; /* 0x420 */ + u32 pinmux_lock1; /* 0x424 */ + u32 pinmux_lock2; /* 0x428 */ + u32 rsv_0x42c; + u32 pinmux_lock3; /* 0x430 */ + u32 pinmux_lock4; /* 0x434 */ + u32 rsv_0x438[18]; + u32 gpio18d0_ioctrl; /* 0x480 */ + u32 gpio18d1_ioctrl; /* 0x484 */ + u32 gpio18d2_ioctrl; /* 0x488 */ + u32 gpio18d3_ioctrl; /* 0x48c */ + u32 gpio18d4_ioctrl; /* 0x490 */ + u32 gpio18d5_ioctrl; /* 0x494 */ + u32 gpio18d6_ioctrl; /* 0x498 */ + u32 gpio18d7_ioctrl; /* 0x49c */ + u32 gpio18e0_ioctrl; /* 0x4a0 */ + u32 gpio18e1_ioctrl; /* 0x4a4 */ + u32 gpio18e2_ioctrl; /* 0x4a8 */ + u32 gpio18e3_ioctrl; /* 0x4ac */ + u32 jtag_ioctrl; /* 0x4b0 */ + u32 uart_ioctrl; /* 0x4b4 */ + u32 misc_ioctrl; /* 0x4b8 */ + u32 rsv_0x4bc[17]; /* 0x4bc ~ 0x4fc */ + u32 pinmux_seucre0_0; /* 0x500 */ + u32 pinmux_seucre0_1; /* 0x504 */ + u32 pinmux_seucre0_2; /* 0x508 */ + u32 rsv_0x50c; + u32 pinmux_seucre0_3; /* 0x510 */ + u32 pinmux_seucre0_4; /* 0x514 */ + u32 rsv_0x518[58]; + u32 pinmux_seucre1_0; /* 0x600 */ + u32 pinmux_seucre1_1; /* 0x604 */ + u32 pinmux_seucre1_2; /* 0x608 */ + u32 rsv_0x60c; + u32 pinmux_seucre1_3; /* 0x610 */ + u32 pinmux_seucre1_4; /* 0x614 */ + u32 rsv_0x618[58]; + u32 pinmux_seucre2_0; /* 0x700 */ + u32 pinmux_seucre2_1; /* 0x704 */ + u32 pinmux_seucre2_2; /* 0x708 */ + u32 rsv_0x70c; + u32 pinmux_seucre2_3; /* 0x710 */ + u32 pinmux_seucre2s_4; /* 0x714 */ + u32 rsv_0x718[26]; + u32 cpu_scratch[96]; /* 0x780 ~ 0x8FC */ + u32 vga0_scratch1[4]; /* 0x900 ~ 0x90C */ + u32 vga1_scratch1[4]; /* 0x910 ~ 0x91C */ + u32 vga0_scratch2[8]; /* 0x920 ~ 0x93C */ + u32 vga1_scratch2[8]; /* 0x940 ~ 0x95C */ + u32 pci_cfg1[3]; /* 0x960 ~ 0x968 */ + u32 rsv_0x96c; /* 0x96C */ + u32 pcie_cfg1; /* 0x970 */ + u32 mmio_decode1; /* 0x974 */ + u32 reloc_ctrl_decode1[2]; /* 0x978 ~ 0x97C */ + u32 rsv_0x980[4]; /* 0x980 ~ 0x98C */ + u32 mbox_decode1; /* 0x990 */ + u32 shared_sram_decode1[2];/* 0x994 ~ 0x998 */ + u32 rsv_0x99c; /* 0x99C */ + u32 pci_cfg2[3]; /* 0x9A0 ~ 0x9A8 */ + u32 rsv_0x9ac; /* 0x9AC */ + u32 pcie_cfg2; /* 0x9B0 */ + u32 mmio_decode2; /* 0x9B4 */ + u32 reloc_ctrl_decode2[2]; /* 0x9B8 ~ 0x9BC */ + u32 rsv_0x9c0[4]; /* 0x9C0 ~ 0x9CC */ + u32 mbox_decode2; /* 0x9D0 */ + u32 shared_sram_decode2[2];/* 0x9D4 ~ 0x9D8 */ + u32 rsv_0x9dc[9]; /* 0x9DC ~ 0x9FC */ + u32 pci0_misc[32]; /* 0xA00 ~ 0xA7C */ + u32 pci1_misc[32]; /* 0xA80 ~ 0xAFC */ +}; + +struct ast2700_scu1 { + u32 chip_id1; /* 0x000 */ + u32 rsv_0x04[3]; /* 0x004 ~ 0x00C */ + u32 hwstrap1; /* 0x010 */ + u32 hwstrap1_clr; /* 0x014 */ + u32 rsv_0x18[2]; /* 0x018 ~ 0x01C */ + u32 hwstrap1_lock; /* 0x020 */ + u32 hwstrap1_sec1; /* 0x024 */ + u32 hwstrap1_sec2; /* 0x028 */ + u32 hwstrap1_sec3; /* 0x02C */ + u32 hwstrap2; /* 0x030 */ + u32 hwstrap2_clr; /* 0x034 */ + u32 rsv_0x38[2]; /* 0x038 ~ 0x03C */ + u32 hwstrap2_lock; /* 0x040 */ + u32 hwstrap2_sec1; /* 0x044 */ + u32 hwstrap2_sec2; /* 0x048 */ + u32 hwstrap2_sec3; /* 0x04C */ + u32 sysrest_log1; /* 0x050 */ + u32 sysrest_log1_sec1; /* 0x054 */ + u32 sysrest_log1_sec2; /* 0x058 */ + u32 sysrest_log1_sec3; /* 0x05C */ + u32 sysrest_log2; /* 0x060 */ + u32 sysrest_log2_sec1; /* 0x064 */ + u32 sysrest_log2_sec2; /* 0x068 */ + u32 sysrest_log2_sec3; /* 0x06C */ + u32 sysrest_log3; /* 0x070 */ + u32 sysrest_log3_sec1; /* 0x074 */ + u32 sysrest_log3_sec2; /* 0x078 */ + u32 sysrest_log3_sec3; /* 0x07C */ + u32 sysrest_log4; /* 0x080 */ + u32 sysrest_log4_sec1; /* 0x084 */ + u32 sysrest_log4_sec2; /* 0x088 */ + u32 sysrest_log4_sec3; /* 0x08C */ + u32 rsv_0x90[7]; /* 0x090 ~ 0xA8 */ + u32 uart_dbg_rate; /* 0x0AC */ + u32 rsv_0xB0[4]; /* 0x0B0 ~ 0xBC*/ + u32 misc; /* 0x0C0 */ + u32 rsv_0xC4; /* 0x0C4 */ + u32 debug_ctrl; /* 0x0C8 */ + u32 rsv_0xCC; /* 0x0CC */ + u32 dac_ctrl; /* 0x0D0 */ + u32 dac_crc_ctrl; /* 0x0D4 */ + u32 rsv_0xD8[2]; /* 0x0D8 ~ 0x0DC */ + u32 video_input_ctrl; /* 0x0E0 */ + u32 rsv_0xE4[3]; /* 0x0E4 ~ 0x0EC */ + u32 random_num_ctrl; /* 0x0F0 */ + u32 random_num_data; /* 0x0F4 */ + u32 rsv_0xF0[2]; /* 0x0F8 ~ 0x0FC */ + u32 rsv_0x100[32]; /* 0x100 ~ 0x17C */ + u32 scratch[32]; /* 0x180 ~ 0x1FC */ + u32 modrst1_ctrl; /* 0x200 */ + u32 modrst1_clr; /* 0x204 */ + u32 rsv_0x208[2]; /* 0x208 ~ 0x20C */ + u32 modrst_lock1; /* 0x210 */ + u32 modrst1_sec1; /* 0x214 */ + u32 modrst1_sec2; /* 0x218 */ + u32 modrst1_sec3; /* 0x21C */ + u32 modrst2_ctrl; /* 0x220 */ + u32 modrst2_clr; /* 0x224 */ + u32 rsv_0x228[2]; /* 0x228 ~ 0x22C */ + u32 modrst2_lock; /* 0x230 */ + u32 modrst2_prot1; /* 0x234 */ + u32 modrst2_prot2; /* 0x238 */ + u32 modrst2_prot3; /* 0x23C */ + u32 clkgate_ctrl1; /* 0x240 */ + u32 clkgate_clr1; /* 0x244 */ + u32 rsv_0x248[2]; /* 0x248 */ + u32 clkgate_lock1; /* 0x250 */ + u32 clkgate_secure11; /* 0x254 */ + u32 clkgate_secure12; /* 0x258 */ + u32 clkgate_secure13; /* 0x25c */ + u32 clkgate_ctrl2; /* 0x260 */ + u32 clkgate_clr2; /* 0x264 */ + u32 rsv_0x268[2]; /* 0x268 */ + u32 clkgate_lock2; /* 0x270 */ + u32 clkgate_secure21; /* 0x274 */ + u32 clkgate_secure22; /* 0x278 */ + u32 clkgate_secure23; /* 0x27c */ + u32 clk_sel1; /* 0x280 */ + u32 clk_sel2; /* 0x284 */ + u32 rsv_0x288[2]; /* 0x288 */ + u32 clk_sel1_lock; /* 0x290 */ + u32 clk_sel2_lock; /* 0x294 */ + u32 rsv_0x298[2]; /* 0x298 */ + u32 clk_sel1_secure1; /* 0x2a0 */ + u32 clk_sel1_secure2; /* 0x2a4 */ + u32 rsv_0x2a8[2]; /* 0x2a8 */ + u32 clk_sel2_secure1; /* 0x2b0 */ + u32 clk_sel2_secure2; /* 0x2b4 */ + u32 rsv_0x2b8[2]; /* 0x2b8 */ + u32 clk_sel3_secure1; /* 0x2c0 */ + u32 clk_sel3_secure2; /* 0x2c4 */ + u32 rsv_0x2c8[10]; /* 0x2c8 */ + u32 extrst_sel1; /* 0x2f0 */ + u32 extrst_sel2; /* 0x2f4 */ + u32 rsv_0x2f8[2]; /* 0x2f8 */ + u32 hpll; /* 0x300 */ + u32 hpll_ext; /* 0x304 */ + u32 rsv_0x308[2]; /* 0x308 ~ 0x30C */ + u32 apll; /* 0x310 */ + u32 apll_ext; /* 0x314 */ + u32 rsv_0x318[2]; /* 0x318 ~ 0x31C */ + u32 dpll; /* 0x320 */ + u32 dpll_ext; /* 0x324 */ + u32 rsv_0x328[2]; /* 0x328 ~ 0x32C */ + u32 uxclk_ctrl; /* 0x330 */ + u32 huxclk_ctrl; /* 0x334 */ + u32 rsv_0x338[18]; /* 0x338 ~ 0x37C */ + u32 clkduty_meas_ctrl; /* 0x380 */ + u32 clkduty1; /* 0x384 */ + u32 clkduty2; /* 0x388 */ + u32 rsv_0x38c; /* 0x38c */ + u32 mac_delay; /* 0x390 */ + u32 mac_100m_delay; /* 0x394 */ + u32 mac_10m_delay; /* 0x398 */ + u32 rsv_0x39c; /* 0x39c */ + u32 freq_counter_ctrl; /* 0x3a0 */ + u32 freq_counter_cmp; /* 0x3a4 */ + u32 rsv_0x3a8[2]; /* 0x3a8 ~ 0x3aC */ + u32 usb_ctrl; /* 0x3b0 */ + u32 usb_lock; /* 0x3b4 */ + u32 usb_secure1; /* 0x3b8 */ + u32 usb_secure2; /* 0x3bc */ + u32 usb_secure3; /* 0x3c0 */ + u32 rsv_0x3c4[15]; /* 0x3c4 ~ 0x3fc */ + u32 pinumx1; /* 0x400 */ + u32 pinumx2; /* 0x404 */ + u32 pinumx3; /* 0x408 */ + u32 pinumx4; /* 0x40c */ + u32 pinumx5; /* 0x410 */ + u32 pinumx6; /* 0x414 */ + u32 pinumx7; /* 0x418 */ + u32 pinumx8; /* 0x41c */ + u32 pinumx9; /* 0x420 */ + u32 pinumx10; /* 0x424 */ + u32 pinumx11; /* 0x428 */ + u32 pinumx12; /* 0x42c */ + u32 pinumx13; /* 0x430 */ + u32 pinumx14; /* 0x434 */ + u32 pinumx15; /* 0x438 */ + u32 pinumx16; /* 0x43c */ + u32 pinumx17; /* 0x440 */ + u32 pinumx18; /* 0x444 */ + u32 pinumx19; /* 0x448 */ + u32 pinumx20; /* 0x44c */ + u32 pinumx21; /* 0x450 */ + u32 pinumx22; /* 0x454 */ + u32 pinumx23; /* 0x458 */ + u32 pinumx24; /* 0x45c */ + u32 pinumx25; /* 0x460 */ + u32 pinumx26; /* 0x464 */ + u32 pinumx27; /* 0x468 */ + u32 rsv_0x46c[4]; /* 0x46c ~ 0x478 */ + u32 pinumx31; /* 0x47c */ + u32 pull_down_dis[8]; /* 0x480 ~ 0x49c */ + u32 pin_conf; /* 0x4a0 */ + u32 rsv_0x4a4[7]; /* 0x4a4 ~ 0x4bc */ + u32 io_driving0; /* 0x4c0 */ + u32 io_driving1; /* 0x4c4 */ + u32 io_driving2; /* 0x4c8 */ + u32 io_driving3; /* 0x4cc */ + u32 io_driving4; /* 0x4d0 */ + u32 io_driving5; /* 0x4d4 */ + u32 io_driving6; /* 0x4d8 */ + u32 io_driving7; /* 0x4dc */ + u32 io_driving8; /* 0x4e0 */ +}; + +#endif +#endif diff --git a/arch/arm/include/asm/arch-aspeed/sdram.h b/arch/arm/include/asm/arch-aspeed/sdram.h new file mode 100644 index 00000000000..daf48dd6ed1 --- /dev/null +++ b/arch/arm/include/asm/arch-aspeed/sdram.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) Aspeed Technology Inc. + */ +#ifndef __ASM_AST2700_SDRAM_H__ +#define __ASM_AST2700_SDRAM_H__ + +struct sdrammc_regs { + u32 prot_key; + u32 intr_status; + u32 intr_clear; + u32 intr_mask; + u32 mcfg; + u32 mctl; + u32 msts; + u32 error_status; + u32 actime1; + u32 actime2; + u32 actime3; + u32 actime4; + u32 actime5; + u32 actime6; + u32 actime7; + u32 dfi_timing; + u32 dcfg; + u32 dctl; + u32 mrctl; + u32 mrwr; + u32 mrrd; + u32 mr01; + u32 mr23; + u32 mr45; + u32 mr67; + u32 refctl; + u32 refmng_ctl; + u32 refsts; + u32 zqctl; + u32 ecc_addr_range; + u32 ecc_failure_status; + u32 ecc_failure_addr; + u32 ecc_test_control; + u32 ecc_test_status; + u32 arbctl; + u32 enccfg; + u32 protect_lock_set; + u32 protect_lock_status; + u32 protect_lock_reset; + u32 enc_min_addr; + u32 enc_max_addr; + u32 enc_key[4]; + u32 enc_iv[3]; + u32 bistcfg; + u32 bist_addr; + u32 bist_size; + u32 bist_patt; + u32 bist_res; + u32 bist_fail_addr; + u32 bist_fail_data[4]; + u32 reserved2[2]; + u32 debug_control; + u32 debug_status; + u32 phy_intf_status; + u32 testcfg; + u32 gfmcfg; + u32 gfm0ctl; + u32 gfm1ctl; + u32 reserved3[0xf8]; +}; + +#define DRAMC_UNLK_KEY 0x1688a8a8 + +/* offset 0x04 */ +#define DRAMC_IRQSTA_PWRCTL_ERR BIT(16) +#define DRAMC_IRQSTA_PHY_ERR BIT(15) +#define DRAMC_IRQSTA_LOWPOWER_DONE BIT(12) +#define DRAMC_IRQSTA_FREQ_CHG_DONE BIT(11) +#define DRAMC_IRQSTA_REF_DONE BIT(10) +#define DRAMC_IRQSTA_ZQ_DONE BIT(9) +#define DRAMC_IRQSTA_BIST_DONE BIT(8) +#define DRAMC_IRQSTA_ECC_RCVY_ERR BIT(5) +#define DRAMC_IRQSTA_ECC_ERR BIT(4) +#define DRAMC_IRQSTA_PROT_ERR BIT(3) +#define DRAMC_IRQSTA_OVERSZ_ERR BIT(2) +#define DRAMC_IRQSTA_MR_DONE BIT(1) +#define DRAMC_IRQSTA_PHY_INIT_DONE BIT(0) + +/* offset 0x14 */ +#define DRAMC_MCTL_WB_SOFT_RESET BIT(24) +#define DRAMC_MCTL_PHY_CLK_DIS BIT(18) +#define DRAMC_MCTL_PHY_RESET BIT(17) +#define DRAMC_MCTL_PHY_POWER_ON BIT(16) +#define DRAMC_MCTL_FREQ_CHG_START BIT(3) +#define DRAMC_MCTL_PHY_LOWPOWER_START BIT(2) +#define DRAMC_MCTL_SELF_REF_START BIT(1) +#define DRAMC_MCTL_PHY_INIT_START BIT(0) + +/* offset 0x40 */ +#define DRAMC_DFICFG_WD_POL BIT(18) +#define DRAMC_DFICFG_CKE_OUT BIT(17) +#define DRAMC_DFICFG_RESET BIT(16) + +/* offset 0x48 */ +#define DRAMC_MRCTL_ERR_STATUS BIT(31) +#define DRAMC_MRCTL_READY_STATUS BIT(30) +#define DRAMC_MRCTL_MR_ADDR BIT(8) +#define DRAMC_MRCTL_CMD_DLL_RST BIT(7) +#define DRAMC_MRCTL_CMD_DQ_SEL BIT(6) +#define DRAMC_MRCTL_CMD_TYPE BIT(2) +#define DRAMC_MRCTL_CMD_WR_CTL BIT(1) +#define DRAMC_MRCTL_CMD_START BIT(0) + +/* offset 0xC0 */ +#define DRAMC_BISTRES_RUNNING BIT(10) +#define DRAMC_BISTRES_FAIL BIT(9) +#define DRAMC_BISTRES_DONE BIT(8) +#define DRAMC_BISTCFG_INIT_MODE BIT(7) +#define DRAMC_BISTCFG_PMODE GENMASK(6, 4) +#define DRAMC_BISTCFG_BMODE GENMASK(3, 2) +#define DRAMC_BISTCFG_ENABLE BIT(1) +#define DRAMC_BISTCFG_START BIT(0) +#define BIST_PMODE_CRC (3) +#define BIST_BMODE_RW_SWITCH (3) + +/* DRAMC048 MR Control Register */ +#define MR_TYPE_SHIFT 2 +#define MR_RW (0 << MR_TYPE_SHIFT) +#define MR_MPC BIT(2) +#define MR_VREFCS (2 << MR_TYPE_SHIFT) +#define MR_VREFCA (3 << MR_TYPE_SHIFT) +#define MR_ADDRESS_SHIFT 8 +#define MR_ADDR(n) (((n) << MR_ADDRESS_SHIFT) | DRAMC_MRCTL_CMD_WR_CTL) +#define MR_NUM_SHIFT 4 +#define MR_NUM(n) ((n) << MR_NUM_SHIFT) +#define MR_DLL_RESET BIT(7) +#define MR_1T_MODE BIT(16) + +#endif diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 81af89c631f..9c5f3090bd8 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -82,7 +82,7 @@ int enable_lcdif_clock(u32 base_addr, bool enable); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); void mxs_set_lcdclk(u32 base_addr, u32 freq); -void select_ldb_di_clock_source(enum ldb_di_clock clk); +void select_ldb_di_clock_source(enum ldb_di_clock clk0, enum ldb_di_clock clk1); void enable_eim_clk(unsigned char enable); int do_mx6_showclocks(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/arch/arm/include/asm/mach-imx/ele_api.h b/arch/arm/include/asm/mach-imx/ele_api.h index 04e7f20a2a6..8d779d6ae1b 100644 --- a/arch/arm/include/asm/mach-imx/ele_api.h +++ b/arch/arm/include/asm/mach-imx/ele_api.h @@ -30,6 +30,7 @@ #define ELE_START_RNG (0xA3) #define ELE_CMD_DERIVE_KEY (0xA9) #define ELE_GENERATE_DEK_BLOB (0xAF) +#define ELE_V2X_GET_STATE_REQ (0xB2) #define ELE_ENABLE_PATCH_REQ (0xC3) #define ELE_RELEASE_RDC_REQ (0xC4) #define ELE_GET_FW_STATUS_REQ (0xC5) @@ -141,6 +142,12 @@ struct ele_get_info_data { u32 reserved[8]; }; +struct v2x_get_state { + u8 v2x_state; + u8 v2x_power_state; + u32 v2x_err_code; +}; + int ele_release_rdc(u8 core_id, u8 xrdc, u32 *response); int ele_auth_oem_ctnr(ulong ctnr_addr, u32 *response); int ele_release_container(u32 *response); @@ -166,4 +173,5 @@ int ele_read_shadow_fuse(u32 fuse_id, u32 *fuse_val, u32 *response); int ele_set_gmid(u32 *response); int ele_volt_change_start_req(void); int ele_volt_change_finish_req(void); +int ele_v2x_get_state(struct v2x_get_state *state, u32 *response); #endif diff --git a/arch/arm/lib/gic-v2.c b/arch/arm/lib/gic-v2.c index b70434a45d4..378bdb54c89 100644 --- a/arch/arm/lib/gic-v2.c +++ b/arch/arm/lib/gic-v2.c @@ -38,7 +38,7 @@ static int acpi_gicv2_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -static struct acpi_ops gic_v2_acpi_ops = { +static const struct acpi_ops gic_v2_acpi_ops = { .fill_madt = acpi_gicv2_fill_madt, }; #endif diff --git a/arch/arm/lib/gic-v3-its.c b/arch/arm/lib/gic-v3-its.c index d11a1ea436e..064b93b2aa1 100644 --- a/arch/arm/lib/gic-v3-its.c +++ b/arch/arm/lib/gic-v3-its.c @@ -197,7 +197,7 @@ static int acpi_gicv3_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -struct acpi_ops gic_v3_acpi_ops = { +static const struct acpi_ops gic_v3_acpi_ops = { .fill_madt = acpi_gicv3_fill_madt, }; #endif diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig index c88b1e59366..f4b038ebd9e 100644 --- a/arch/arm/mach-aspeed/Kconfig +++ b/arch/arm/mach-aspeed/Kconfig @@ -36,9 +36,20 @@ config ASPEED_AST2600 It is used as Board Management Controller on many server boards, which is enabled by support of LPC and eSPI peripherals. +config ASPEED_AST2700 + bool "Support Aspeed AST2700 SoC" + select ARM64 + select SYS_ARCH_TIMER + help + Support for the Aspeed AST2700, an arm64 (Cortex-A35) Baseboard + Management Controller (BMC) SoC. This is the 8th-generation BMC + SoC family from Aspeed and features a dual-die architecture + (CPU die + I/O die) connected via an internal coherent bus. + endchoice source "arch/arm/mach-aspeed/ast2500/Kconfig" source "arch/arm/mach-aspeed/ast2600/Kconfig" +source "arch/arm/mach-aspeed/ast2700/Kconfig" endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile index 42599c125b8..d0b4eb74c6c 100644 --- a/arch/arm/mach-aspeed/Makefile +++ b/arch/arm/mach-aspeed/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o obj-$(CONFIG_ASPEED_AST2500) += ast2500/ obj-$(CONFIG_ASPEED_AST2600) += ast2600/ +obj-$(CONFIG_ASPEED_AST2700) += ast2700/ diff --git a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds index 303ace2f61c..894eda1db77 100644 --- a/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds +++ b/arch/arm/mach-aspeed/ast2600/u-boot-spl.lds @@ -42,6 +42,7 @@ SECTIONS . = ALIGN(4); __u_boot_list : { KEEP(*(SORT(__u_boot_list*))); + . = ALIGN(8); } > .nor . = ALIGN(4); @@ -49,7 +50,6 @@ SECTIONS __binman_sym_start = .; KEEP(*(SORT(.binman_sym*))); __binman_sym_end = .; - . = ALIGN(8); } > .nor /* diff --git a/arch/arm/mach-aspeed/ast2700/Kconfig b/arch/arm/mach-aspeed/ast2700/Kconfig new file mode 100644 index 00000000000..3dd68db76db --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/Kconfig @@ -0,0 +1,36 @@ +if ASPEED_AST2700 + +config SYS_CPU + default "armv8" + +config SPI_KERNEL_FIT_ADDR + hex "SPI address of kernel FIT image" + default 0x100420000 + help + Address in the SPI flash where the kernel FIT image is stored. + Used by the bootspi command to load and boot the kernel image + from the SPI flash on AST2700 platforms. + +choice + prompt "AST2700 board select" + depends on ASPEED_AST2700 + default TARGET_EVB_AST2700 + help + Select the AST2700 board model. Each board option configures + the board-specific Kconfig, defaults and devicetree. + +config TARGET_EVB_AST2700 + bool "EVB-AST2700" + depends on ASPEED_AST2700 + select ARCH_MISC_INIT + help + EVB-AST2700 is Aspeed evaluation board for AST2700A0 chip. + It has 512M of RAM, 32M of SPI flash, two Ethernet ports, + 4 Serial ports, 4 USB ports, VGA port, PCIe, SD card slot, + 20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs. + +endchoice + +source "board/aspeed/evb_ast2700/Kconfig" + +endif diff --git a/arch/arm/mach-aspeed/ast2700/Makefile b/arch/arm/mach-aspeed/ast2700/Makefile new file mode 100644 index 00000000000..38bd52f3d5d --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/Makefile @@ -0,0 +1,2 @@ +obj-y += lowlevel_init.o board_common.o arm64-mmu.o platform.o +obj-$(CONFIG_DISPLAY_CPUINFO) += cpu-info.o diff --git a/arch/arm/mach-aspeed/ast2700/arm64-mmu.c b/arch/arm/mach-aspeed/ast2700/arm64-mmu.c new file mode 100644 index 00000000000..a068e6ede97 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/arm64-mmu.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <dm.h> +#include <asm/armv8/mmu.h> + +static struct mm_region aspeed2700_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x40000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN, + }, + { + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x2C0000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE, + }, + { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, + { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = aspeed2700_mem_map; + +u64 get_page_table_size(void) +{ + return 0x80000; +} diff --git a/arch/arm/mach-aspeed/ast2700/board_common.c b/arch/arm/mach-aspeed/ast2700/board_common.c new file mode 100644 index 00000000000..6d2160bbca4 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/board_common.c @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <dm.h> +#include <ram.h> +#include <init.h> +#include <timer.h> +#include <asm/io.h> +#include <asm/arch/timer.h> +#include <linux/bitfield.h> +#include <linux/bitops.h> +#include <linux/err.h> +#include <dm/uclass.h> +#include <asm/arch-aspeed/scu_ast2700.h> + +#define AHBC_GROUP(x) (0x40 * (x)) +#define AHBC_HREADY_WAIT_CNT_REG 0x34 +#define AHBC_HREADY_WAIT_CNT_MAX 0x3f + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + struct udevice *dev; + struct ram_info ram; + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + printf("cannot get DRAM driver\n"); + debug("cannot get DRAM driver\n"); + return ret; + } + + ret = ram_get_info(dev, &ram); + if (ret) { + debug("cannot get DRAM information\n"); + return ret; + } + + gd->ram_size = ram.size; + + return 0; +} + +static void ahbc_init(void) +{ + u32 reg_val; + int i; + + reg_val = readl(ASPEED_CPU_REVISION_ID); + if (FIELD_GET(SCU_CPU_REVISION_ID_HW, reg_val)) + return; + + /* CPU-die AHBC timeout counter */ + for (i = 0; i < 4; i++) + writel(AHBC_HREADY_WAIT_CNT_MAX, + (void *)ASPEED_CPU_AHBC_BASE + AHBC_GROUP(i) + AHBC_HREADY_WAIT_CNT_REG); + + /* IO-die AHBC timeout counter */ + for (i = 0; i < 8; i++) + writel(AHBC_HREADY_WAIT_CNT_MAX, + (void *)ASPEED_IO_AHBC_BASE + AHBC_GROUP(i) + AHBC_HREADY_WAIT_CNT_REG); +} + +int board_init(void) +{ + struct udevice *dev; + int i = 0; + int ret; + + ahbc_init(); + + /* + * Loop over all MISC uclass drivers to call the comphy code + * and init all CP110 devices enabled in the DT + */ + while (1) { + /* Call the comphy code via the MISC uclass driver */ + ret = uclass_get_device(UCLASS_MISC, i++, &dev); + + /* We're done, once no further CP110 device is found */ + if (ret) + break; + } + + return 0; +} diff --git a/arch/arm/mach-aspeed/ast2700/cpu-info.c b/arch/arm/mach-aspeed/ast2700/cpu-info.c new file mode 100644 index 00000000000..7f29c4d8c33 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/cpu-info.c @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + * Ryan Chen <[email protected]> + */ + +#include <command.h> +#include <asm/io.h> +#include <asm/arch/platform.h> +#include <asm/arch/scu_ast2700.h> + +/* SoC mapping Table */ +#define SOC_ID(str, rev) { .name = str, .rev_id = rev, } + +struct soc_id { + const char *name; + u64 rev_id; +}; + +static struct soc_id soc_map_table[] = { + SOC_ID("AST2750-A0", 0x0600000306000003), + SOC_ID("AST2700-A0", 0x0600010306000103), + SOC_ID("AST2720-A0", 0x0600020306000203), + SOC_ID("AST2750-A1", 0x0601000306010003), + SOC_ID("AST2700-A1", 0x0601010306010103), + SOC_ID("AST2720-A1", 0x0601020306010203), + SOC_ID("AST2750-A2", 0x0602000306020003), + SOC_ID("AST2700-A2", 0x0602010306020103), + SOC_ID("AST2720-A2", 0x0602020306020203), +}; + +void ast2700_print_soc_id(void) +{ + int i; + u64 rev_id; + + rev_id = readl(ASPEED_CPU_REVISION_ID); + rev_id = ((u64)readl(ASPEED_IO_REVISION_ID) << 32) | rev_id; + + for (i = 0; i < ARRAY_SIZE(soc_map_table); i++) { + if (rev_id == soc_map_table[i].rev_id) + break; + } + if (i == ARRAY_SIZE(soc_map_table)) + printf("Unknown-SOC: %llx\n", rev_id); + else + printf("SOC: %4s\n", soc_map_table[i].name); +} + +#define SYS_DRAM_ECCRST BIT(3) +#define SYS_ABRRST BIT(2) +#define SYS_EXTRST BIT(1) +#define SYS_SRST BIT(0) + +#define WDT_RST_BIT_MASK(s) (GENMASK(3, 0) << (s)) +#define BIT_WDT_FULL(s) (BIT(0) << (s)) +#define BIT_WDT_ARM(s) (BIT(1) << (s)) +#define BIT_WDT_SOC(s) (BIT(2) << (s)) +#define BIT_WDT_SW(s) (BIT(3) << (s)) + +void ast2700_print_wdtrst_info(void) +{ + u32 wdt_rst = readl(ASPEED_IO_RESET_LOG4); + int i; + + for (i = 0; i < 8; i++) { + if (wdt_rst & WDT_RST_BIT_MASK(i * 4)) { + printf("RST: WDT%d ", i); + if (wdt_rst & BIT_WDT_SOC(i * 4)) { + printf("SOC "); + writel(BIT_WDT_SOC(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_FULL(i * 4)) { + printf("FULL "); + writel(BIT_WDT_FULL(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_ARM(i * 4)) { + printf("ARM "); + writel(BIT_WDT_ARM(i * 4), ASPEED_IO_RESET_LOG4); + } + if (wdt_rst & BIT_WDT_SW(i * 4)) { + printf("SW "); + writel(BIT_WDT_SW(i * 4), ASPEED_IO_RESET_LOG4); + } + printf("\n"); + } + } +} + +#define SYS_EXTRST BIT(1) +#define SYS_SRST BIT(0) + +void ast2700_print_sysrst_info(void) +{ + u32 sys_rst = readl(ASPEED_CPU_RESET_LOG1); + + if (sys_rst & SYS_SRST) { + printf("RST: Power On\n"); + writel(SYS_SRST, ASPEED_CPU_RESET_LOG1); + } else if (sys_rst & SYS_EXTRST) { + printf("RST: EXTRST\n"); + writel(SYS_EXTRST, ASPEED_CPU_RESET_LOG1); + } else { + ast2700_print_wdtrst_info(); + } +} + +int print_cpuinfo(void) +{ + ast2700_print_soc_id(); + ast2700_print_sysrst_info(); + + return 0; +} diff --git a/arch/arm/mach-aspeed/ast2700/lowlevel_init.S b/arch/arm/mach-aspeed/ast2700/lowlevel_init.S new file mode 100644 index 00000000000..9b78fed0b26 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/lowlevel_init.S @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) ASPEED Technology Inc. + */ +#include <config.h> +#include <linux/linkage.h> + +/* + * SMP mailbox + * +-----------------------+ 0x40 + * | | + * | mailbox insn. for | + * | cpuN GO sign polling | + * | | + * +-----------------------+ 0x20 + * | cpu3 entrypoint | + * +-----------------------+ 0x18 + * | cpu2 entrypoint | + * +-----------------------+ 0x10 + * | cpu1 entrypoint | + * +-----------------------+ 0x8 + * | reserved | + * +-----------------------+ 0x4 + * | mailbox ready | + * +-----------------------+ SCU_CPU + 0x780 + */ + +#define SCU_CPU_BASE 0x12c02000 +#define SCU_CPU_SMP_READY (SCU_CPU_BASE + 0x780) +#define SCU_CPU_SMP_EP1 (SCU_CPU_BASE + 0x788) +#define SCU_CPU_SMP_EP2 (SCU_CPU_BASE + 0x790) +#define SCU_CPU_SMP_EP3 (SCU_CPU_BASE + 0x798) +#define SCU_CPU_SMP_POLLINSN (SCU_CPU_BASE + 0x7a0) + +ENTRY(lowlevel_init) + /* backup LR */ + mov x29, lr + +#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) + /* reset SMP mailbox ASAP */ + ldr x0, =SCU_CPU_SMP_READY + str wzr, [x0] + + /* + * get cpu core id + * + * ast2700 has 1-cluster, 4-cores CPU topology. + * Affinity level 0 in MPIDR is sufficient. + */ + mrs x4, mpidr_el1 + ands x4, x4, #0xff + + /* cpu0 is the primary core to setup SMP mailbox */ + beq do_primary_core_setup + + /* hold cpuN until mailbox is ready */ + ldr x0, =SCU_CPU_SMP_READY + movz w1, #0xcafe + movk w1, #0xbabe, lsl #16 + +poll_mailbox_ready: + wfe + ldr w2, [x0] + cmp w1, w2 + bne poll_mailbox_ready + + /* + * parameters for relocated SMP go polling insn. + * x4 = cpu id + * x5 = SCU_CPU_SMP_EPx + */ + add x5, x0, x4, lsl #3 + + /* jump to the polling loop in SMP mailbox, no return */ + ldr x0, =SCU_CPU_SMP_POLLINSN + br x0 + +do_primary_core_setup: + /* relocate mailbox insn. for cpuN to poll for SMP go signal */ + adr x0, smp_mbox_insn + adr x1, smp_mbox_insn_end + ldr x2, =SCU_CPU_SMP_POLLINSN + +relocate_smp_mbox_insn: + ldr w3, [x0], #0x4 + str w3, [x2], #0x4 + cmp x0, x1 + bne relocate_smp_mbox_insn + + /* reset cpuN entrypoints */ + ldr x0, =SCU_CPU_SMP_EP1 + str xzr, [x0], #8 + str xzr, [x0], #8 + str xzr, [x0] + + /* notify cpuN that SMP mailbox is ready */ + movz w0, #0xcafe + movk w0, #0xbabe, lsl #16 + ldr x1, =SCU_CPU_SMP_READY + str w0, [x1] + + sev +#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ + + /* back to arch calling code */ + mov lr, x29 + ret +ENDPROC(lowlevel_init) + +/* + * insn. inside mailbox to poll SMP go signal. + * + * Note that this code will be relocated, any absolute + * addressing should NOT be used. + */ +smp_mbox_insn: + /* + * x4 = cpu id + * x5 = SCU_CPU_SMP_EPx + */ +poll_smp_mbox_go: + wfe + ldr x0, [x5] + cmp x0, xzr + beq poll_smp_mbox_go + + /* jump to secondary core entrypoint */ + br x0 + +smp_mbox_insn_end: + /* should never reach */ + b . diff --git a/arch/arm/mach-aspeed/ast2700/platform.c b/arch/arm/mach-aspeed/ast2700/platform.c new file mode 100644 index 00000000000..9cca85766f6 --- /dev/null +++ b/arch/arm/mach-aspeed/ast2700/platform.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <dm.h> +#include <asm/arch-aspeed/scu_ast2700.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <env.h> +#include <env_internal.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum env_location env_loc = ENVL_UNKNOWN; + u32 strap = readl(ASPEED_IO_HW_STRAP1); + + if (prio) + return env_loc; + + if (IS_ENABLED(CONFIG_ENV_IS_NOWHERE)) { + env_loc = ENVL_NOWHERE; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH) && + !(strap & SCU_IO_HWSTRAP_EMMC)) { + env_loc = ENVL_SPI_FLASH; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC) && + (strap & SCU_IO_HWSTRAP_EMMC) && + !(strap & SCU_IO_HWSTRAP_UFS)) { + env_loc = ENVL_MMC; + } else if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH)) { + /* + * This tree does not carry an ENV_IS_IN_UFS backend yet. + * Fall back to SPI flash when that backend exists. + */ + env_loc = ENVL_SPI_FLASH; + } else { + env_loc = ENVL_NOWHERE; + } + + return env_loc; +} + +int arch_misc_init(void) +{ + if (IS_ENABLED(CONFIG_ARCH_MISC_INIT)) { + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_EMMC)) { + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_UFS)) + env_set("boot_device", "ufs"); + else + env_set("boot_device", "mmc"); + } else { + env_set("boot_device", "spi"); + } + + if ((readl(ASPEED_IO_HW_STRAP1) & SCU_IO_HWSTRAP_SECBOOT)) + env_set("verify", "yes"); + else + env_set("verify", "no"); + } + + return 0; +} diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 65e9d70f084..19e3ac360dd 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -150,9 +150,9 @@ config TARGET_SAM9X60EK select BOARD_LATE_INIT config TARGET_SAM9X60_CURIOSITY - bool "SAM9X60 CURIOSITY board" - select SAM9X60 - select BOARD_LATE_INIT + bool "SAM9X60 CURIOSITY board" + select SAM9X60 + select BOARD_LATE_INIT config TARGET_SAM9X75_CURIOSITY bool "SAM9X75 CURIOSITY board" @@ -270,9 +270,9 @@ config TARGET_CORVUS imply CMD_DM config TARGET_SAMA7G5EK - bool "SAMA7G5 EK board" - select SAMA7G5 - select BOARD_LATE_INIT + bool "SAMA7G5 EK board" + select SAMA7G5 + select BOARD_LATE_INIT config TARGET_SAMA7G54_CURIOSITY bool "SAMA7G54 CURIOSITY board" diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 66142a835ce..561f1ee044a 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -157,7 +157,7 @@ config CMD_PRIBLOB depends on HAS_CAAM && IMX_HAB help This option enables the priblob command which can be used - to set the priblob setting to 0x3. + to set the priblob setting to 0x3. config CMD_HDMIDETECT bool "Support the 'hdmidet' command" diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index c49ad44ac2d..93be5644c88 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -47,7 +47,7 @@ u32 get_imx_reset_cause(void) return reset_cause; } -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) +#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) && !CONFIG_IS_ENABLED(CPU) static char *get_reset_cause(void) { switch (get_imx_reset_cause()) { @@ -75,11 +75,6 @@ static char *get_reset_cause(void) return "WDOG4"; case 0x00200: return "TEMPSENSE"; -#elif defined(CONFIG_IMX8M) - case 0x00100: - return "WDOG2"; - case 0x00200: - return "TEMPSENSE"; #else case 0x00100: return "TEMPSENSE"; @@ -90,63 +85,10 @@ static char *get_reset_cause(void) return "unknown reset"; } } -#endif - -#if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_XPL_BUILD) const char *get_imx_type(u32 imxtype) { switch (imxtype) { - case MXC_CPU_IMX8MP: - return "8MP[8]"; /* Quad-core version of the imx8mp */ - case MXC_CPU_IMX8MPD2: - return "8MP Dual[2]"; /* Dual-core version of the imx8mp, low cost industrial & HMI */ - case MXC_CPU_IMX8MPD: - return "8MP Dual[3]"; /* Dual-core version of the imx8mp */ - case MXC_CPU_IMX8MPL: - return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */ - case MXC_CPU_IMX8MP5: - return "8MP[5]"; /* Quad-core version of the imx8mp, low cost industrial & HMI */ - case MXC_CPU_IMX8MP6: - return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */ - case MXC_CPU_IMX8MPUL: - return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */ - case MXC_CPU_IMX8MN: - return "8MNano Quad"; /* Quad-core version */ - case MXC_CPU_IMX8MND: - return "8MNano Dual"; /* Dual-core version */ - case MXC_CPU_IMX8MNS: - return "8MNano Solo"; /* Single-core version */ - case MXC_CPU_IMX8MNL: - return "8MNano QuadLite"; /* Quad-core Lite version */ - case MXC_CPU_IMX8MNDL: - return "8MNano DualLite"; /* Dual-core Lite version */ - case MXC_CPU_IMX8MNSL: - return "8MNano SoloLite";/* Single-core Lite version of the imx8mn */ - case MXC_CPU_IMX8MNUQ: - return "8MNano UltraLite Quad";/* Quad-core UltraLite version of the imx8mn */ - case MXC_CPU_IMX8MNUD: - return "8MNano UltraLite Dual";/* Dual-core UltraLite version of the imx8mn */ - case MXC_CPU_IMX8MNUS: - return "8MNano UltraLite Solo";/* Single-core UltraLite version of the imx8mn */ - case MXC_CPU_IMX8MM: - return "8MMQ"; /* Quad-core version of the imx8mm */ - case MXC_CPU_IMX8MML: - return "8MMQL"; /* Quad-core Lite version of the imx8mm */ - case MXC_CPU_IMX8MMD: - return "8MMD"; /* Dual-core version of the imx8mm */ - case MXC_CPU_IMX8MMDL: - return "8MMDL"; /* Dual-core Lite version of the imx8mm */ - case MXC_CPU_IMX8MMS: - return "8MMS"; /* Single-core version of the imx8mm */ - case MXC_CPU_IMX8MMSL: - return "8MMSL"; /* Single-core Lite version of the imx8mm */ - case MXC_CPU_IMX8MQ: - return "8MQ"; /* Quad-core version of the imx8mq */ - case MXC_CPU_IMX8MQL: - return "8MQLite"; /* Quad-core Lite version of the imx8mq */ - case MXC_CPU_IMX8MD: - return "8MD"; /* Dual-core version of the imx8mq */ case MXC_CPU_MX7S: return "7S"; /* Single-core version of the mx7 */ case MXC_CPU_MX7D: diff --git a/arch/arm/mach-imx/fdt.c b/arch/arm/mach-imx/fdt.c index f19ab9edce4..1ef26718463 100644 --- a/arch/arm/mach-imx/fdt.c +++ b/arch/arm/mach-imx/fdt.c @@ -3,6 +3,7 @@ * Copyright 2024 NXP */ +#include <env.h> #include <errno.h> #include <fdtdec.h> #include <malloc.h> @@ -91,6 +92,15 @@ int fixup_thermal_trips(void *blob, const char *name) int minc, maxc; int node, trip; + /* + * During development or various dangerous experiments, it may + * be necessary to override the trip points. Allow users to do + * that. However, do keep in mind that this may damage the SoC. + */ + if (CONFIG_IS_ENABLED(ENV_SUPPORT)) + if (env_get("imx_skip_fixup_thermal_trips")) + return 0; + node = fdt_path_offset(blob, "/thermal-zones"); if (node < 0) return node; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 0d22d3b4e3a..5f7d7e4c66e 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -10,6 +10,7 @@ config IMX8M select ARMV8_CRYPTO imply CPU imply CPU_IMX + imply DM_THERMAL imply IMX_TMU config IMX8MQ diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index e600fd6b33e..909bd7476db 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1480,6 +1480,33 @@ void reset_cpu(void) #endif #if IS_ENABLED(CONFIG_ARCH_MISC_INIT) +static char *get_reset_cause(void) +{ + switch (get_imx_reset_cause()) { + case 0x00001: + case 0x00011: + return "POR"; + case 0x00004: + return "CSU"; + case 0x00008: + return "IPP USER"; + case 0x00010: + return "WDOG"; + case 0x00020: + return "JTAG HIGH-Z"; + case 0x00040: + return "JTAG SW"; + case 0x00080: + return "WDOG3"; + case 0x00100: + return "WDOG2"; + case 0x00200: + return "TEMPSENSE"; + default: + return "unknown reset"; + } +} + int arch_misc_init(void) { if (IS_ENABLED(CONFIG_FSL_CAAM)) { @@ -1491,6 +1518,9 @@ int arch_misc_init(void) printf("Failed to initialize caam_jr: %d\n", ret); } + if (IS_ENABLED(CONFIG_XPL_BUILD)) + printf("Reset cause: %s\n", get_reset_cause()); + return 0; } #endif diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 6d6f3b81aca..3e9566bd7ca 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -254,11 +254,6 @@ static char *get_reset_cause(char *ret) } #if defined(CONFIG_DISPLAY_CPUINFO) -const char *get_imx_type(u32 imxtype) -{ - return "8ULP"; -} - int print_cpuinfo(void) { u32 cpurev; @@ -266,8 +261,7 @@ int print_cpuinfo(void) cpurev = get_cpu_rev(); - printf("CPU: i.MX%s rev%d.%d at %d MHz\n", - get_imx_type((cpurev & 0xFF000) >> 12), + printf("CPU: i.MX8ULP rev%d.%d at %d MHz\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig index 4bb6a87ce26..cbd0078ba2a 100644 --- a/arch/arm/mach-imx/imx9/Kconfig +++ b/arch/arm/mach-imx/imx9/Kconfig @@ -1,9 +1,9 @@ if ARCH_IMX9 config AHAB_BOOT - bool "Support i.MX9 AHAB features" - help - This option enables the support for AHAB secure boot. + bool "Support i.MX9 AHAB features" + help + This option enables the support for AHAB secure boot. config IMX9 bool @@ -14,6 +14,7 @@ config IMX9 select HAS_CAAM select ROM_UNIFIED_SECTIONS imply IMX_TMU + imply OF_LIVE config IMX93 bool @@ -172,6 +173,10 @@ config TARGET_IMX943_EVK imply BOOTSTD_FULL imply OF_UPSTREAM +config TARGET_AQUILA_IMX95 + bool "Support Toradex Aquila iMX95" + select IMX95 + config TARGET_TORADEX_SMARC_IMX95 bool "Support Toradex SMARC iMX95" select IMX95 @@ -205,6 +210,7 @@ source "board/phytec/phycore_imx91_93/Kconfig" source "board/variscite/imx93_var_som/Kconfig" source "board/nxp/imx94_evk/Kconfig" source "board/nxp/imx95_evk/Kconfig" +source "board/toradex/aquila-imx95/Kconfig" source "board/toradex/smarc-imx95/Kconfig" source "board/toradex/verdin-imx95/Kconfig" source "board/nxp/imx952_evk/Kconfig" diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile index 80b697396ea..ec08430d41d 100644 --- a/arch/arm/mach-imx/imx9/Makefile +++ b/arch/arm/mach-imx/imx9/Makefile @@ -11,7 +11,7 @@ obj-y += soc.o clock.o clock_root.o trdc.o endif ifneq ($(CONFIG_SPL_BUILD),y) -obj-y += imx_bootaux.o +obj-y += imx_bootaux.o misc.o endif obj-$(CONFIG_$(PHASE_)IMX_QB) += qb.o diff --git a/arch/arm/mach-imx/imx9/misc.c b/arch/arm/mach-imx/imx9/misc.c new file mode 100644 index 00000000000..3cad67aed43 --- /dev/null +++ b/arch/arm/mach-imx/imx9/misc.c @@ -0,0 +1,98 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2023-2026 NXP + * + */ + +#include <command.h> +#include <cpu_func.h> +#include <init.h> +#include <log.h> +#include <asm/io.h> +#include <errno.h> +#include <linux/bitops.h> +#include <asm/arch-imx/cpu.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/arch/sys_proto.h> +#include <linux/delay.h> +#include <linux/sizes.h> +#include <display_options.h> + +static int do_v2x_status(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + u32 resp = 0; + struct v2x_get_state state; + + if (is_imx91() || is_imx93()) { + printf("No V2X supported\n"); + return CMD_RET_FAILURE; + } + + ret = ele_v2x_get_state(&state, &resp); + if (ret) { + printf("get v2x state failed, resp 0x%x, ret %d\n", resp, ret); + return CMD_RET_FAILURE; + } + + printf("V2X state: 0x%x\n", state.v2x_state); + printf("V2X power state: 0x%x\n", state.v2x_power_state); + printf("V2X err code: 0x%x\n", state.v2x_err_code); + + return CMD_RET_SUCCESS; +} + +static int do_ele_info(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + u32 res = 0, length; + struct ele_get_info_data *info; + + /* ELE can't access full DDR */ + info = (struct ele_get_info_data *)(CONFIG_TEXT_BASE + SZ_2M - + sizeof(struct ele_get_info_data)); + flush_dcache_range((ulong)info, (ulong)info + sizeof(struct ele_get_info_data)); + + ret = ele_get_info(info, &res); + if (ret) { + printf("Get ELE info failed, resp 0x%x, ret %d\n", res, ret); + return CMD_RET_FAILURE; + } + + invalidate_dcache_range((ulong)info, (ulong)info + sizeof(struct ele_get_info_data)); + + printf("SOC: 0x%x\n", info->soc); + printf("LC: 0x%x\n", info->lc); + + printf("\nUID:\n"); + print_buffer(0, &info->uid, 4, 4, 0); + + printf("\nSHA256 ROM PATCH:\n"); + print_buffer(0, &info->sha256_rom_patch, 4, 8, 0); + + printf("\nSHA FW:\n"); + print_buffer(0, &info->sha_fw, 4, 8, 0); + + printf("\nOEM SRKH:\n"); + print_buffer(0, &info->oem_srkh, 4, 16, 0); + + printf("\nSTATE: 0x%x\n", info->state); + + length = (info->hdr >> 16) & 0xffff; + if (length == sizeof(struct ele_get_info_data)) { + printf("\nOEM PQC SRKH:\n"); + print_buffer(0, &info->oem_pqc_srkh, 4, 16, 0); + } + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(v2x_status, CONFIG_SYS_MAXARGS, 1, do_v2x_status, + "display v2x status", + "" +); + +U_BOOT_CMD(ele_info, CONFIG_SYS_MAXARGS, 1, do_ele_info, + "display ELE information", + "" +); diff --git a/arch/arm/mach-imx/imx9/scmi/soc.c b/arch/arm/mach-imx/imx9/scmi/soc.c index 82b3cdffeea..18d00355999 100644 --- a/arch/arm/mach-imx/imx9/scmi/soc.c +++ b/arch/arm/mach-imx/imx9/scmi/soc.c @@ -515,6 +515,35 @@ phys_size_t get_effective_memsize(void) } } +static inline u64 ether_addr_to_u64(const u8 *addr) +{ + u64 u = 0; + int i; + + for (i = 0; i < 6; i++) + u = u << 8 | addr[i]; + + return u; +} + +static inline void u64_to_ether_addr(u64 u, u8 *addr) +{ + int i; + + for (i = 6 - 1; i >= 0; i--) { + addr[i] = u & 0xff; + u = u >> 8; + } +} + +static inline void eth_addr_add(u8 *addr, long offset) +{ + u64 u = ether_addr_to_u64(addr); + + u += offset; + u64_to_ether_addr(u, addr); +} + void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { u32 val[2] = {}; @@ -559,16 +588,16 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) * | 10 | netc switch | swp2 | */ if (dev_id == 0) - mac[5] = mac[5] + 2; /* enetc3 mac/swp0 */ + eth_addr_add(mac, 2); /* enetc3 mac/swp0 */ if (dev_id == 1) - mac[5] = mac[5] + 8; /* enetc1 */ + eth_addr_add(mac, 8); /* enetc1 */ if (dev_id == 2) - mac[5] = mac[5] + 9; /* enetc2 */ + eth_addr_add(mac, 9); /* enetc2 */ } else { if (dev_id == 1) - mac[5] = mac[5] + 3; + eth_addr_add(mac, 3); if (dev_id == 2) - mac[5] = mac[5] + 6; + eth_addr_add(mac, 6); } debug("%s: MAC%d: %pM\n", __func__, dev_id, mac); @@ -673,11 +702,11 @@ int get_reset_reason(bool sys, bool lm) } if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { printf("SYS shutdown reason: %s, origin: %ld, errid: %ld\n", - rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], - out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, - out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1 + rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON], + out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags) : -1, + out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags) : -1 ); } } @@ -704,11 +733,11 @@ int get_reset_reason(bool sys, bool lm) if (out.shutdownflags & MISC_SHUTDOWN_FLAG_VLD) { printf("LM shutdown reason: %s, origin: %ld, errid: %ld\n", - rst[out.bootflags & MISC_SHUTDOWN_FLAG_REASON], - out.bootflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.bootflags) : -1, - out.bootflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? - FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.bootflags) : -1 + rst[out.shutdownflags & MISC_SHUTDOWN_FLAG_REASON], + out.shutdownflags & MISC_SHUTDOWN_FLAG_ORG_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ORIGIN, out.shutdownflags) : -1, + out.shutdownflags & MISC_SHUTDOWN_FLAG_ERR_VLD ? + FIELD_GET(MISC_SHUTDOWN_FLAG_ERR_ID, out.shutdownflags) : -1 ); } } @@ -1102,10 +1131,11 @@ enum boot_device get_boot_device(void) bool arch_check_dst_in_secure(void *start, ulong size) { - ulong ns_end = CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE; -#ifdef PHYS_SDRAM_2_SIZE - ns_end += PHYS_SDRAM_2_SIZE; -#endif + ulong ns_end; + phys_size_t dram_size; + + board_phys_sdram_size(&dram_size); + ns_end = CFG_SYS_SDRAM_BASE + dram_size; if ((ulong)start < CFG_SYS_SDRAM_BASE || (ulong)start + size > ns_end) return true; @@ -1115,5 +1145,10 @@ bool arch_check_dst_in_secure(void *start, ulong size) void *arch_get_container_trampoline(void) { - return (void *)((ulong)CFG_SYS_SDRAM_BASE + PHYS_SDRAM_SIZE - SZ_16M); + phys_size_t size; + + board_phys_sdram_size(&size); + size = (size > PHYS_SDRAM_SIZE) ? PHYS_SDRAM_SIZE : size; + + return (void *)((ulong)CFG_SYS_SDRAM_BASE + size - SZ_16M); } diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c index 0c731e76329..dcf2fff1aa6 100644 --- a/arch/arm/mach-imx/imx9/soc.c +++ b/arch/arm/mach-imx/imx9/soc.c @@ -21,6 +21,7 @@ #include <asm/armv8/mmu.h> #include <dm/device.h> #include <dm/device_compat.h> +#include <dm/ofnode.h> #include <dm/uclass.h> #include <env.h> #include <env_internal.h> @@ -738,13 +739,16 @@ int arch_cpu_init(void) int imx9_probe_mu(void) { struct udevice *devp; - int node, ret; + ofnode node; + int ret; u32 res; struct ele_get_info_data info; - node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "fsl,imx93-mu-s4"); + node = ofnode_by_compatible(ofnode_null(), "fsl,imx93-mu-s4"); + if (!ofnode_valid(node)) + return -ENODEV; - ret = uclass_get_device_by_of_offset(UCLASS_MISC, node, &devp); + ret = uclass_get_device_by_ofnode(UCLASS_MISC, node, &devp); if (ret) return ret; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 7ed4b24b751..a38adfed02b 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -95,10 +95,10 @@ config MX6_OCRAM_256KB bool "Support 256KB OCRAM" depends on MX6D || MX6Q help - Allows using the full 256KB size of the OCRAM on the MX6Q/MX6D series - of chips, such as for SPL. The OCRAM of the Lite series of chips is - only 128KB, so using this option will prevent the resulting code from - working on those chips. + Allows using the full 256KB size of the OCRAM on the MX6Q/MX6D series + of chips, such as for SPL. The OCRAM of the Lite series of chips is + only 128KB, so using this option will prevent the resulting code from + working on those chips. config MX6_DDRCAL bool "Include dynamic DDR calibration routines" @@ -698,10 +698,10 @@ config TARGET_BRPPT2 select SUPPORT_SPL select SPL_DM if SPL select SPL_OF_CONTROL if SPL - help - Support - B&R BRPPT2 platform - based on Freescale's iMX6 SoC + help + Support + B&R BRPPT2 platform + based on Freescale's iMX6 SoC config TARGET_O4_IMX6ULL_NANO bool "O4-iMX6ULL-NANO" diff --git a/arch/arm/mach-imx/mx6/clock.c b/arch/arm/mach-imx/mx6/clock.c index b5aa606b8d0..d366180e788 100644 --- a/arch/arm/mach-imx/mx6/clock.c +++ b/arch/arm/mach-imx/mx6/clock.c @@ -1452,7 +1452,7 @@ static void enable_ldb_di_clock_sources(void) * Try call this function as early in the boot process as possible since the * function temporarily disables PLL2 PFD's, PLL3 PFD's and PLL5. */ -void select_ldb_di_clock_source(enum ldb_di_clock clk) +void select_ldb_di_clock_source(enum ldb_di_clock clk0, enum ldb_di_clock clk1) { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; int reg; @@ -1525,8 +1525,8 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk) reg = readl(&mxc_ccm->cs2cdr); reg &= ~(MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK | MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK); - reg |= ((clk << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) - | (clk << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)); + reg |= ((clk0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (clk1 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET)); writel(reg, &mxc_ccm->cs2cdr); /* Unbypass pll3_sw_clk */ diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c index ca1cf759fe1..1dd350cf50e 100644 --- a/arch/arm/mach-imx/mx7ulp/soc.c +++ b/arch/arm/mach-imx/mx7ulp/soc.c @@ -259,11 +259,6 @@ void reset_cpu(void) #endif #if defined(CONFIG_DISPLAY_CPUINFO) -const char *get_imx_type(u32 imxtype) -{ - return "7ULP"; -} - int print_cpuinfo(void) { u32 cpurev; @@ -271,8 +266,7 @@ int print_cpuinfo(void) cpurev = get_cpu_rev(); - printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", - get_imx_type((cpurev & 0xFF000) >> 12), + printf("CPU: Freescale i.MX7ULP rev%d.%d at %d MHz\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); diff --git a/arch/arm/mach-k3/am64x/am642_init.c b/arch/arm/mach-k3/am64x/am642_init.c index a15adf1cb1e..d6cc7a85aae 100644 --- a/arch/arm/mach-k3/am64x/am642_init.c +++ b/arch/arm/mach-k3/am64x/am642_init.c @@ -212,14 +212,14 @@ void board_init_f(ulong dummy) #if defined(CONFIG_K3_LOAD_SYSFW) /* - * Process pinctrl for serial3 a.k.a. MAIN UART1 module and continue + * Process pinctrl for serial1 a.k.a. MAIN UART1 module and continue * regardless of the result of pinctrl. Do this without probing the * device, but instead by searching the device that would request the * given sequence number if probed. The UART will be used by the system * firmware (SYSFW) image for various purposes and SYSFW depends on us * to initialize its pin settings. */ - ret = uclass_find_device_by_seq(UCLASS_SERIAL, 3, &dev); + ret = uclass_find_device_by_seq(UCLASS_SERIAL, 1, &dev); if (!ret) pinctrl_select_state(dev, "default"); diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig index 9bf71a9b453..82efc9f7c40 100644 --- a/arch/arm/mach-keystone/Kconfig +++ b/arch/arm/mach-keystone/Kconfig @@ -18,9 +18,9 @@ config TARGET_K2L_EVM config TARGET_K2G_EVM bool "TI Keystone 2 Galileo EVM" - select BOARD_LATE_INIT + select BOARD_LATE_INIT select SOC_K2G - select TI_I2C_BOARD_DETECT + select TI_I2C_BOARD_DETECT endchoice diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig index f1ccedba5d7..8d56ca1a6e3 100644 --- a/arch/arm/mach-kirkwood/Kconfig +++ b/arch/arm/mach-kirkwood/Kconfig @@ -22,13 +22,13 @@ config KIRKWOOD_COMMON select SYS_NS16550 config HAS_CUSTOM_SYS_INIT_SP_ADDR - bool "Use a custom location for the initial stack pointer address" - default y + bool "Use a custom location for the initial stack pointer address" + default y config CUSTOM_SYS_INIT_SP_ADDR - hex "Static location for the initial stack pointer" - depends on HAS_CUSTOM_SYS_INIT_SP_ADDR - default 0x5ff000 + hex "Static location for the initial stack pointer" + depends on HAS_CUSTOM_SYS_INIT_SP_ADDR + default 0x5ff000 choice prompt "Marvell Kirkwood board select" diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 80f7185e929..5e6c50ca64d 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -45,7 +45,7 @@ config TARGET_MT7981 help The MediaTek MT7981 is a ARM64-based SoC with a dual-core Cortex-A53. including UART, SPI, USB, NAND, SNFI, PWM, Gigabit Ethernet, I2C, - built-in Wi-Fi, and PCIe. + built-in Wi-Fi, and PCIe. config TARGET_MT7986 bool "MediaTek MT7986 SoC" @@ -89,9 +89,9 @@ config TARGET_MT8188 select ARM64 help The MediaTek MT8188 is a ARM64-based SoC with a dual-core Cortex-A78 - cluster and a six-core Cortex-A55 cluster. It includes UART, SPI, - USB3.0 dual role, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and - several LPDDR3 and LPDDR4 options. + cluster and a six-core Cortex-A55 cluster. It includes UART, SPI, + USB3.0 dual role, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and + several LPDDR3 and LPDDR4 options. config TARGET_MT8189 bool "MediaTek MT8189 SoC" @@ -120,13 +120,13 @@ config TARGET_MT8365 I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options. config TARGET_MT8512 - bool "MediaTek MT8512 SoC" - select ARM64 - help - The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53. - including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, - IR RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth digital - and several LPDDR3 and LPDDR4 options. + bool "MediaTek MT8512 SoC" + select ARM64 + help + The MediaTek MT8512 is a ARM64-based SoC with a dual-core Cortex-A53. + including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM, + IR RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth digital + and several LPDDR3 and LPDDR4 options. config TARGET_MT8516 bool "MediaTek MT8516 SoC" @@ -154,7 +154,7 @@ config MTK_MEM_MAP_DDR_BASE_PHY hex "DDR physical base address" default 0x40000000 help - Target-specific DDR physical base address. + Target-specific DDR physical base address. config MTK_MEM_MAP_DDR_SIZE hex "DDR .size in mem_map" @@ -164,14 +164,14 @@ config MTK_MEM_MAP_DDR_SIZE default 0x40000000 if TARGET_MT7622 || TARGET_MT8512 default 0x20000000 help - Target-specific DDR region size in mem_map. + Target-specific DDR region size in mem_map. config MTK_MEM_MAP_MMIO_SIZE hex "MMIO .size in mem_map" default 0x40000000 if TARGET_MT7622 || TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7987 || TARGET_MT7988 || TARGET_MT8512 default 0x20000000 help - Target-specific MMIO region size in mem_map. + Target-specific MMIO region size in mem_map. endif @@ -199,8 +199,6 @@ config SYS_CONFIG_NAME default "mt7629" if TARGET_MT7629 default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 - default "mt7987" if TARGET_MT7987 - default "mt7988" if TARGET_MT7988 default "mt8183" if TARGET_MT8183 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 diff --git a/arch/arm/mach-mediatek/mt7988/init.c b/arch/arm/mach-mediatek/mt7988/init.c index 7f4d934bfe9..5b37a91cd72 100644 --- a/arch/arm/mach-mediatek/mt7988/init.c +++ b/arch/arm/mach-mediatek/mt7988/init.c @@ -6,6 +6,7 @@ #include <fdtdec.h> #include <init.h> +#include <linux/kernel.h> #include <linux/sizes.h> #include <asm/armv8/mmu.h> #include <asm/global_data.h> @@ -26,6 +27,15 @@ int dram_init(void) return 0; } +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + /* + * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like + * MMC requires DMA buffer allocated below SZ_4G. + */ + return min(gd->ram_top, SZ_4G); +} + void reset_cpu(ulong addr) { psci_system_reset(); diff --git a/arch/arm/mach-mediatek/mt8188/init.c b/arch/arm/mach-mediatek/mt8188/init.c index a48a41f3b97..1108bc19373 100644 --- a/arch/arm/mach-mediatek/mt8188/init.c +++ b/arch/arm/mach-mediatek/mt8188/init.c @@ -20,13 +20,13 @@ int dram_init(void) return fdtdec_setup_mem_size_base(); } -phys_size_t get_effective_memsize(void) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like * MMC requires DMA buffer allocated below SZ_4G. */ - return min(SZ_4G - gd->ram_base, gd->ram_size); + return min(gd->ram_top, SZ_4G); } void reset_cpu(void) diff --git a/arch/arm/mach-mediatek/mt8189/init.c b/arch/arm/mach-mediatek/mt8189/init.c index ec7587c3586..4435c75a656 100644 --- a/arch/arm/mach-mediatek/mt8189/init.c +++ b/arch/arm/mach-mediatek/mt8189/init.c @@ -20,13 +20,13 @@ int dram_init(void) return fdtdec_setup_mem_size_base(); } -phys_size_t get_effective_memsize(void) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like * MMC requires DMA buffer allocated below SZ_4G. */ - return min(SZ_4G - gd->ram_base, gd->ram_size); + return min(gd->ram_top, SZ_4G); } void reset_cpu(ulong addr) diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c index e31d4eec0fb..83cac9d01d6 100644 --- a/arch/arm/mach-mediatek/mt8195/init.c +++ b/arch/arm/mach-mediatek/mt8195/init.c @@ -20,13 +20,13 @@ int dram_init(void) return fdtdec_setup_mem_size_base(); } -phys_size_t get_effective_memsize(void) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* * Limit gd->ram_top not exceeding SZ_4G. Because some peripherals like * MMC requires DMA buffer allocated below SZ_4G. */ - return min(SZ_4G - gd->ram_base, gd->ram_size); + return min(gd->ram_top, SZ_4G); } int mtk_soc_early_init(void) diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c index bc1d515fcca..6a9ae776794 100644 --- a/arch/arm/mach-mediatek/mt8512/init.c +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -29,10 +29,10 @@ int dram_init(void) return fdtdec_setup_mem_size_base(); } -phys_size_t get_effective_memsize(void) +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { /* limit stack below tee reserve memory */ - return gd->ram_size - 6 * SZ_1M; + return gd->ram_base + gd->ram_size - 6 * SZ_1M; } void reset_cpu(void) diff --git a/arch/arm/mach-mediatek/tzcfg.c b/arch/arm/mach-mediatek/tzcfg.c index c8fe8ac0e9b..fbc96d96a4b 100644 --- a/arch/arm/mach-mediatek/tzcfg.c +++ b/arch/arm/mach-mediatek/tzcfg.c @@ -35,12 +35,13 @@ struct tz_reserved_region { }; static bool fix_tz_region(struct tz_reserved_region region[], - uint32_t used_regions) + uint32_t used_regions, + phys_addr_t ram_top) { phys_addr_t size; - if (region[0].addr + region[0].size > gd->ram_top) { - if (region[0].addr >= gd->ram_top) { + if (region[0].addr + region[0].size > ram_top) { + if (region[0].addr >= ram_top) { debug("Discarded region 0x%08llx, size 0x%llx\n", region[0].addr, region[0].size); @@ -50,7 +51,7 @@ static bool fix_tz_region(struct tz_reserved_region region[], return true; } - size = gd->ram_top - region[0].addr; + size = ram_top - region[0].addr; debug("Truncated region 0x%08llx, size 0x%llx -> 0x%llx\n", region[0].addr, region[0].size, size); @@ -63,12 +64,15 @@ static bool fix_tz_region(struct tz_reserved_region region[], phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { - phys_addr_t uboot_ram_top, pstore_size, uboot_size = 0; + phys_addr_t uboot_ram_top, ram_top, pstore_size = 0, uboot_size = 0; struct tz_reserved_region region[2], tmp; phys_addr_t top_addr, low_addr; struct arm_smccc_res res; u32 used_regions = 1; + /* ram_top must be <= 4GiB due to DMA limitations */ + ram_top = min_t(phys_addr_t, gd->ram_top, SZ_4G); + /* BL31 region */ arm_smccc_smc(MTK_SIP_GET_BL31_REGION, 0, 0, 0, 0, 0, 0, 0, &res); if (res.a0) { @@ -119,14 +123,14 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) } debug("Effective memory @ 0x%08zx, size 0x%llx\n", gd->ram_base, - gd->ram_top - gd->ram_base); + ram_top - gd->ram_base); /* Discard/fix region which is outside the effective memory */ - if (fix_tz_region(region, used_regions)) { + if (fix_tz_region(region, used_regions, ram_top)) { used_regions--; if (used_regions) { - if (fix_tz_region(region, used_regions)) + if (fix_tz_region(region, used_regions, ram_top)) used_regions--; } } @@ -144,7 +148,7 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) uboot_size += U_BOOT_MIN_STACK_SIZE + REGION_ALIGNMENT - 1; uboot_size &= ~(REGION_ALIGNMENT - 1); - uboot_ram_top = gd->ram_top & ~(REGION_ALIGNMENT - 1); + uboot_ram_top = ram_top & ~(REGION_ALIGNMENT - 1); if (!used_regions || (uboot_ram_top - region[0].addr - region[0].size >= uboot_size)) { diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig index 5394529658b..2a96a8418e2 100644 --- a/arch/arm/mach-omap2/omap5/Kconfig +++ b/arch/arm/mach-omap2/omap5/Kconfig @@ -64,7 +64,7 @@ config OMAP_PLATFORM_RESET_TIME_MAX_USEC 1: Time taken by the Osciallator to stop and restart 2: PMIC OTP time 3: Voltage ramp time, which can be derived using the PMIC slew rate - and value of voltage ramp needed. + and value of voltage ramp needed. if TARGET_DRA7XX_EVM || TARGET_AM57XX_EVM menu "Voltage Domain OPP selections" @@ -72,7 +72,7 @@ menu "Voltage Domain OPP selections" choice prompt "MPU Voltage Domain" default DRA7_MPU_OPP_NOM - help + help Select the Operating Performance Point(OPP) for the MPU voltage domain on DRA7xx & AM57xx SoCs. @@ -86,7 +86,7 @@ endchoice choice prompt "DSPEVE Voltage Domain" - help + help Select the Operating Performance Point(OPP) for the DSPEVE voltage domain on DRA7xx & AM57xx SoCs. @@ -110,7 +110,7 @@ endchoice choice prompt "IVA Voltage Domain" - help + help Select the Operating Performance Point(OPP) for the IVA voltage domain on DRA7xx & AM57xx SoCs. @@ -134,7 +134,7 @@ endchoice choice prompt "GPU Voltage Domain" - help + help Select the Operating Performance Point(OPP) for the GPU voltage domain on DRA7xx & AM57xx SoCs. diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig index 76d3998884d..4d1bfb778ee 100644 --- a/arch/arm/mach-owl/Kconfig +++ b/arch/arm/mach-owl/Kconfig @@ -1,21 +1,21 @@ if ARCH_OWL choice - prompt "Actions Semi Owl SoC Variant" + prompt "Actions Semi Owl SoC Variant" optional config MACH_S900 - bool "Actions Semi S900 SoC" - select ARM64 + bool "Actions Semi S900 SoC" + select ARM64 config MACH_S700 - bool "Actions Semi S700 SoC" - select ARM64 + bool "Actions Semi S700 SoC" + select ARM64 endchoice config TEXT_BASE - default 0x11000000 + default 0x11000000 config SYS_CONFIG_NAME default "owl-common" diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index d92fcae2bb5..1a2e7847c9e 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -607,8 +607,8 @@ config SPL_ROCKCHIP_BACK_TO_BROM depends on SPL help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, - SPL will return to the boot rom, which will then load the U-Boot - binary to keep going on. + SPL will return to the boot rom, which will then load the U-Boot + binary to keep going on. config TPL_ROCKCHIP_BACK_TO_BROM bool "TPL returns to bootrom" @@ -618,8 +618,8 @@ config TPL_ROCKCHIP_BACK_TO_BROM depends on TPL help Rockchip SoCs have ability to load SPL & U-Boot binary. If enabled, - SPL will return to the boot rom, which will then load the U-Boot - binary to keep going on. + SPL will return to the boot rom, which will then load the U-Boot + binary to keep going on. config ROCKCHIP_COMMON_BOARD bool "Rockchip common board file" @@ -661,7 +661,7 @@ config ROCKCHIP_BOOT_MODE_REG config ROCKCHIP_RK8XX_DISABLE_BOOT_ON_POWERON bool "Disable device boot on power plug-in" depends on PMIC_RK8XX - ---help--- + help Say Y here to prevent the device from booting up because of a plug-in event. When set, the device will boot briefly to determine why it was powered on, and if it was determined because of a plug-in event @@ -689,7 +689,7 @@ config ROCKCHIP_BROM_HELPER bool config SPL_ROCKCHIP_EARLYRETURN_TO_BROM - bool "SPL requires early-return (for RK3188-style BROM) to BROM" + bool "SPL requires early-return (for RK3188-style BROM) to BROM" depends on SPL && ENABLE_ARM_SOC_BOOT0_HOOK help Some Rockchip BROM variants (e.g. on the RK3188) load the @@ -710,7 +710,7 @@ config ROCKCHIP_DISABLE_FORCE_JTAG Rockchip SoCs can automatically switch between jtag and sdmmc based on the following rules: - all the SDMMC pins including SDMMC_DET set as SDMMC function in - GRF, + GRF, - force_jtag bit in GRF is 1, - SDMMC_DET is low (no card detected), @@ -727,7 +727,7 @@ config ROCKCHIP_DISABLE_FORCE_JTAG If unsure, say Y. config TPL_ROCKCHIP_EARLYRETURN_TO_BROM - bool "TPL requires early-return (for RK3188-style BROM) to BROM" + bool "TPL requires early-return (for RK3188-style BROM) to BROM" depends on TPL && ENABLE_ARM_SOC_BOOT0_HOOK help Some Rockchip BROM variants (e.g. on the RK3188) load the diff --git a/arch/arm/mach-rockchip/px30/Kconfig b/arch/arm/mach-rockchip/px30/Kconfig index 2b57b166894..adba1b49a52 100644 --- a/arch/arm/mach-rockchip/px30/Kconfig +++ b/arch/arm/mach-rockchip/px30/Kconfig @@ -18,7 +18,7 @@ config TARGET_PX30_CORE * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. * EDIMM2.2 is a Form Factor Capacitive Evaluation Board from Engicam. * PX30.Core needs to mount on top of EDIMM2.2 for creating complete - PX30.Core EDIMM2.2 Starter Kit. + PX30.Core EDIMM2.2 Starter Kit. PX30.Core CTOUCH2: * PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam. @@ -39,7 +39,7 @@ config TARGET_RINGNECK_PX30 bool "Theobroma Systems PX30-uQ7 (Ringneck)" help The PX30-uQ7 (Ringneck) SoM is a uQseven-compatible (40mmx70mm, - MXM-230 connector) system-on-module from Theobroma Systems[1], + MXM-230 connector) system-on-module from Theobroma Systems[1], featuring the Rockchip PX30. It provides the following feature set: diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig index 9ad1f54055b..ba694093990 100644 --- a/arch/arm/mach-rockchip/rk322x/Kconfig +++ b/arch/arm/mach-rockchip/rk322x/Kconfig @@ -27,10 +27,10 @@ config SPL_SERIAL default y config TPL_STACK - default 0x10088000 + default 0x10088000 config TPL_TEXT_BASE - default 0x10081000 + default 0x10081000 source "board/rockchip/evb_rk3229/Kconfig" diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 128ee362f8a..91e11910876 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -91,7 +91,7 @@ config TARGET_MIQI_RK3288 config TARGET_PHYCORE_RK3288 bool "phyCORE-RK3288" - select BOARD_LATE_INIT + select BOARD_LATE_INIT help Add basic support for the PCM-947 carrier board, a RK3288 based development board made by PHYTEC. This board works in a combination @@ -128,7 +128,7 @@ config TARGET_ROCK2 config TARGET_TINKER_RK3288 bool "Tinker-RK3288" - select BOARD_LATE_INIT + select BOARD_LATE_INIT select ROCKCHIP_COMMON_STACK_ADDR select TPL help @@ -173,7 +173,7 @@ config SPL_SERIAL default y config TPL_STACK - default 0xff718000 + default 0xff718000 config TPL_SYS_MALLOC_F_LEN default 0x2000 diff --git a/arch/arm/mach-rockchip/rk3308/Kconfig b/arch/arm/mach-rockchip/rk3308/Kconfig index b8d25c52542..540ddc93cd0 100644 --- a/arch/arm/mach-rockchip/rk3308/Kconfig +++ b/arch/arm/mach-rockchip/rk3308/Kconfig @@ -5,7 +5,7 @@ config TARGET_EVB_RK3308 select BOARD_LATE_INIT config TARGET_ROC_RK3308_CC - bool "Firefly roc-rk3308-cc" + bool "Firefly roc-rk3308-cc" select BOARD_LATE_INIT config ROCKCHIP_BOOT_MODE_REG diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig index a7be30bbd89..6c6ca02c309 100644 --- a/arch/arm/mach-rockchip/rk3368/Kconfig +++ b/arch/arm/mach-rockchip/rk3368/Kconfig @@ -13,14 +13,14 @@ config TARGET_GEEKBOX bool "GeekBox" config TARGET_EVB_PX5 - bool "Evb-PX5" + bool "Evb-PX5" select ARCH_EARLY_INIT_R - help - PX5 EVB is designed by Rockchip for automotive field - with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS - HDMI video input/output interface, audio codec ES8396, - WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity - sensor STK3410. + help + PX5 EVB is designed by Rockchip for automotive field + with integrated CVBS (TP2825) / MIPI DSI / CSI / LVDS + HDMI video input/output interface, audio codec ES8396, + WIFI/BT (on RTL8723BS), Gsensor BMA250E and light&proximity + sensor STK3410. endchoice config ROCKCHIP_BOOT_MODE_REG @@ -49,9 +49,9 @@ config SPL_STACK_R_ADDR default 0x04000000 config TPL_STACK - default 0xff8cffff + default 0xff8cffff config TPL_TEXT_BASE - default 0xff8c1000 + default 0xff8c1000 endif diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig index 5c21b08a5ae..d84a9da8ed5 100644 --- a/arch/arm/mach-rockchip/rk3399/Kconfig +++ b/arch/arm/mach-rockchip/rk3399/Kconfig @@ -145,10 +145,10 @@ config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds" config TPL_STACK - default 0xff8effff + default 0xff8effff config TPL_TEXT_BASE - default 0xff8c2000 + default 0xff8c2000 if BOOTCOUNT_LIMIT diff --git a/arch/arm/mach-rockchip/rk3528/rk3528.c b/arch/arm/mach-rockchip/rk3528/rk3528.c index f9bfc445b85..a39cb8be9a1 100644 --- a/arch/arm/mach-rockchip/rk3528/rk3528.c +++ b/arch/arm/mach-rockchip/rk3528/rk3528.c @@ -95,7 +95,7 @@ void rockchip_stimer_init(void) if (reg & TIMER_EN) return; - asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + asm volatile("msr cntfrq_el0, %x0" : : "r" (CONFIG_COUNTER_FREQUENCY)); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); diff --git a/arch/arm/mach-rockchip/rk3576/rk3576.c b/arch/arm/mach-rockchip/rk3576/rk3576.c index 1def4e87971..e3e93f66395 100644 --- a/arch/arm/mach-rockchip/rk3576/rk3576.c +++ b/arch/arm/mach-rockchip/rk3576/rk3576.c @@ -131,7 +131,7 @@ void rockchip_stimer_init(void) if (reg & TIMER_EN) return; - asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + asm volatile("msr cntfrq_el0, %x0" : : "r" (CONFIG_COUNTER_FREQUENCY)); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); writel((TIMER_EN << 16) | TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index c8de1a21024..f69792670d0 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -167,7 +167,7 @@ void rockchip_stimer_init(void) if (reg & TIMER_EN) return; - asm volatile("msr cntfrq_el0, %0" : : "r" (CONFIG_COUNTER_FREQUENCY)); + asm volatile("msr cntfrq_el0, %x0" : : "r" (CONFIG_COUNTER_FREQUENCY)); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT0_REG); writel(0xffffffff, HP_TIMER_BASE + HP_LOAD_COUNT1_REG); writel(TIMER_EN, HP_TIMER_BASE + HP_CTRL_REG); diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig index 43eeaa9c449..d066df9a86e 100644 --- a/arch/arm/mach-rockchip/rv1126/Kconfig +++ b/arch/arm/mach-rockchip/rv1126/Kconfig @@ -47,7 +47,7 @@ config TPL_LDSCRIPT default "arch/arm/mach-rockchip/u-boot-tpl.lds" config TPL_STACK - default 0xff718000 + default 0xff718000 config TPL_SYS_MALLOC_F_LEN default 0x2000 diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index f0923186fa6..2e404df1b20 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -294,10 +294,20 @@ __weak int rockchip_dram_init_banksize_fixup(struct bd_info *bd) return 0; } +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + /* Make sure U-Boot only uses the space below the 4G address boundary */ + u64 usable_top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G); + + return (gd->ram_top > usable_top) ? usable_top : gd->ram_top; +} + int dram_init_banksize(void) { - size_t ram_top = (unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE); - size_t top = min((unsigned long)ram_top, (unsigned long)(gd->ram_top)); + /* Make sure first bank uses the space below the 4G address boundary */ + u64 usable_top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G); + size_t ram_top = (unsigned long)(CFG_SYS_SDRAM_BASE + gd->ram_size); + size_t top = min((unsigned long)ram_top, (unsigned long)(usable_top)); #ifdef CONFIG_ARM64 int ret = rockchip_dram_init_banksize(); @@ -507,11 +517,3 @@ int dram_init(void) return 0; } - -phys_addr_t board_get_usable_ram_top(phys_size_t total_size) -{ - /* Make sure U-Boot only uses the space below the 4G address boundary */ - u64 top = min_t(u64, CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE, SZ_4G); - - return (gd->ram_top > top) ? top : gd->ram_top; -} diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index fb98b647442..a9b639a5ed9 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -15,8 +15,8 @@ config SOCFPGA_SECURE_VAB_AUTH select SHA512 select SPL_FIT_IMAGE_POST_PROCESS help - All images loaded from FIT will be authenticated by Secure Device - Manager. + All images loaded from FIT will be authenticated by Secure Device + Manager. config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE bool "Allow non-FIT VAB signed images" diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig index d9e264024c8..df26e7b8ef2 100644 --- a/arch/arm/mach-sti/Kconfig +++ b/arch/arm/mach-sti/Kconfig @@ -14,7 +14,7 @@ config TARGET_STIH410_B2260 Specifications. Features: - 1GB DDR - On-Board USB combo WiFi/Bluetooth RTL8723BU - with PCB soldered antenna + with PCB soldered antenna - Ethernet 1000-BaseT - Sata - HDMI diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index 39f25869c1d..f45010ddbd0 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -56,8 +56,8 @@ config STM32MP13X imply CMD_NVEDIT_INFO imply OF_UPSTREAM help - support of STMicroelectronics SOC STM32MP13x family - STMicroelectronics MPU with core ARMv7 + support of STMicroelectronics SOC STM32MP13x family + STMicroelectronics MPU with core ARMv7 config STM32MP15X bool "Support STMicroelectronics STM32MP15x Soc" @@ -77,10 +77,10 @@ config STM32MP15X imply CMD_NVEDIT_INFO imply OF_UPSTREAM help - support of STMicroelectronics SOC STM32MP15x family - STM32MP157, STM32MP153 or STM32MP151 - STMicroelectronics MPU with core ARMv7 - dual core A7 for STM32MP157/3, monocore for STM32MP151 + support of STMicroelectronics SOC STM32MP15x family + STM32MP157, STM32MP153 or STM32MP151 + STMicroelectronics MPU with core ARMv7 + dual core A7 for STM32MP157/3, monocore for STM32MP151 config STM32MP21X bool "Support STMicroelectronics STM32MP21x Soc" @@ -104,8 +104,8 @@ config STM32MP21X imply TEE imply VERSION_VARIABLE help - Support of STMicroelectronics SOC STM32MP21X family - STMicroelectronics MPU with 1 A35 core and 1 M33 core + Support of STMicroelectronics SOC STM32MP21X family + STMicroelectronics MPU with 1 A35 core and 1 M33 core config STM32MP23X bool "Support STMicroelectronics STM32MP23x Soc" @@ -129,8 +129,8 @@ config STM32MP23X imply TEE imply VERSION_VARIABLE help - Support of STMicroelectronics SOC STM32MP23x family - STMicroelectronics MPU with 2 * A53 core and 1 M33 core + Support of STMicroelectronics SOC STM32MP23x family + STMicroelectronics MPU with 2 * A53 core and 1 M33 core config STM32MP25X bool "Support STMicroelectronics STM32MP25x Soc" @@ -153,8 +153,8 @@ config STM32MP25X imply TEE imply VERSION_VARIABLE help - Support of STMicroelectronics SOC STM32MP25x family - STMicroelectronics MPU with 2 * A53 core and 1 M33 core + Support of STMicroelectronics SOC STM32MP25x family + STMicroelectronics MPU with 2 * A53 core and 1 M33 core endchoice config NR_DRAM_BANKS @@ -164,13 +164,13 @@ config DDR_CACHEABLE_SIZE hex "Size of the DDR marked cacheable in pre-reloc stage" default 0x40000000 help - Define the size of the DDR marked as cacheable in U-Boot - pre-reloc stage. - This option can be useful to avoid speculatif access - to secured area of DDR used by TF-A or OP-TEE before U-Boot - initialization. - The areas marked "no-map" in device tree should be located - before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. + Define the size of the DDR marked as cacheable in U-Boot + pre-reloc stage. + This option can be useful to avoid speculatif access + to secured area of DDR used by TF-A or OP-TEE before U-Boot + initialization. + The areas marked "no-map" in device tree should be located + before this limit: STM32_DDR_BASE + DDR_CACHEABLE_SIZE. config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 hex "Partition on MMC2 to use to load U-Boot from" @@ -203,10 +203,10 @@ config CMD_STM32KEY bool "command stm32key to fuse public key hash" depends on CMDLINE help - fuse public key hash in corresponding fuse used to authenticate - binary. - This command is used to evaluate the secure boot on stm32mp SOC, - it is deactivated by default in real products. + fuse public key hash in corresponding fuse used to authenticate + binary. + This command is used to evaluate the secure boot on stm32mp SOC, + it is deactivated by default in real products. config MFD_STM32_TIMERS bool "STM32 multifonction timer support" @@ -226,15 +226,15 @@ config STM32MP15_PWR depends on DM_REGULATOR && DM_PMIC && (STM32MP13X || STM32MP15X) default y if STM32MP15X help - This config enables implementation of driver-model pmic and - regulator uclass features for access to STM32MP15x PWR. + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR. config SPL_STM32MP15_PWR bool "Enable driver for STM32MP15x PWR in SPL" depends on SPL && SPL_DM_REGULATOR && SPL_DM_PMIC && (STM32MP13X || STM32MP15X) default y if STM32MP15X help - This config enables implementation of driver-model pmic and - regulator uclass features for access to STM32MP15x PWR in SPL. + This config enables implementation of driver-model pmic and + regulator uclass features for access to STM32MP15x PWR in SPL. endif diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig index 647e0a4c2bf..5ae57d13340 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig @@ -10,10 +10,10 @@ config CMD_STM32PROG imply DFU_MMC if MMC imply DFU_MTD if MTD help - activate a specific command stm32prog for STM32MP soc family - witch update the device with the tools STM32CubeProgrammer - NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based - on U-Boot DFU framework + activate a specific command stm32prog for STM32MP soc family + witch update the device with the tools STM32CubeProgrammer + NB: access to not volatile memory (NOR/NAND/SD/eMMC) is based + on U-Boot DFU framework config CMD_STM32PROG_USB bool "support stm32prog over USB" @@ -21,9 +21,9 @@ config CMD_STM32PROG_USB depends on USB_GADGET_DOWNLOAD default y help - activate the command "stm32prog usb" for STM32MP soc family - witch update the device with the tools STM32CubeProgrammer, - using USB with DFU protocol + activate the command "stm32prog usb" for STM32MP soc family + witch update the device with the tools STM32CubeProgrammer, + using USB with DFU protocol config CMD_STM32PROG_SERIAL bool "support stm32prog over UART" @@ -32,13 +32,13 @@ config CMD_STM32PROG_SERIAL imply SILENT_CONSOLE default y help - activate the command "stm32prog serial" for STM32MP soc family - with the tools STM32CubeProgrammer using U-Boot serial device - and UART protocol. + activate the command "stm32prog serial" for STM32MP soc family + with the tools STM32CubeProgrammer using U-Boot serial device + and UART protocol. config CMD_STM32PROG_OTP bool "support stm32prog for OTP update" depends on CMD_STM32PROG default y if ARM_SMCCC || OPTEE help - Support the OTP update with the command "stm32prog" for STM32MP + Support the OTP update with the command "stm32prog" for STM32MP diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index ceba96b61a5..5ace74567dd 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -223,11 +223,11 @@ config SUNXI_SRAM_ADDRESS default 0x44000 if MACH_SUN55I_A523 default 0x20000 if SUN50I_GEN_H6 || SUNXI_GEN_NCAT2 default 0x0 - ---help--- - Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, - with the first SRAM region being located at address 0. - Some newer SoCs map the boot ROM at address 0 instead and move the - SRAM to a different address. + help + Older Allwinner SoCs have their mask boot ROM mapped just below 4GB, + with the first SRAM region being located at address 0. + Some newer SoCs map the boot ROM at address 0 instead and move the + SRAM to a different address. config SUNXI_RVBAR_ADDRESS hex @@ -236,26 +236,26 @@ config SUNXI_RVBAR_ADDRESS default 0x08000040 if MACH_SUN55I_A523 default 0x09010040 if SUN50I_GEN_H6 default 0x017000a0 - ---help--- - The read-only RVBAR system register holds the address of the first - instruction to execute after a reset. Allwinner cores provide a - writable MMIO backing store for this register, to allow to set the - entry point when switching to AArch64. This store is on different - addresses, depending on the SoC. + help + The read-only RVBAR system register holds the address of the first + instruction to execute after a reset. Allwinner cores provide a + writable MMIO backing store for this register, to allow to set the + entry point when switching to AArch64. This store is on different + addresses, depending on the SoC. config SUNXI_RVBAR_ALTERNATIVE hex depends on ARM64 default 0x08100040 if MACH_SUN50I_H616 default SUNXI_RVBAR_ADDRESS - ---help--- - The H616 die exists in at least two variants, with one having the - RVBAR registers at a different address. If the SoC variant ID - (stored in SRAM_VER_REG[7:0]) is not 0, we need to use the - other address. - Set this alternative address to the same as the normal address - for all other SoCs, so the content of the SRAM_VER_REG becomes - irrelevant there, and we can use the same code. + help + The H616 die exists in at least two variants, with one having the + RVBAR registers at a different address. If the SoC variant ID + (stored in SRAM_VER_REG[7:0]) is not 0, we need to use the + other address. + Set this alternative address to the same as the normal address + for all other SoCs, so the content of the SRAM_VER_REG becomes + irrelevant there, and we can use the same code. config SUNXI_BL31_BASE hex @@ -282,16 +282,16 @@ config SUNXI_A64_TIMER_ERRATUM # not supported by Kconfig config SUNXI_GEN_SUN4I bool - ---help--- - Select this for sunxi SoCs which have resets and clocks set up - as the original A10 (mach-sun4i). + help + Select this for sunxi SoCs which have resets and clocks set up + as the original A10 (mach-sun4i). config SUNXI_GEN_SUN6I bool - ---help--- - Select this for sunxi SoCs which have sun6i like periphery, like - separate ahb reset control registers, custom pmic bus, new style - watchdog, etc. + help + Select this for sunxi SoCs which have sun6i like periphery, like + separate ahb reset control registers, custom pmic bus, new style + watchdog, etc. config SUN50I_GEN_H6 bool @@ -299,38 +299,38 @@ config SUN50I_GEN_H6 select SPL_LOAD_FIT if SPL select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL - ---help--- - Select this for sunxi SoCs which have H6 like peripherals, clocks - and memory map. + help + Select this for sunxi SoCs which have H6 like peripherals, clocks + and memory map. config SUNXI_GEN_NCAT2 bool select MMC_SUNXI_HAS_NEW_MODE select SUPPORT_SPL - ---help--- - Select this for sunxi SoCs which have D1 like peripherals, clocks - and memory map. + help + Select this for sunxi SoCs which have D1 like peripherals, clocks + and memory map. config SUNXI_DRAM_DW bool - ---help--- - Select this for sunxi SoCs which uses a DRAM controller like the - DesignWare controller used in H3, mainly SoCs after H3, which do - not have official open-source DRAM initialization code, but can - use modified H3 DRAM initialization code. + help + Select this for sunxi SoCs which uses a DRAM controller like the + DesignWare controller used in H3, mainly SoCs after H3, which do + not have official open-source DRAM initialization code, but can + use modified H3 DRAM initialization code. if SUNXI_DRAM_DW config SUNXI_DRAM_DW_16BIT bool - ---help--- - Select this for sunxi SoCs with DesignWare DRAM controller and - have only 16-bit memory buswidth. + help + Select this for sunxi SoCs with DesignWare DRAM controller and + have only 16-bit memory buswidth. config SUNXI_DRAM_DW_32BIT bool - ---help--- - Select this for sunxi SoCs with DesignWare DRAM controller with - 32-bit memory buswidth. + help + Select this for sunxi SoCs with DesignWare DRAM controller with + 32-bit memory buswidth. endif config MACH_SUNXI_H3_H5 @@ -576,25 +576,25 @@ config MACH_SUN8I config RESERVE_ALLWINNER_BOOT0_HEADER bool "reserve space for Allwinner boot0 header" select ENABLE_ARM_SOC_BOOT0_HOOK - ---help--- - Prepend a 1536 byte (empty) header to the U-Boot image file, to be - filled with magic values post build. The Allwinner provided boot0 - blob relies on this information to load and execute U-Boot. - Only needed on 64-bit Allwinner boards so far when using boot0. + help + Prepend a 1536 byte (empty) header to the U-Boot image file, to be + filled with magic values post build. The Allwinner provided boot0 + blob relies on this information to load and execute U-Boot. + Only needed on 64-bit Allwinner boards so far when using boot0. config ARM_BOOT_HOOK_RMR bool depends on ARM64 default y select ENABLE_ARM_SOC_BOOT0_HOOK - ---help--- - Insert some ARM32 code at the very beginning of the U-Boot binary - which uses an RMR register write to bring the core into AArch64 mode. - The very first instruction acts as a switch, since it's carefully - chosen to be a NOP in one mode and a branch in the other, so the - code would only be executed if not already in AArch64. - This allows both the SPL and the U-Boot proper to be entered in - either mode and switch to AArch64 if needed. + help + Insert some ARM32 code at the very beginning of the U-Boot binary + which uses an RMR register write to bring the core into AArch64 mode. + The very first instruction acts as a switch, since it's carefully + chosen to be a NOP in one mode and a branch in the other, so the + code would only be executed if not already in AArch64. + This allows both the SPL and the U-Boot proper to be entered in + either mode and switch to AArch64 if needed. if SUNXI_DRAM_DW || DRAM_SUN50I_H6 || DRAM_SUN50I_H616 || DRAM_SUN50I_A133 || DRAM_SUN55I_A523 config SUNXI_DRAM_DDR3 @@ -622,33 +622,33 @@ config SUNXI_DRAM_DDR3_1333 bool "DDR3 1333" select SUNXI_DRAM_DDR3 depends on !DRAM_SUN50I_A133 - ---help--- - This option is the original only supported memory type, which suits - many H3/H5/A64 boards available now. + help + This option is the original only supported memory type, which suits + many H3/H5/A64 boards available now. config SUNXI_DRAM_LPDDR3_STOCK bool "LPDDR3 with Allwinner stock configuration" select SUNXI_DRAM_LPDDR3 depends on !DRAM_SUN50I_A133 - ---help--- - This option is the LPDDR3 timing used by the stock boot0 by - Allwinner. + help + This option is the LPDDR3 timing used by the stock boot0 by + Allwinner. config SUNXI_DRAM_H6_LPDDR3 bool "LPDDR3 DRAM chips on the H6 DRAM controller" select SUNXI_DRAM_LPDDR3 depends on DRAM_SUN50I_H6 - ---help--- - This option is the LPDDR3 timing used by the stock boot0 by - Allwinner. + help + This option is the LPDDR3 timing used by the stock boot0 by + Allwinner. config SUNXI_DRAM_H6_DDR3_1333 bool "DDR3-1333 boot0 timings on the H6 DRAM controller" select SUNXI_DRAM_DDR3 depends on DRAM_SUN50I_H6 - ---help--- - This option is the DDR3 timing used by the boot0 on H6 TV boxes - which use a DDR3-1333 timing. + help + This option is the DDR3 timing used by the boot0 on H6 TV boxes + which use a DDR3-1333 timing. config SUNXI_DRAM_H616_LPDDR3 bool "LPDDR3 DRAM chips on the H616 DRAM controller" @@ -694,9 +694,9 @@ config SUNXI_DRAM_DDR2_V3S bool "DDR2 found in V3s chip" select SUNXI_DRAM_DDR2 depends on MACH_SUN8I_V3S - ---help--- - This option is only for the DDR2 memory chip which is co-packaged in - Allwinner V3s SoC. + help + This option is only for the DDR2 memory chip which is co-packaged in + Allwinner V3s SoC. config SUNXI_DRAM_A523_DDR3 bool "DDR3 DRAM chips on the A523/T527 DRAM controller" @@ -720,8 +720,8 @@ config DRAM_TYPE int "sunxi dram type" depends on MACH_SUN8I_A83T default 3 - ---help--- - Set the dram type, 3: DDR3, 7: LPDDR3 + help + Set the dram type, 3: DDR3, 7: LPDDR3 config DRAM_CLK int "sunxi dram clock speed" @@ -734,17 +734,17 @@ config DRAM_CLK default 744 if MACH_SUN50I_H6 default 720 if MACH_SUN50I_H616 || MACH_SUN50I_A133 default 1200 if MACH_SUN55I_A523 - ---help--- - Set the dram clock speed, valid range 240 - 480 (prior to sun9i), - must be a multiple of 24. For the sun9i (A80), the tested values - (for DDR3-1600) are 312 to 792. + help + Set the dram clock speed, valid range 240 - 480 (prior to sun9i), + must be a multiple of 24. For the sun9i (A80), the tested values + (for DDR3-1600) are 312 to 792. if MACH_SUN5I || MACH_SUN7I config DRAM_MBUS_CLK int "sunxi mbus clock speed" default 300 - ---help--- - Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. + help + Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. endif @@ -760,8 +760,8 @@ config DRAM_ZQ default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6 default 4145117 if MACH_SUN9I default 3881915 if MACH_SUN50I - ---help--- - Set the dram zq value. + help + Set the dram zq value. config DRAM_ODT_EN bool "sunxi dram odt enable" @@ -772,72 +772,72 @@ config DRAM_ODT_EN default y if MACH_SUN8I_R40 default y if MACH_SUN50I default y if MACH_SUN50I_H6 - ---help--- - Select this to enable dram odt (on die termination). + help + Select this to enable dram odt (on die termination). if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I config DRAM_EMR1 int "sunxi dram emr1 value" default 0 if MACH_SUN4I default 4 if MACH_SUN5I || MACH_SUN7I - ---help--- - Set the dram controller emr1 value. + help + Set the dram controller emr1 value. config DRAM_TPR3 hex "sunxi dram tpr3 value" default 0x0 - ---help--- - Set the dram controller tpr3 parameter. This parameter configures - the delay on the command lane and also phase shifts, which are - applied for sampling incoming read data. The default value 0 - means that no phase/delay adjustments are necessary. Properly - configuring this parameter increases reliability at high DRAM - clock speeds. + help + Set the dram controller tpr3 parameter. This parameter configures + the delay on the command lane and also phase shifts, which are + applied for sampling incoming read data. The default value 0 + means that no phase/delay adjustments are necessary. Properly + configuring this parameter increases reliability at high DRAM + clock speeds. config DRAM_DQS_GATING_DELAY hex "sunxi dram dqs_gating_delay value" default 0x0 - ---help--- - Set the dram controller dqs_gating_delay parmeter. Each byte - encodes the DQS gating delay for each byte lane. The delay - granularity is 1/4 cycle. For example, the value 0x05060606 - means that the delay is 5 quarter-cycles for one lane (1.25 - cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. - The default value 0 means autodetection. The results of hardware - autodetection are not very reliable and depend on the chip - temperature (sometimes producing different results on cold start - and warm reboot). But the accuracy of hardware autodetection - is usually good enough, unless running at really high DRAM - clocks speeds (up to 600MHz). If unsure, keep as 0. + help + Set the dram controller dqs_gating_delay parmeter. Each byte + encodes the DQS gating delay for each byte lane. The delay + granularity is 1/4 cycle. For example, the value 0x05060606 + means that the delay is 5 quarter-cycles for one lane (1.25 + cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. + The default value 0 means autodetection. The results of hardware + autodetection are not very reliable and depend on the chip + temperature (sometimes producing different results on cold start + and warm reboot). But the accuracy of hardware autodetection + is usually good enough, unless running at really high DRAM + clocks speeds (up to 600MHz). If unsure, keep as 0. choice prompt "sunxi dram timings" default DRAM_TIMINGS_VENDOR_MAGIC - ---help--- - Select the timings of the DDR3 chips. + help + Select the timings of the DDR3 chips. config DRAM_TIMINGS_VENDOR_MAGIC bool "Magic vendor timings from Android" - ---help--- - The same DRAM timings as in the Allwinner boot0 bootloader. + help + The same DRAM timings as in the Allwinner boot0 bootloader. config DRAM_TIMINGS_DDR3_1066F_1333H bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" - ---help--- - Use the timings of the standard JEDEC DDR3-1066F speed bin for - DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin - for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips - used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 - or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm - that down binning to DDR3-1066F is supported (because DDR3-1066F - uses a bit faster timings than DDR3-1333H). + help + Use the timings of the standard JEDEC DDR3-1066F speed bin for + DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin + for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips + used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 + or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm + that down binning to DDR3-1066F is supported (because DDR3-1066F + uses a bit faster timings than DDR3-1333H). config DRAM_TIMINGS_DDR3_800E_1066G_1333J bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" - ---help--- - Use the timings of the slowest possible JEDEC speed bin for the - selected DRAM_CLK. Depending on the DRAM_CLK value, it may be - DDR3-800E, DDR3-1066G or DDR3-1333J. + help + Use the timings of the slowest possible JEDEC speed bin for the + selected DRAM_CLK. Depending on the DRAM_CLK value, it may be + DDR3-800E, DDR3-1066G or DDR3-1333J. endchoice @@ -847,11 +847,11 @@ if MACH_SUN8I_A23 config DRAM_ODT_CORRECTION int "sunxi dram odt correction value" default 0 - ---help--- - Set the dram odt correction value (range -255 - 255). In allwinner - fex files, this option is found in bits 8-15 of the u32 odt_en variable - in the [dram] section. When bit 31 of the odt_en variable is set - then the correction is negative. Usually the value for this is 0. + help + Set the dram odt correction value (range -255 - 255). In allwinner + fex files, this option is found in bits 8-15 of the u32 odt_en variable + in the [dram] section. When bit 31 of the odt_en variable is set + then the correction is negative. Usually the value for this is 0. endif config SYS_CLK_FREQ @@ -888,59 +888,59 @@ config SUNXI_MINIMUM_DRAM_MB default 32 if MACH_SUNIV default 64 if MACH_SUN8I_V3S default 256 - ---help--- - Minimum DRAM size expected on the board. Traditionally we assumed - 256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM - we have smaller sizes, though, so that U-Boot's own load address and - the default payload addresses must be shifted down. - This is expected to be fixed by the SoC selection. + help + Minimum DRAM size expected on the board. Traditionally we assumed + 256 MB, so that U-Boot would load at 160MB. With co-packaged DRAM + we have smaller sizes, though, so that U-Boot's own load address and + the default payload addresses must be shifted down. + This is expected to be fixed by the SoC selection. config UART0_PORT_F bool "UART0 on MicroSD breakout board" - ---help--- - Repurpose the SD card slot for getting access to the UART0 serial - console. Primarily useful only for low level u-boot debugging on - tablets, where normal UART0 is difficult to access and requires - device disassembly and/or soldering. As the SD card can't be used - at the same time, the system can be only booted in the FEL mode. - Only enable this if you really know what you are doing. + help + Repurpose the SD card slot for getting access to the UART0 serial + console. Primarily useful only for low level u-boot debugging on + tablets, where normal UART0 is difficult to access and requires + device disassembly and/or soldering. As the SD card can't be used + at the same time, the system can be only booted in the FEL mode. + Only enable this if you really know what you are doing. config OLD_SUNXI_KERNEL_COMPAT bool "Enable workarounds for booting old kernels" - ---help--- - Set this to enable various workarounds for old kernels, this results in - sub-optimal settings for newer kernels, only enable if needed. + help + Set this to enable various workarounds for old kernels, this results in + sub-optimal settings for newer kernels, only enable if needed. config MMC1_PINS_PH bool "Pins for mmc1 are on Port H" depends on MACH_SUN4I || MACH_SUN7I || MACH_SUN8I_R40 - ---help--- - Select this option for boards where mmc1 uses the Port H pinmux. + help + Select this option for boards where mmc1 uses the Port H pinmux. config MMC_SUNXI_SLOT_EXTRA int "mmc extra slot number" default -1 - ---help--- - sunxi builds always enable mmc0, some boards also have a second sdcard - slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable - support for this. + help + sunxi builds always enable mmc0, some boards also have a second sdcard + slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable + support for this. config I2C0_ENABLE bool "Enable I2C/TWI controller 0" default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40 default n if MACH_SUN6I || MACH_SUN8I select CMD_I2C - ---help--- - This allows enabling I2C/TWI controller 0 by muxing its pins, enabling - its clock and setting up the bus. This is especially useful on devices - with slaves connected to the bus or with pins exposed through e.g. an - expansion port/header. + help + This allows enabling I2C/TWI controller 0 by muxing its pins, enabling + its clock and setting up the bus. This is especially useful on devices + with slaves connected to the bus or with pins exposed through e.g. an + expansion port/header. config I2C1_ENABLE bool "Enable I2C/TWI controller 1" select CMD_I2C - ---help--- - See I2C0_ENABLE help text. + help + See I2C0_ENABLE help text. if SUNXI_GEN_SUN6I || SUN50I_GEN_H6 || SUNXI_GEN_NCAT2 config R_I2C_ENABLE @@ -948,20 +948,20 @@ config R_I2C_ENABLE # This is used for the pmic on H3 default y if SY8106A_POWER select CMD_I2C - ---help--- - Set this to y to enable the I2C controller which is part of the PRCM. + help + Set this to y to enable the I2C controller which is part of the PRCM. endif config AXP_GPIO bool "Enable support for gpio-s on axp PMICs" depends on AXP_PMIC_BUS - ---help--- - Say Y here to enable support for the gpio pins of the axp PMIC ICs. + help + Say Y here to enable support for the gpio pins of the axp PMIC ICs. config AXP_DISABLE_BOOT_ON_POWERON bool "Disable device boot on power plug-in" depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER - ---help--- + help Say Y here to prevent the device from booting up because of a plug-in event. When set, the device will boot into the SPL briefly to determine why it was powered on, and if it was determined because of @@ -982,127 +982,127 @@ config VIDEO_SUNXI imply VIDEO_DAMAGE imply VIDEO_DT_SIMPLEFB default y - ---help--- - Say Y here to add support for using a graphical console on the HDMI, - LCD or VGA output found on older sunxi devices. This will also provide - a simple_framebuffer device for Linux. + help + Say Y here to add support for using a graphical console on the HDMI, + LCD or VGA output found on older sunxi devices. This will also provide + a simple_framebuffer device for Linux. config VIDEO_HDMI bool "HDMI output support" depends on VIDEO_SUNXI && !MACH_SUN8I && !MACH_SUNIV default y - ---help--- - Say Y here to add support for outputting video over HDMI. + help + Say Y here to add support for outputting video over HDMI. config VIDEO_VGA bool "VGA output support" depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I) - ---help--- - Say Y here to add support for outputting video over VGA. + help + Say Y here to add support for outputting video over VGA. config VIDEO_VGA_VIA_LCD bool "VGA via LCD controller support" depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I) - ---help--- - Say Y here to add support for external DACs connected to the parallel - LCD interface driving a VGA connector, such as found on the - Olimex A13 boards. + help + Say Y here to add support for external DACs connected to the parallel + LCD interface driving a VGA connector, such as found on the + Olimex A13 boards. config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH bool "Force sync active high for VGA via LCD controller support" depends on VIDEO_VGA_VIA_LCD - ---help--- - Say Y here if you've a board which uses opendrain drivers for the vga - hsync and vsync signals. Opendrain drivers cannot generate steep enough - positive edges for a stable video output, so on boards with opendrain - drivers the sync signals must always be active high. + help + Say Y here if you've a board which uses opendrain drivers for the vga + hsync and vsync signals. Opendrain drivers cannot generate steep enough + positive edges for a stable video output, so on boards with opendrain + drivers the sync signals must always be active high. config VIDEO_VGA_EXTERNAL_DAC_EN string "LCD panel power enable pin" depends on VIDEO_VGA_VIA_LCD default "" - ---help--- - Set the enable pin for the external VGA DAC. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + help + Set the enable pin for the external VGA DAC. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. config VIDEO_COMPOSITE bool "Composite video output support" depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I) - ---help--- - Say Y here to add support for outputting composite video. + help + Say Y here to add support for outputting composite video. config VIDEO_LCD_MODE string "LCD panel timing details" depends on VIDEO_SUNXI default "" - ---help--- - LCD panel timing details string, leave empty if there is no LCD panel. - This is in drivers/video/videomodes.c: video_get_params() format, e.g. - x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 - Also see: http://linux-sunxi.org/LCD + help + LCD panel timing details string, leave empty if there is no LCD panel. + This is in drivers/video/videomodes.c: video_get_params() format, e.g. + x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0 + Also see: http://linux-sunxi.org/LCD config VIDEO_LCD_DCLK_PHASE int "LCD panel display clock phase" depends on VIDEO_SUNXI || VIDEO default 1 range 0 3 - ---help--- - Select LCD panel display clock phase shift + help + Select LCD panel display clock phase shift config VIDEO_LCD_POWER string "LCD panel power enable pin" depends on VIDEO_SUNXI default "" - ---help--- - Set the power enable pin for the LCD panel. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + help + Set the power enable pin for the LCD panel. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_RESET string "LCD panel reset pin" depends on VIDEO_SUNXI default "" - ---help--- - Set the reset pin for the LCD panel. This takes a string in the format - understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + help + Set the reset pin for the LCD panel. This takes a string in the format + understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_BL_EN string "LCD panel backlight enable pin" depends on VIDEO_SUNXI default "" - ---help--- - Set the backlight enable pin for the LCD panel. This takes a string in the - the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of - port H. + help + Set the backlight enable pin for the LCD panel. This takes a string in the + the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of + port H. config VIDEO_LCD_BL_PWM string "LCD panel backlight pwm pin" depends on VIDEO_SUNXI default "" - ---help--- - Set the backlight pwm pin for the LCD panel. This takes a string in the - format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + help + Set the backlight pwm pin for the LCD panel. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_BL_PWM_ACTIVE_LOW bool "LCD panel backlight pwm is inverted" depends on VIDEO_SUNXI default y - ---help--- - Set this if the backlight pwm output is active low. + help + Set this if the backlight pwm output is active low. config VIDEO_LCD_PANEL_I2C bool "LCD panel needs to be configured via i2c" depends on VIDEO_SUNXI select DM_I2C_GPIO - ---help--- - Say y here if the LCD panel needs to be configured via i2c. This - will add a bitbang i2c controller using gpios to talk to the LCD. + help + Say y here if the LCD panel needs to be configured via i2c. This + will add a bitbang i2c controller using gpios to talk to the LCD. config VIDEO_LCD_PANEL_I2C_NAME string "LCD panel i2c interface node name" depends on VIDEO_LCD_PANEL_I2C default "i2c" - ---help--- - Set the device tree node name for the LCD i2c interface. + help + Set the device tree node name for the LCD i2c interface. # Note only one of these may be selected at a time! But hidden choices are # not supported by Kconfig @@ -1123,16 +1123,16 @@ config VIDEO_DE2 select VIDEO_DW_HDMI imply VIDEO_DT_SIMPLEFB default y - ---help--- - Say y here if you want to build DE2 video driver which is present on - newer SoCs. Currently only HDMI output is supported. + help + Say y here if you want to build DE2 video driver which is present on + newer SoCs. Currently only HDMI output is supported. choice prompt "LCD panel support" depends on VIDEO_SUNXI - ---help--- - Select which type of LCD panel to support. + help + Select which type of LCD panel to support. config VIDEO_LCD_PANEL_PARALLEL bool "Generic parallel interface LCD panel" @@ -1146,40 +1146,40 @@ config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip" select VIDEO_LCD_SSD2828 select VIDEO_LCD_IF_PARALLEL - ---help--- - 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 + help + 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip" select VIDEO_LCD_ANX9804 select VIDEO_LCD_IF_PARALLEL select VIDEO_LCD_PANEL_I2C - ---help--- - Select this for eDP LCD panels with 4 lanes running at 1.62G, - connected via an ANX9804 bridge chip. + help + Select this for eDP LCD panels with 4 lanes running at 1.62G, + connected via an ANX9804 bridge chip. config VIDEO_LCD_PANEL_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LCD panel" select VIDEO_LCD_HITACHI_TX18D42VM select VIDEO_LCD_IF_LVDS - ---help--- - 7.85" 1024x768 Hitachi tx18d42vm LCD panel support + help + 7.85" 1024x768 Hitachi tx18d42vm LCD panel support config VIDEO_LCD_TL059WV5C0 bool "tl059wv5c0 LCD panel" select VIDEO_LCD_PANEL_I2C select VIDEO_LCD_IF_PARALLEL - ---help--- - 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and - Aigo M60/M608/M606 tablets. + help + 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and + Aigo M60/M608/M606 tablets. endchoice config GMAC_TX_DELAY int "GMAC Transmit Clock Delay Chain" default 0 - ---help--- - Set the GMAC Transmit Clock Delay Chain value. + help + Set the GMAC Transmit Clock Delay Chain value. config SPL_STACK_R_ADDR default 0x81e00000 if MACH_SUNIV diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig index c570fb3294d..d2fa72f4724 100644 --- a/arch/arm/mach-uniphier/Kconfig +++ b/arch/arm/mach-uniphier/Kconfig @@ -4,7 +4,7 @@ config SYS_CONFIG_NAME default "uniphier" choice - prompt "UniPhier SoC select" + prompt "UniPhier SoC select" config ARCH_UNIPHIER_V7_MULTI bool "UniPhier V7 SoCs" diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c index 78ead1f45f6..7df7c49ac71 100644 --- a/arch/arm/mach-versal-net/cpu.c +++ b/arch/arm/mach-versal-net/cpu.c @@ -7,6 +7,10 @@ */ #include <init.h> +#include <log.h> +#include <malloc.h> +#include <time.h> +#include <vsprintf.h> #include <asm/armv8/mmu.h> #include <asm/cache.h> #include <asm/global_data.h> @@ -15,6 +19,9 @@ #include <asm/arch/sys_proto.h> #include <asm/cache.h> #include <dm/platdata.h> +#include <linux/bitfield.h> +#include <linux/string.h> +#include "../../../board/xilinx/common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -88,6 +95,148 @@ u64 get_page_table_size(void) return 0x14000; } +void versal_net_timer_setup(void) +{ + u32 val; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); +} + +u32 versal_net_bootmode_reg(void) +{ + return readl(&crp_base->boot_mode_usr); +} + +u8 __weak versal_net_get_bootmode(void) +{ + u32 reg = versal_net_bootmode_reg(); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + return reg & BOOT_MODES_MASK; +} + +static u32 platform_id, platform_version; + +char *soc_name_decode(void) +{ + char *name, *platform_name; + + switch (platform_id) { + case VERSAL_NET_SPP: + platform_name = "ipp"; + break; + case VERSAL_NET_EMU: + platform_name = "emu"; + break; + case VERSAL_NET_QEMU: + platform_name = "qemu"; + break; + default: + return NULL; + } + + /* + * --rev. are 6 chars + * max platform name is qemu which is 4 chars + * platform version number are 1+1 + * Plus 1 char for \n + */ + name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); + if (!name) + return NULL; + + sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD, + platform_name, platform_version / 10, + platform_version % 10); + + return name; +} + +bool soc_detection(void) +{ + u32 version, ps_version; + + version = readl(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + ps_version = FIELD_GET(PS_VERSION_MASK, version); + + debug("idcode %x, version %x, usercode %x\n", + readl(PMC_TAP_IDCODE), version, + readl(PMC_TAP_USERCODE)); + + debug("pmc_ver %lx, ps version %x, rtl version %lx\n", + FIELD_GET(PMC_VERSION_MASK, version), + ps_version, + FIELD_GET(RTL_VERSION_MASK, version)); + + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + if (platform_id == VERSAL_NET_SPP || + platform_id == VERSAL_NET_EMU) { + if (ps_version == PS_VERSION_PRODUCTION) { + /* + * ES1 version ends at 1.9 version where there was +9 + * used because of IPP/SPP conversion. Production + * version have platform_version started from 0 again + * that's why adding +20 to continue with the same line. + * It means the last ES1 version ends at 1.9 version and + * new PRODUCTION line starts at 2.0. + */ + platform_version += 20; + } else { + /* + * 9 is diff for + * 0 means 0.9 version + * 1 means 1.0 version + * 2 means 1.1 version + * etc, + */ + platform_version += 9; + } + } + + debug("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10, platform_version % 10); + + return true; +} + U_BOOT_DRVINFO(soc_xilinx_versal_net) = { .name = "soc_xilinx_versal_net", }; diff --git a/arch/arm/mach-versal-net/include/mach/sys_proto.h b/arch/arm/mach-versal-net/include/mach/sys_proto.h index 23374d10a6b..4907dae1108 100644 --- a/arch/arm/mach-versal-net/include/mach/sys_proto.h +++ b/arch/arm/mach-versal-net/include/mach/sys_proto.h @@ -7,3 +7,9 @@ #include <linux/build_bug.h> void mem_map_fill(void); +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void versal_net_timer_setup(void); +/* Overridable bootmode decode: weak MMIO default, firmware override */ +u8 versal_net_get_bootmode(void); +/* Direct MMIO read of the bootmode register (EL3 / no-firmware path) */ +u32 versal_net_bootmode_reg(void); diff --git a/arch/arm/mach-versal/cpu.c b/arch/arm/mach-versal/cpu.c index 0dd5cc153c4..7521d45bc1a 100644 --- a/arch/arm/mach-versal/cpu.c +++ b/arch/arm/mach-versal/cpu.c @@ -1,10 +1,14 @@ // SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 - 2018 Xilinx, Inc. + * (C) Copyright 2026, Advanced Micro Devices, Inc. + * * Michal Simek <[email protected]> */ #include <init.h> +#include <log.h> +#include <time.h> #include <asm/armv8/mmu.h> #include <asm/cache.h> #include <asm/global_data.h> @@ -16,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; -#define VERSAL_MEM_MAP_USED 5 +#define VERSAL_MEM_MAP_USED 3 #define DRAM_BANKS CONFIG_NR_DRAM_BANKS @@ -44,26 +48,13 @@ static struct mm_region versal_mem_map[VERSAL_MEM_MAP_MAX] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { + }, { /* FPD_AXI_PL_high */ .virt = 0x400000000UL, .phys = 0x400000000UL, .size = 0x200000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x600000000UL, - .phys = 0x600000000UL, - .size = 0x800000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe00000000UL, - .phys = 0xe00000000UL, - .size = 0xf200000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN } }; @@ -121,6 +112,72 @@ int arm_reserve_mmu(void) } #endif +u32 versal_multi_boot_reg(void) +{ + return readl(PMC_MULTI_BOOT_REG) & PMC_MULTI_BOOT_MASK; +} + +u32 __weak versal_pmc_multi_boot(void) +{ + return versal_multi_boot_reg(); +} + +void versal_timer_setup(void) +{ + u32 val; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); +} + +u32 versal_bootmode_reg(void) +{ + return readl(&crp_base->boot_mode_usr); +} + +u8 __weak versal_get_bootmode(void) +{ + u32 reg = versal_bootmode_reg(); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + return reg & BOOT_MODES_MASK; +} + U_BOOT_DRVINFO(soc_xilinx_versal) = { .name = "soc_xilinx_versal", }; diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index a6dfa556966..cb373e6fad9 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -3,6 +3,9 @@ * Copyright 2016 - 2018 Xilinx, Inc. */ +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + #include <linux/build_bug.h> enum tcm_mode { @@ -13,3 +16,16 @@ enum tcm_mode { void initialize_tcm(enum tcm_mode mode); void tcm_init(enum tcm_mode mode); void mem_map_fill(void); + +/* Overridable PMC multiboot accessor: weak MMIO default, firmware override */ +u32 versal_pmc_multi_boot(void); +/* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */ +u32 versal_multi_boot_reg(void); +/* Overridable bootmode decode: weak MMIO default, firmware override */ +u8 versal_get_bootmode(void); +/* Direct MMIO read of the bootmode register (EL3 / no-firmware path) */ +u32 versal_bootmode_reg(void); +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void versal_timer_setup(void); + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c index f65c231bdab..6cc6592b0fc 100644 --- a/arch/arm/mach-versal2/cpu.c +++ b/arch/arm/mach-versal2/cpu.c @@ -7,21 +7,29 @@ */ #include <init.h> +#include <log.h> +#include <malloc.h> +#include <time.h> +#include <vsprintf.h> #include <asm/armv8/mmu.h> #include <asm/cache.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/system.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/cache.h> #include <dm/platdata.h> +#include <linux/bitfield.h> +#include <linux/string.h> +#include "../../../board/xilinx/common/board.h" DECLARE_GLOBAL_DATA_PTR; #if CONFIG_IS_ENABLED(PCIE_DW_AMD) -#define VERSAL2_MEM_MAP_USED 6 +#define VERSAL2_MEM_MAP_USED 4 #else -#define VERSAL2_MEM_MAP_USED 5 +#define VERSAL2_MEM_MAP_USED 3 #endif #define DRAM_BANKS CONFIG_NR_DRAM_BANKS @@ -51,19 +59,6 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x600000000UL, - .phys = 0x600000000UL, - .size = 0x800000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xe00000000UL, - .phys = 0xe00000000UL, - .size = 0xf200000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN #if CONFIG_IS_ENABLED(PCIE_DW_AMD) }, { /* PCIe DBI (1 MB) and config space (255 MB) are contiguous */ @@ -140,6 +135,141 @@ u64 get_page_table_size(void) } #endif +u32 versal2_multi_boot_reg(void) +{ + return readl(PMC_MULTI_BOOT_REG) & PMC_MULTI_BOOT_MASK; +} + +u32 __weak versal2_pmc_multi_boot(void) +{ + return versal2_multi_boot_reg(); +} + +u8 __weak versal2_get_bootmode(void) +{ + u8 bootmode; + u32 reg; + + reg = readl(&crp_base->boot_mode_usr); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + bootmode = reg & BOOT_MODES_MASK; + + return bootmode; +} + +void versal2_timer_setup(void) +{ + u32 val; + + debug("iou_switch ctrl div0 %x\n", + readl(&crlapb_base->iou_switch_ctrl)); + + writel(IOU_SWITCH_CTRL_CLKACT_BIT | + (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), + &crlapb_base->iou_switch_ctrl); + + /* Global timer init - Program time stamp reference clk */ + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; + writel(val, &crlapb_base->timestamp_ref_ctrl); + + debug("ref ctrl 0x%x\n", + readl(&crlapb_base->timestamp_ref_ctrl)); + + /* Clear reset of timestamp reg */ + writel(0, &crlapb_base->rst_timestamp); + + /* + * Program freq register in System counter and + * enable system counter. + */ + writel(CONFIG_COUNTER_FREQUENCY, + &iou_scntr_secure->base_frequency_id_register); + + debug("counter val 0x%x\n", + readl(&iou_scntr_secure->base_frequency_id_register)); + + writel(IOU_SCNTRS_CONTROL_EN, + &iou_scntr_secure->counter_control_register); + + debug("scntrs control 0x%x\n", + readl(&iou_scntr_secure->counter_control_register)); + debug("timer 0x%llx\n", get_ticks()); + debug("timer 0x%llx\n", get_ticks()); +} + +static u32 platform_id, platform_version; + +char *soc_name_decode(void) +{ + char *name, *platform_name; + + switch (platform_id) { + case VERSAL2_SPP: + platform_name = "spp"; + break; + case VERSAL2_EMU: + platform_name = "emu"; + break; + case VERSAL2_SPP_MMD: + platform_name = "spp-mmd"; + break; + case VERSAL2_EMU_MMD: + platform_name = "emu-mmd"; + break; + case VERSAL2_QEMU: + platform_name = "qemu"; + break; + default: + return NULL; + } + + /* + * --rev.-el are 9 chars + * max platform name is emu-mmd which is 7 chars + * platform version number are 1+1 + * el is 1 char + * Plus 1 char for NULL byte + */ + name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20); + if (!name) + return NULL; + + sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD, + platform_name, platform_version / 10, + platform_version % 10, current_el()); + + return name; +} + +bool soc_detection(void) +{ + u32 version, ps_version; + + version = readl(PMC_TAP_VERSION); + platform_id = FIELD_GET(PLATFORM_MASK, version); + ps_version = FIELD_GET(PS_VERSION_MASK, version); + + debug("idcode %x, version %x, usercode %x\n", + readl(PMC_TAP_IDCODE), version, + readl(PMC_TAP_USERCODE)); + + debug("pmc_ver %lx, ps version %x, rtl version %lx\n", + FIELD_GET(PMC_VERSION_MASK, version), + ps_version, + FIELD_GET(RTL_VERSION_MASK, version)); + + platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); + + debug("Platform id: %d version: %d.%d\n", platform_id, + platform_version / 10, platform_version % 10); + + return true; +} + U_BOOT_DRVINFO(soc_amd_versal2) = { .name = "soc_amd_versal2", }; diff --git a/arch/arm/mach-versal2/include/mach/sys_proto.h b/arch/arm/mach-versal2/include/mach/sys_proto.h index cee13488620..b8d12d1dd3b 100644 --- a/arch/arm/mach-versal2/include/mach/sys_proto.h +++ b/arch/arm/mach-versal2/include/mach/sys_proto.h @@ -4,8 +4,22 @@ * Copyright (C) 2022 - 2024, Advanced Micro Devices, Inc. */ +#ifndef _ASM_ARCH_SYS_PROTO_H +#define _ASM_ARCH_SYS_PROTO_H + #include <linux/build_bug.h> #include <asm/armv8/mmu.h> void mem_map_fill(struct mm_region *bank_info, u32 num_banks); void fill_bd_mem_info(void); + +/* Overridable PMC multiboot accessor: weak MMIO default, firmware override */ +u32 versal2_pmc_multi_boot(void); +/* Direct MMIO read of the multiboot register (EL3 / no-firmware path) */ +u32 versal2_multi_boot_reg(void); +/* Weak bootmode decode (MMIO default); a firmware/SCMI build may override */ +u8 versal2_get_bootmode(void); +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void versal2_timer_setup(void); + +#endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-zynqmp/cpu.c b/arch/arm/mach-zynqmp/cpu.c index 3dc47e5d48e..088cc962189 100644 --- a/arch/arm/mach-zynqmp/cpu.c +++ b/arch/arm/mach-zynqmp/cpu.c @@ -8,6 +8,7 @@ #include <time.h> #include <linux/errno.h> #include <linux/types.h> +#include <asm/arch/clk.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/armv8/mmu.h> @@ -171,15 +172,19 @@ unsigned int zynqmp_get_silicon_version(void) return ZYNQMP_CSU_VERSION_SILICON; } -static int zynqmp_mmio_rawwrite(const u32 address, - const u32 mask, - const u32 value) +int zynqmp_mmio_rawread(const u32 address, u32 *value) +{ + *value = readl((ulong)address); + return 0; +} + +int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value) { u32 data; u32 value_local = value; int ret; - ret = zynqmp_mmio_read(address, &data); + ret = zynqmp_mmio_rawread(address, &data); if (ret) return ret; @@ -190,48 +195,44 @@ static int zynqmp_mmio_rawwrite(const u32 address, return 0; } -static int zynqmp_mmio_rawread(const u32 address, u32 *value) +int __weak zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) { - *value = readl((ulong)address); - return 0; + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) + return zynqmp_mmio_rawwrite(address, mask, value); + + return -EINVAL; } -int zynqmp_mmio_write(const u32 address, - const u32 mask, - const u32 value) +int __weak zynqmp_mmio_read(const u32 address, u32 *value) { + if (!value) + return -EINVAL; + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) - return zynqmp_mmio_rawwrite(address, mask, value); -#if defined(CONFIG_ZYNQMP_FIRMWARE) - else - return xilinx_pm_request(PM_MMIO_WRITE, address, mask, - value, 0, 0, 0, NULL); -#endif + return zynqmp_mmio_rawread(address, value); return -EINVAL; } -int zynqmp_mmio_read(const u32 address, u32 *value) +void zynqmp_timer_setup(void) { - u32 ret = -EINVAL; + u32 val; - if (!value) - return ret; + val = readl(&crlapb_base->timestamp_ref_ctrl); + val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) { - ret = zynqmp_mmio_rawread(address, value); - } -#if defined(CONFIG_ZYNQMP_FIRMWARE) - else { - u32 ret_payload[PAYLOAD_ARG_CNT]; + if (!val) { + val = readl(&crlapb_base->timestamp_ref_ctrl); + val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; + writel(val, &crlapb_base->timestamp_ref_ctrl); - ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0, - 0, 0, 0, ret_payload); - *value = ret_payload[1]; + /* Program freq register in System counter */ + writel(zynqmp_get_system_timer_freq(), + &iou_scntr_secure->base_frequency_id_register); + /* And enable system counter */ + writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, + &iou_scntr_secure->counter_control_register); } -#endif - - return ret; } U_BOOT_DRVINFO(soc_xilinx_zynqmp) = { diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h index b6a41df1da4..d2bb10ffcbb 100644 --- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h +++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h @@ -54,5 +54,10 @@ void mem_map_fill(void); #if defined(CONFIG_DEFINE_TCM_OCM_MMAP) void tcm_init(enum tcm_mode mode); #endif +/* EL3 clock/timer register setup, called from board_early_init_r() */ +void zynqmp_timer_setup(void); +/* Direct MMIO accessors (EL3/SPL or no-firmware path) */ +int zynqmp_mmio_rawread(const u32 address, u32 *value); +int zynqmp_mmio_rawwrite(const u32 address, const u32 mask, const u32 value); #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 8bebf0ea3e1..61a1845c2ee 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -11,56 +11,56 @@ config STATIC_RELA config MCF520x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF52x2 select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF523x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF530x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF5301x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF532x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF537x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE bool config MCF5441x select OF_CONTROL select DM - select DM_SERIAL + select DM_SERIAL select ARCH_COLDFIRE select CREATE_ARCH_SYMLINK bool @@ -191,9 +191,9 @@ config TARGET_AMCORE select M5307 config TARGET_STMARK2 - bool "Support stmark2" - select CF_DSPI - select M54418 + bool "Support stmark2" + select CF_DSPI + select M54418 config TARGET_QEMU_M68K bool "Support QEMU m68k virt" diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 36612756294..75913d4f1ae 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -267,8 +267,8 @@ config CPU_MIPS64_OCTEON select 64BIT select SPL_64BIT if SPL help - Choose this option for Marvell Octeon CPUs. These CPUs are between - MIPS64 R5 and R6 with other extensions. + Choose this option for Marvell Octeon CPUs. These CPUs are between + MIPS64 R5 and R6 with other extensions. endchoice @@ -351,7 +351,7 @@ config MIPS_RELOCATION_TABLE_SIZE range 0x100 0x10000 default "0xc000" if TARGET_MALTA default "0x8000" - ---help--- + help A table of relocation data will be appended to the U-Boot binary and parsed in relocate_code() to fix up all offsets in the relocated U-Boot. @@ -526,7 +526,7 @@ config MIPS_SRAM_INIT config DMA_ADDR_T_64BIT bool help - Select this to enable 64-bit DMA addressing + Select this to enable 64-bit DMA addressing config SYS_DCACHE_SIZE int diff --git a/arch/mips/mach-octeon/Kconfig b/arch/mips/mach-octeon/Kconfig index 6105cdcf96e..cd1e377c79d 100644 --- a/arch/mips/mach-octeon/Kconfig +++ b/arch/mips/mach-octeon/Kconfig @@ -25,8 +25,8 @@ choice config SOC_OCTEON3 bool "Octeon III family" help - This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx - and CNF75XX. + This selects the Octeon III SoC family CN70xx, CN73XX, CN78xx + and CNF75XX. endchoice @@ -38,14 +38,14 @@ config TARGET_OCTEON_EBB7304 bool "Marvell Octeon EBB7304" select OCTEON_CN73XX help - Choose this for the Octeon EBB7304 board + Choose this for the Octeon EBB7304 board config TARGET_OCTEON_NIC23 bool "Marvell Octeon NIC23" select ARCH_MISC_INIT select OCTEON_CN73XX help - Choose this for the Octeon NIC23 board + Choose this for the Octeon NIC23 board endchoice diff --git a/arch/powerpc/config.mk b/arch/powerpc/config.mk index 6e30df6504e..32e86d84a12 100644 --- a/arch/powerpc/config.mk +++ b/arch/powerpc/config.mk @@ -32,7 +32,7 @@ archprepare: checkgcc4 # GCC 3.x is reported to have problems generating the type of relocation # that U-Boot wants. -# See http://lists.denx.de/pipermail/u-boot/2012-September/135156.html +# See https://patch.msgid.link/1348500648.2514.2.camel@petert/ checkgcc4: @if test "$(call cc-name)" = "gcc" -a \ $(call cc-version) -lt 0400; then \ diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index cb564b32c07..32a140b0913 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -966,14 +966,14 @@ config E500 bool default y help - Enable PowerPC E500 cores, including e500v1, e500v2, e500mc + Enable PowerPC E500 cores, including e500v1, e500v2, e500mc config E500MC bool select BTB imply CMD_PCI help - Enble PowerPC E500MC core + Enable PowerPC E500MC core config E5500 bool @@ -982,7 +982,7 @@ config E6500 bool select BTB help - Enable PowerPC E6500 core + Enable PowerPC E6500 core config NOBQFMAN bool @@ -990,7 +990,7 @@ config NOBQFMAN config FSL_LAW bool help - Use Freescale common code for Local Access Window + Use Freescale common code for Local Access Window config HETROGENOUS_CLUSTERS bool @@ -1054,10 +1054,10 @@ config SYS_CCSRBAR_DEFAULT ARCH_T4240 default 0xe0000000 if ARCH_QEMU_E500 help - Default value of CCSRBAR comes from power-on-reset. It - is fixed on each SoC. Some SoCs can have different value - if changed by pre-boot regime. The value here must match - the current value in SoC. If not sure, do not change. + Default value of CCSRBAR comes from power-on-reset. It + is fixed on each SoC. Some SoCs can have different value + if changed by pre-boot regime. The value here must match + the current value in SoC. If not sure, do not change. config SYS_DPAA_PME bool @@ -1287,8 +1287,8 @@ config SYS_FSL_NUM_LAWS default 8 if ARCH_MPC8540 || \ ARCH_MPC8560 help - Number of local access windows. This is fixed per SoC. - If not sure, do not change. + Number of local access windows. This is fixed per SoC. + If not sure, do not change. config SYS_FSL_CORES_PER_CLUSTER int @@ -1308,8 +1308,8 @@ config SYS_NUM_TLBCAMS default 64 if E500MC default 16 help - Number of TLB CAM entries for Book-E chips. 64 for E500MC, - 16 for other E500 SoCs. + Number of TLB CAM entries for Book-E chips. 64 for E500MC, + 16 for other E500 SoCs. config L2_CACHE bool "Enable L2 cache support" @@ -1401,12 +1401,12 @@ config SYS_PPC_E500_DEBUG_TLB ARCH_BSC9132 || \ ARCH_C29X help - Select a temporary TLB entry to be used during boot to work - around limitations in e500v1 and e500v2 external debugger - support. This reduces the portions of the boot code where - breakpoints and single stepping do not work. The value of this - symbol should be set to the TLB1 entry to be used for this - purpose. If unsure, do not change. + Select a temporary TLB entry to be used during boot to work + around limitations in e500v1 and e500v2 external debugger + support. This reduces the portions of the boot code where + breakpoints and single stepping do not work. The value of this + symbol should be set to the TLB1 entry to be used for this + purpose. If unsure, do not change. config SYS_FSL_IFC_CLK_DIV int "Divider of platform clock" @@ -1419,8 +1419,8 @@ config SYS_FSL_IFC_CLK_DIV ARCH_T4240 default 1 help - Defines divider of platform clock(clock input to - IFC controller). + Defines divider of platform clock(clock input to + IFC controller). config SYS_FSL_LBC_CLK_DIV int "Divider of platform clock" @@ -1435,8 +1435,8 @@ config SYS_FSL_LBC_CLK_DIV default 1 help - Defines divider of platform clock(clock input to - eLBC controller). + Defines divider of platform clock(clock input to + eLBC controller). config ENABLE_36BIT_PHYS bool "Enable 36bit physical address space support" diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 8f21b78dbe4..ec4d484a669 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -44,9 +44,9 @@ config X86_RUN_64BIT_NO_SPL bool "64-bit" select X86_64 help - Build U-Boot as a 64-bit binary without SPL. As U-Boot enters - in 64-bit mode, the assumption is that the silicon is fully - initialized (MP, page tables, etc.). + Build U-Boot as a 64-bit binary without SPL. As U-Boot enters + in 64-bit mode, the assumption is that the silicon is fully + initialized (MP, page tables, etc.). endchoice @@ -585,11 +585,11 @@ config DCACHE_RAM_MRC_VAR_SIZE not boot. config HAVE_REFCODE - bool "Add a Reference Code binary" - help - Select this option to add a Reference Code binary to the resulting - U-Boot image. This is an Intel binary blob that handles system - initialisation, in this case the PCH and System Agent. + bool "Add a Reference Code binary" + help + Select this option to add a Reference Code binary to the resulting + U-Boot image. This is an Intel binary blob that handles system + initialisation, in this case the PCH and System Agent. Note: Without this binary (on platforms that need it such as broadwell) U-Boot will be missing some critical setup steps. @@ -617,8 +617,8 @@ config SMP_AP_WORK bool depends on SMP help - Allow APs to do other work after initialisation instead of going - to sleep. + Allow APs to do other work after initialisation instead of going + to sleep. config MAX_CPUS int "Maximum number of CPUs permitted" diff --git a/arch/x86/cpu/apollolake/cpu.c b/arch/x86/cpu/apollolake/cpu.c index f480bb1d8c3..d1f592ec57e 100644 --- a/arch/x86/cpu/apollolake/cpu.c +++ b/arch/x86/cpu/apollolake/cpu.c @@ -171,11 +171,9 @@ static int cpu_apl_probe(struct udevice *dev) return 0; } -#ifdef CONFIG_ACPIGEN -struct acpi_ops apl_cpu_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_cpu_acpi_ops = { .fill_ssdt = acpi_cpu_fill_ssdt, }; -#endif static const struct cpu_ops cpu_x86_apl_ops = { .get_desc = cpu_x86_get_desc, diff --git a/arch/x86/cpu/apollolake/hostbridge.c b/arch/x86/cpu/apollolake/hostbridge.c index 284f16cfd91..360d091121c 100644 --- a/arch/x86/cpu/apollolake/hostbridge.c +++ b/arch/x86/cpu/apollolake/hostbridge.c @@ -366,7 +366,7 @@ ulong sa_get_tseg_base(struct udevice *dev) return sa_read_reg(dev, TSEG); } -struct acpi_ops apl_hostbridge_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_hostbridge_acpi_ops = { .get_name = apl_acpi_hb_get_name, #if CONFIG_IS_ENABLED(GENERATE_ACPI_TABLE) .write_tables = apl_acpi_hb_write_tables, diff --git a/arch/x86/cpu/apollolake/lpc.c b/arch/x86/cpu/apollolake/lpc.c index f34c199bf73..008c4dc0037 100644 --- a/arch/x86/cpu/apollolake/lpc.c +++ b/arch/x86/cpu/apollolake/lpc.c @@ -119,7 +119,7 @@ static int apl_acpi_lpc_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "LPCB"); } -struct acpi_ops apl_lpc_acpi_ops = { +static const struct acpi_ops __maybe_unused apl_lpc_acpi_ops = { .get_name = apl_acpi_lpc_get_name, #ifdef CONFIG_GENERATE_ACPI_TABLE .write_tables = intel_southbridge_write_acpi_tables, diff --git a/arch/x86/cpu/intel_common/generic_wifi.c b/arch/x86/cpu/intel_common/generic_wifi.c index 75fa4e01d8a..1a24c10ab0b 100644 --- a/arch/x86/cpu/intel_common/generic_wifi.c +++ b/arch/x86/cpu/intel_common/generic_wifi.c @@ -102,7 +102,7 @@ static int intel_wifi_acpi_fill_ssdt(const struct udevice *dev, return 0; } -struct acpi_ops wifi_acpi_ops = { +static const struct acpi_ops wifi_acpi_ops = { .fill_ssdt = intel_wifi_acpi_fill_ssdt, }; diff --git a/arch/x86/lib/fsp/fsp_graphics.c b/arch/x86/lib/fsp/fsp_graphics.c index ad25020086c..d425e80760b 100644 --- a/arch/x86/lib/fsp/fsp_graphics.c +++ b/arch/x86/lib/fsp/fsp_graphics.c @@ -150,7 +150,7 @@ static int fsp_video_acpi_write_tables(const struct udevice *dev, } #endif -struct acpi_ops fsp_video_acpi_ops = { +static const struct acpi_ops __maybe_unused fsp_video_acpi_ops = { #ifdef CONFIG_INTEL_GMA_ACPI .write_tables = fsp_video_acpi_write_tables, #endif diff --git a/board/alliedtelesis/SBx81LIFKW/Kconfig b/board/alliedtelesis/SBx81LIFKW/Kconfig index 5c2609b7f46..49516b7f007 100644 --- a/board/alliedtelesis/SBx81LIFKW/Kconfig +++ b/board/alliedtelesis/SBx81LIFKW/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "SBx81LIFKW" config SYS_VENDOR - default "alliedtelesis" + default "alliedtelesis" config SYS_CONFIG_NAME default "SBx81LIFKW" diff --git a/board/alliedtelesis/SBx81LIFXCAT/Kconfig b/board/alliedtelesis/SBx81LIFXCAT/Kconfig index 524c2900892..20e02144d3a 100644 --- a/board/alliedtelesis/SBx81LIFXCAT/Kconfig +++ b/board/alliedtelesis/SBx81LIFXCAT/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "SBx81LIFXCAT" config SYS_VENDOR - default "alliedtelesis" + default "alliedtelesis" config SYS_CONFIG_NAME default "SBx81LIFXCAT" diff --git a/board/amd/versal2/board.c b/board/amd/versal2/board.c index ec28e60c410..2afd283b8dd 100644 --- a/board/amd/versal2/board.c +++ b/board/amd/versal2/board.c @@ -29,11 +29,8 @@ #include <dm/device.h> #include <dm/uclass.h> #include <versalpl.h> -#include <zynqmp_firmware.h> #include "../../xilinx/common/board.h" -#include <linux/bitfield.h> -#include <linux/sizes.h> #include <debug_uart.h> #include <generated/dt.h> #include <linux/ioport.h> @@ -62,151 +59,25 @@ int board_init(void) return 0; } -static u32 platform_id, platform_version; - -char *soc_name_decode(void) -{ - char *name, *platform_name; - - switch (platform_id) { - case VERSAL2_SPP: - platform_name = "spp"; - break; - case VERSAL2_EMU: - platform_name = "emu"; - break; - case VERSAL2_SPP_MMD: - platform_name = "spp-mmd"; - break; - case VERSAL2_EMU_MMD: - platform_name = "emu-mmd"; - break; - case VERSAL2_QEMU: - platform_name = "qemu"; - break; - default: - return NULL; - } - - /* - * --rev.-el are 9 chars - * max platform name is emu-mmd which is 7 chars - * platform version number are 1+1 - * el is 1 char - * Plus 1 char for NULL byte - */ - name = calloc(1, strlen(CONFIG_SYS_BOARD) + 20); - if (!name) - return NULL; - - sprintf(name, "%s-%s-rev%d.%d-el%d", CONFIG_SYS_BOARD, - platform_name, platform_version / 10, - platform_version % 10, current_el()); - - return name; -} - -bool soc_detection(void) -{ - u32 version, ps_version; - - version = readl(PMC_TAP_VERSION); - platform_id = FIELD_GET(PLATFORM_MASK, version); - ps_version = FIELD_GET(PS_VERSION_MASK, version); - - debug("idcode %x, version %x, usercode %x\n", - readl(PMC_TAP_IDCODE), version, - readl(PMC_TAP_USERCODE)); - - debug("pmc_ver %lx, ps version %x, rtl version %lx\n", - FIELD_GET(PMC_VERSION_MASK, version), - ps_version, - FIELD_GET(RTL_VERSION_MASK, version)); - - platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); - - debug("Platform id: %d version: %d.%d\n", platform_id, - platform_version / 10, platform_version % 10); - - return true; -} - int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - debug("iou_switch ctrl div0 %x\n", - readl(&crlapb_base->iou_switch_ctrl)); - - writel(IOU_SWITCH_CTRL_CLKACT_BIT | - (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), - &crlapb_base->iou_switch_ctrl); - - /* Global timer init - Program time stamp reference clk */ - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - debug("ref ctrl 0x%x\n", - readl(&crlapb_base->timestamp_ref_ctrl)); - - /* Clear reset of timestamp reg */ - writel(0, &crlapb_base->rst_timestamp); - - /* - * Program freq register in System counter and - * enable system counter. - */ - writel(CONFIG_COUNTER_FREQUENCY, - &iou_scntr_secure->base_frequency_id_register); - - debug("counter val 0x%x\n", - readl(&iou_scntr_secure->base_frequency_id_register)); - - writel(IOU_SCNTRS_CONTROL_EN, - &iou_scntr_secure->counter_control_register); - - debug("scntrs control 0x%x\n", - readl(&iou_scntr_secure->counter_control_register)); - debug("timer 0x%llx\n", get_ticks()); - debug("timer 0x%llx\n", get_ticks()); + versal2_timer_setup(); return 0; } -static u8 versal2_get_bootmode(void) -{ - u8 bootmode; - u32 reg = 0; - - reg = readl(&crp_base->boot_mode_usr); - - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; - - bootmode = reg & BOOT_MODES_MASK; - - return bootmode; -} - static u32 versal2_multi_boot(void) { u8 bootmode = versal2_get_bootmode(); - u32 reg = 0; /* Mostly workaround for QEMU CI pipeline */ if (bootmode == JTAG_MODE) return 0; - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) - reg = zynqmp_pm_get_pmc_multi_boot_reg(); - else - reg = readl(PMC_MULTI_BOOT_REG); - - return reg & PMC_MULTI_BOOT_MASK; + return versal2_pmc_multi_boot(); } static int boot_targets_setup(void) @@ -605,3 +476,31 @@ void set_dfu_alt_info(char *interface, char *devstr) env_set("dfu_alt_info", buf); } #endif + +int spi_get_env_dev(void) +{ + struct udevice *dev; + const char *name; + int bootseq; + + switch (versal2_get_bootmode()) { + case QSPI_MODE_24BIT: + case QSPI_MODE_32BIT: + name = "spi@f1030000"; + break; + case OSPI_MODE: + name = "spi@f1010000"; + break; + default: + return -1; + } + + if (uclass_get_device_by_name(UCLASS_SPI, name, &dev)) { + debug("SPI driver for %s is not present\n", name); + return -1; + } + + bootseq = dev_seq(dev); + debug("bootseq %d\n", bootseq); + return bootseq; +} diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 8cfac9fbb34..4a2349e165b 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -218,7 +218,7 @@ static void set_gpr_register(void) int board_early_init_f(void) { - select_ldb_di_clock_source(MXC_PLL5_CLK); + select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK); set_gpr_register(); /* diff --git a/board/aspeed/evb_ast2700/Kconfig b/board/aspeed/evb_ast2700/Kconfig new file mode 100644 index 00000000000..ede9eb7fb85 --- /dev/null +++ b/board/aspeed/evb_ast2700/Kconfig @@ -0,0 +1,13 @@ +if TARGET_EVB_AST2700 + +config SYS_BOARD + default "evb_ast2700" + +config SYS_VENDOR + default "aspeed" + +config SYS_CONFIG_NAME + string "board configuration name" + default "evb_ast2700" + +endif diff --git a/board/aspeed/evb_ast2700/Makefile b/board/aspeed/evb_ast2700/Makefile new file mode 100644 index 00000000000..0c29700f5a9 --- /dev/null +++ b/board/aspeed/evb_ast2700/Makefile @@ -0,0 +1 @@ +obj-y += evb_ast2700.o diff --git a/board/aspeed/evb_ast2700/evb_ast2700.c b/board/aspeed/evb_ast2700/evb_ast2700.c new file mode 100644 index 00000000000..b34aa6e1682 --- /dev/null +++ b/board/aspeed/evb_ast2700/evb_ast2700.c @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) ASPEED Technology Inc. + */ + diff --git a/board/beagle/beagleboneai64/Kconfig b/board/beagle/beagleboneai64/Kconfig index 0f21582614d..7d7077e9f28 100644 --- a/board/beagle/beagleboneai64/Kconfig +++ b/board/beagle/beagleboneai64/Kconfig @@ -34,7 +34,7 @@ config SYS_BOARD default "beagleboneai64" config SYS_VENDOR - default "beagle" + default "beagle" config SYS_CONFIG_NAME default "beagleboneai64" @@ -49,7 +49,7 @@ config SYS_BOARD default "beagleboneai64" config SYS_VENDOR - default "beagle" + default "beagle" config SYS_CONFIG_NAME default "beagleboneai64" diff --git a/board/beagle/beagleplay/Kconfig b/board/beagle/beagleplay/Kconfig index 592b53e493c..fcc6a5aa496 100644 --- a/board/beagle/beagleplay/Kconfig +++ b/board/beagle/beagleplay/Kconfig @@ -30,13 +30,13 @@ endchoice if TARGET_AM625_A53_BEAGLEPLAY config SYS_BOARD - default "beagleplay" + default "beagleplay" config SYS_VENDOR - default "beagle" + default "beagle" config SYS_CONFIG_NAME - default "beagleplay" + default "beagleplay" source "board/ti/common/Kconfig" @@ -45,13 +45,13 @@ endif if TARGET_AM625_R5_BEAGLEPLAY config SYS_BOARD - default "beagleplay" + default "beagleplay" config SYS_VENDOR - default "beagle" + default "beagle" config SYS_CONFIG_NAME - default "beagleplay" + default "beagleplay" config SPL_LDSCRIPT default "arch/arm/mach-omap2/u-boot-spl.lds" diff --git a/board/beagle/beagley-ai/Kconfig b/board/beagle/beagley-ai/Kconfig index bf953982151..07aedc2ea3f 100644 --- a/board/beagle/beagley-ai/Kconfig +++ b/board/beagle/beagley-ai/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "beagley-ai" config SYS_VENDOR - default "beagle" + default "beagle" config SYS_CONFIG_NAME default "beagley_ai" diff --git a/board/boundary/nitrogen6x/README b/board/boundary/nitrogen6x/README index 0b59289e7f0..114f81f1d1a 100644 --- a/board/boundary/nitrogen6x/README +++ b/board/boundary/nitrogen6x/README @@ -17,7 +17,7 @@ and saving the environment to SPI NOR. It does not support 'boot from SD' at offset 0x400 except through the 'bmode' command. - http://lists.denx.de/pipermail/u-boot/2012-August/131151.html + https://patch.msgid.link/[email protected]/ 2. Boots using 6x_bootscript on SATA or SD card ----------------------------------------------- diff --git a/board/cortina/common/Kconfig b/board/cortina/common/Kconfig index 00c709e70f0..bf5229abd75 100644 --- a/board/cortina/common/Kconfig +++ b/board/cortina/common/Kconfig @@ -1,6 +1,6 @@ config CORTINA_PLATFORM - bool "Cortina-Access Platform" - default y - help - Select this option for Cortina-Access platforms - to enables selection of CAxxxx drivers + bool "Cortina-Access Platform" + default y + help + Select this option for Cortina-Access platforms + to enables selection of CAxxxx drivers diff --git a/board/cortina/presidio-asic/Kconfig b/board/cortina/presidio-asic/Kconfig index 8e6f6cfa27c..7bf8b78742a 100644 --- a/board/cortina/presidio-asic/Kconfig +++ b/board/cortina/presidio-asic/Kconfig @@ -1,7 +1,7 @@ if TARGET_PRESIDIO_ASIC config BIT64 bool - default y + default y select SOC_CA7774 diff --git a/board/firefly/roc-pc-rk3399/Kconfig b/board/firefly/roc-pc-rk3399/Kconfig index c211e9d3c79..b800f7d2102 100644 --- a/board/firefly/roc-pc-rk3399/Kconfig +++ b/board/firefly/roc-pc-rk3399/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "roc-pc-rk3399" config SYS_VENDOR - default "firefly" + default "firefly" config SYS_CONFIG_NAME default "roc-pc-rk3399" diff --git a/board/ge/b1x5v2/b1x5v2.c b/board/ge/b1x5v2/b1x5v2.c index ddb7304d493..f7751fd6fb1 100644 --- a/board/ge/b1x5v2/b1x5v2.c +++ b/board/ge/b1x5v2/b1x5v2.c @@ -320,7 +320,7 @@ int overwrite_console(void) int board_early_init_f(void) { - select_ldb_di_clock_source(MXC_PLL5_CLK); + select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK); return 0; } diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index e1d08475e94..9fc5f604a49 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -383,7 +383,7 @@ int board_early_init_f(void) #if defined(CONFIG_VIDEO_IPUV3) /* Set LDB clock to Video PLL */ - select_ldb_di_clock_source(MXC_PLL5_CLK); + select_ldb_di_clock_source(MXC_PLL5_CLK, MXC_PLL5_CLK); #endif return 0; } diff --git a/board/google/chromebook_coral/coral.c b/board/google/chromebook_coral/coral.c index b4053fa097d..2bb54d59bb8 100644 --- a/board/google/chromebook_coral/coral.c +++ b/board/google/chromebook_coral/coral.c @@ -293,7 +293,7 @@ static int coral_write_acpi_tables(const struct udevice *dev, return 0; } -struct acpi_ops coral_acpi_ops = { +static const struct acpi_ops __maybe_unused coral_acpi_ops = { .write_tables = coral_write_acpi_tables, .inject_dsdt = chromeos_acpi_gpio_generate, }; diff --git a/board/imgtec/boston/Kconfig b/board/imgtec/boston/Kconfig index 965847d9650..d7d8bfd0a76 100644 --- a/board/imgtec/boston/Kconfig +++ b/board/imgtec/boston/Kconfig @@ -11,7 +11,7 @@ config SYS_CONFIG_NAME config ENV_SOURCE_FILE - default "boston" + default "boston" config TEXT_BASE default 0x9fc00000 if 32BIT diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig index f5e2f58b12b..dfc196124f3 100644 --- a/board/logicpd/imx6/Kconfig +++ b/board/logicpd/imx6/Kconfig @@ -4,7 +4,7 @@ config SYS_BOARD default "imx6" config SYS_VENDOR - default "logicpd" + default "logicpd" config SYS_CONFIG_NAME default "imx6_logic" diff --git a/board/mediatek/mt7987/MAINTAINERS b/board/mediatek/mt7987/MAINTAINERS index c257d0b09df..b245174b0f7 100644 --- a/board/mediatek/mt7987/MAINTAINERS +++ b/board/mediatek/mt7987/MAINTAINERS @@ -2,7 +2,6 @@ MT7987 M: Sam Shih <[email protected]> S: Maintained F: board/mediatek/mt7987 -F: include/configs/mt7987.h F: configs/mt7987_rfb_defconfig F: configs/mt7987_emmc_rfb_defconfig F: configs/mt7987_sd_rfb_defconfig diff --git a/board/mediatek/mt7988/MAINTAINERS b/board/mediatek/mt7988/MAINTAINERS index a45bfff26ca..c7e30342e5c 100644 --- a/board/mediatek/mt7988/MAINTAINERS +++ b/board/mediatek/mt7988/MAINTAINERS @@ -2,6 +2,5 @@ MT7988 M: Sam Shih <[email protected]> S: Maintained F: board/mediatek/mt7988 -F: include/configs/mt7988.h F: configs/mt7988_rfb_defconfig F: configs/mt7988_sd_rfb_defconfig diff --git a/board/nxp/imx8mm_evk/imx8mm_evk.env b/board/nxp/imx8mm_evk/imx8mm_evk.env index d59bd6fd5ed..88eefaa35e5 100644 --- a/board/nxp/imx8mm_evk/imx8mm_evk.env +++ b/board/nxp/imx8mm_evk/imx8mm_evk.env @@ -12,6 +12,8 @@ initrd_addr=0x48080000 image=Image ip_dyn=yes kernel_addr_r=0x42000000 +kernel_comp_addr_r=0x60000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mn_evk/imx8mn_evk.env b/board/nxp/imx8mn_evk/imx8mn_evk.env index cffa83bf792..fbdf202c573 100644 --- a/board/nxp/imx8mn_evk/imx8mn_evk.env +++ b/board/nxp/imx8mn_evk/imx8mn_evk.env @@ -12,6 +12,8 @@ initrd_addr=0x48080000 image=Image ip_dyn=yes kernel_addr_r=0x42000000 +kernel_comp_addr_r=0x60000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.env b/board/nxp/imx8mp_evk/imx8mp_evk.env index e994b93b168..dfc922e6215 100644 --- a/board/nxp/imx8mp_evk/imx8mp_evk.env +++ b/board/nxp/imx8mp_evk/imx8mp_evk.env @@ -10,6 +10,8 @@ fdt_addr=0x43000000 fdtfile=DEFAULT_FDT_FILE image=Image ip_dyn=yes +kernel_comp_addr_r=0x80000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw diff --git a/board/nxp/imx8mq_evk/imx8mq_evk.env b/board/nxp/imx8mq_evk/imx8mq_evk.env index 6575dd7cb07..dd674afac91 100644 --- a/board/nxp/imx8mq_evk/imx8mq_evk.env +++ b/board/nxp/imx8mq_evk/imx8mq_evk.env @@ -10,6 +10,8 @@ initrd_addr=0x43800000 image=Image ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x80000000 +kernel_comp_size=0x2000000 loadaddr=CONFIG_SYS_LOAD_ADDR mmcautodetect=yes mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX diff --git a/board/nxp/imx93_evk/imx93_evk.env b/board/nxp/imx93_evk/imx93_evk.env index b2ed1901a2b..76fadc00eeb 100644 --- a/board/nxp/imx93_evk/imx93_evk.env +++ b/board/nxp/imx93_evk/imx93_evk.env @@ -10,13 +10,16 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw mmcautodetect=yes mmcargs=setenv bootargs ${jh_clk} ${mcore_clk} console=${console} root=${mmcroot} prepare_mcore=setenv mcore_clk clk-imx93.mcore_booted -kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file} diff --git a/board/nxp/imx93_frdm/Makefile b/board/nxp/imx93_frdm/Makefile index 9612b1fa55b..751ebfc9458 100644 --- a/board/nxp/imx93_frdm/Makefile +++ b/board/nxp/imx93_frdm/Makefile @@ -7,5 +7,5 @@ obj-y += imx93_frdm.o ifdef CONFIG_XPL_BUILD -obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_2gb_timing.o +obj-y += spl.o lpddr4x_1gb_timing.o lpddr4x_1cs_2gb_timing.o lpddr4x_2cs_2gb_timing.o endif diff --git a/board/nxp/imx93_frdm/imx93_frdm.env b/board/nxp/imx93_frdm/imx93_frdm.env index 9af3bdfd714..96096bc51a0 100644 --- a/board/nxp/imx93_frdm/imx93_frdm.env +++ b/board/nxp/imx93_frdm/imx93_frdm.env @@ -10,12 +10,15 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=1 mmcpart=1 mmcroot=/dev/mmcblk${mmcdev}p2 rootwait rw mmcautodetect=yes mmcargs=setenv bootargs console=${console} root=${mmcroot} -kernel_addr_r=CONFIG_SYS_LOAD_ADDR loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile} boot_os=booti ${loadaddr} - ${fdt_addr_r} diff --git a/board/nxp/imx93_frdm/lpddr4_timing.h b/board/nxp/imx93_frdm/lpddr4_timing.h index 192bc9e1519..3ff50d8519b 100644 --- a/board/nxp/imx93_frdm/lpddr4_timing.h +++ b/board/nxp/imx93_frdm/lpddr4_timing.h @@ -7,6 +7,7 @@ #define __LPDDR4_TIMING_H__ extern struct dram_timing_info dram_timing_1GB; -extern struct dram_timing_info dram_timing_2GB; +extern struct dram_timing_info dram_timing_1CS_2GB; +extern struct dram_timing_info dram_timing_2CS_2GB; #endif /* __LPDDR4_TIMING_H__ */ diff --git a/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_1cs_2gb_timing.c index cd129e12959..5439a039c3d 100644 --- a/board/nxp/imx93_frdm/lpddr4x_2gb_timing.c +++ b/board/nxp/imx93_frdm/lpddr4x_1cs_2gb_timing.c @@ -1978,7 +1978,7 @@ static struct dram_fsp_msg ddr_dram_fsp_msg[] = { }; /* ddr timing config params */ -struct dram_timing_info dram_timing_2GB = { +struct dram_timing_info dram_timing_1CS_2GB = { .ddrc_cfg = ddr_ddrc_cfg, .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), .ddrphy_cfg = ddr_ddrphy_cfg, diff --git a/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c b/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c new file mode 100644 index 00000000000..79539941412 --- /dev/null +++ b/board/nxp/imx93_frdm/lpddr4x_2cs_2gb_timing.c @@ -0,0 +1,2006 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2025 NXP + * + * Generated code from DDR Gear + * + */ + +#include <linux/kernel.h> +#include <asm/arch/ddr.h> + +static struct dram_cfg_param ddr_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { 0x4e300110, 0x44104001 }, + { 0x4e301000, 0x0 }, + { 0x4e300000, 0x8000ff }, + { 0x4e300008, 0x0 }, + { 0x4e300080, 0x80000412 }, + { 0x4e300084, 0x80000412 }, + { 0x4e300114, 0x1002 }, + { 0x4e300260, 0x80 }, + { 0x4e30017c, 0x0 }, + { 0x4e300f04, 0x80 }, + { 0x4e300800, 0x43b30002 }, + { 0x4e300804, 0x1f1f1f1f }, + { 0x4e301240, 0x0 }, + { 0x4e301244, 0x0 }, + { 0x4e301248, 0x0 }, + { 0x4e30124c, 0x0 }, + { 0x4e301250, 0x0 }, + { 0x4e301254, 0x0 }, + { 0x4e301258, 0x0 }, + { 0x4e30125c, 0x0 }, +}; + +/* dram fsp cfg */ +static struct dram_fsp_cfg ddr_dram_fsp_cfg[] = { + { + { + { 0x4e300100, 0x24a0321b }, + { 0x4e300104, 0xfaee001b }, + { 0x4e300108, 0x2f2e3233 }, + { 0x4e30010c, 0x5c18b }, + { 0x4e300124, 0x1c790000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x35f00000 }, + { 0x4e300170, 0x8b0b0608 }, + { 0x4e300250, 0x28 }, + { 0x4e300254, 0xfe00fe }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + { 0x4e300300, 0x224f2213 }, + { 0x4e300304, 0xfe2213 }, + { 0x4e300308, 0xa380e3c }, + }, + { + { 0x01, 0xe4 }, + { 0x02, 0x36 }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 0, + }, + { + { + { 0x4e300100, 0x124f2100 }, + { 0x4e300104, 0xf877000e }, + { 0x4e300108, 0x1816e4aa }, + { 0x4e30010c, 0x5101e6 }, + { 0x4e300124, 0xe3c0000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x30900000 }, + { 0x4e300170, 0x8a0a0508 }, + { 0x4e300250, 0x14 }, + { 0x4e300254, 0x7b007b }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + }, + { + { 0x01, 0xb4 }, + { 0x02, 0x1b }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 0, + }, + { + { + { 0x4e300100, 0x51000 }, + { 0x4e300104, 0xf855000a }, + { 0x4e300108, 0x6e620a48 }, + { 0x4e30010c, 0x31010d }, + { 0x4e300124, 0x4c50000 }, + { 0x4e300160, 0x9102 }, + { 0x4e30016c, 0x30000000 }, + { 0x4e300170, 0x89090408 }, + { 0x4e300250, 0x7 }, + { 0x4e300254, 0x240024 }, + { 0x4e300258, 0x8 }, + { 0x4e30025c, 0x400 }, + }, + { + { 0x01, 0x94 }, + { 0x02, 0x09 }, + { 0x03, 0x32 }, + { 0x0b, 0x26 }, + { 0x0c, 0x11 }, + { 0x0e, 0x11 }, + { 0x16, 0x04 }, + }, + 1, + }, +}; + +/* Auto Generated by SNPS PHY Init code + * which inlcude PHYINIT, 1D/2D message block + * rerention CSR, PIE + */ +static struct dram_cfg_param ddr_ddrphy_cfg[] = { +/* ADDR mapping is from ds file. */ + { 0x100a0, 0x4 }, + { 0x100a1, 0x5 }, + { 0x100a2, 0x6 }, + { 0x100a3, 0x7 }, + { 0x100a4, 0x0 }, + { 0x100a5, 0x1 }, + { 0x100a6, 0x2 }, + { 0x100a7, 0x3 }, + { 0x110a0, 0x3 }, + { 0x110a1, 0x2 }, + { 0x110a2, 0x0 }, + { 0x110a3, 0x1 }, + { 0x110a4, 0x7 }, + { 0x110a5, 0x6 }, + { 0x110a6, 0x4 }, + { 0x110a7, 0x5 }, +/* End of ADDR mapping. */ + { 0x1005f, 0x5ff}, + { 0x1015f, 0x5ff}, + { 0x1105f, 0x5ff}, + { 0x1115f, 0x5ff}, + { 0x11005f, 0x5ff}, + { 0x11015f, 0x5ff}, + { 0x11105f, 0x5ff}, + { 0x11115f, 0x5ff}, + { 0x21005f, 0x5ff}, + { 0x21015f, 0x5ff}, + { 0x21105f, 0x5ff}, + { 0x21115f, 0x5ff}, + { 0x55, 0x1ff}, + { 0x1055, 0x1ff}, + { 0x2055, 0x1ff}, + { 0x200c5, 0x19}, + { 0x1200c5, 0xb}, + { 0x2200c5, 0x7}, + { 0x2002e, 0x2}, + { 0x12002e, 0x2}, + { 0x22002e, 0x2}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x20024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x2007d, 0x212}, + { 0x2007c, 0x61}, + { 0x120024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x12007d, 0x212}, + { 0x12007c, 0x61}, + { 0x220024, 0x1e3}, + { 0x2003a, 0x2}, + { 0x22007d, 0x212}, + { 0x22007c, 0x61}, + { 0x20056, 0x3}, + { 0x120056, 0x3}, + { 0x220056, 0x3}, + { 0x1004d, 0x600}, + { 0x1014d, 0x600}, + { 0x1104d, 0x600}, + { 0x1114d, 0x600}, + { 0x11004d, 0x600}, + { 0x11014d, 0x600}, + { 0x11104d, 0x600}, + { 0x11114d, 0x600}, + { 0x21004d, 0x600}, + { 0x21014d, 0x600}, + { 0x21104d, 0x600}, + { 0x21114d, 0x600}, + { 0x10049, 0xe00}, + { 0x10149, 0xe00}, + { 0x11049, 0xe00}, + { 0x11149, 0xe00}, + { 0x110049, 0xe00}, + { 0x110149, 0xe00}, + { 0x111049, 0xe00}, + { 0x111149, 0xe00}, + { 0x210049, 0xe00}, + { 0x210149, 0xe00}, + { 0x211049, 0xe00}, + { 0x211149, 0xe00}, + { 0x43, 0x60}, + { 0x1043, 0x60}, + { 0x2043, 0x60}, + { 0x20018, 0x1}, + { 0x20075, 0x4}, + { 0x20050, 0x0}, + { 0x2009b, 0x2}, + { 0x20008, 0x3a5}, + { 0x120008, 0x1d3}, + { 0x220008, 0x9c}, + { 0x20088, 0x9}, + { 0x200b2, 0x10c}, + { 0x10043, 0x5a1}, + { 0x10143, 0x5a1}, + { 0x11043, 0x5a1}, + { 0x11143, 0x5a1}, + { 0x1200b2, 0x10c}, + { 0x110043, 0x5a1}, + { 0x110143, 0x5a1}, + { 0x111043, 0x5a1}, + { 0x111143, 0x5a1}, + { 0x2200b2, 0x10c}, + { 0x210043, 0x5a1}, + { 0x210143, 0x5a1}, + { 0x211043, 0x5a1}, + { 0x211143, 0x5a1}, + { 0x200fa, 0x2}, + { 0x1200fa, 0x2}, + { 0x2200fa, 0x2}, + { 0x20019, 0x1}, + { 0x120019, 0x1}, + { 0x220019, 0x1}, + { 0x200f0, 0x600}, + { 0x200f1, 0x0}, + { 0x200f2, 0x4444}, + { 0x200f3, 0x8888}, + { 0x200f4, 0x5655}, + { 0x200f5, 0x0}, + { 0x200f6, 0x0}, + { 0x200f7, 0xf000}, + { 0x1004a, 0x500}, + { 0x1104a, 0x500}, + { 0x20025, 0x0}, + { 0x2002d, 0x0}, + { 0x12002d, 0x0}, + { 0x22002d, 0x0}, + { 0x2002c, 0x0}, + /* workaround STAR_3141216 marker */ + { 0x20021, 0x0}, + /* workaround STAR_3975199 marker */ + { 0x200c7, 0x21}, + /* workaround STAR_3975199 marker */ + { 0x200ca, 0x24}, + /* workaround STAR_3975199 marker */ + { 0x1200c7, 0x21}, + /* workaround STAR_3975199 marker */ + { 0x1200ca, 0x24}, +}; + +static struct dram_cfg_param ddr_ddrphy_trained_csr[] = { + { 0x1005f, 0x0}, + { 0x1015f, 0x0}, + { 0x1105f, 0x0}, + { 0x1115f, 0x0}, + { 0x11005f, 0x0}, + { 0x11015f, 0x0}, + { 0x11105f, 0x0}, + { 0x11115f, 0x0}, + { 0x21005f, 0x0}, + { 0x21015f, 0x0}, + { 0x21105f, 0x0}, + { 0x21115f, 0x0}, + { 0x55, 0x0}, + { 0x1055, 0x0}, + { 0x2055, 0x0}, + { 0x200c5, 0x0}, + { 0x1200c5, 0x0}, + { 0x2200c5, 0x0}, + { 0x2002e, 0x0}, + { 0x12002e, 0x0}, + { 0x22002e, 0x0}, + { 0x90204, 0x0}, + { 0x190204, 0x0}, + { 0x290204, 0x0}, + { 0x20024, 0x0}, + { 0x2003a, 0x0}, + { 0x2007d, 0x0}, + { 0x2007c, 0x0}, + { 0x120024, 0x0}, + { 0x12007d, 0x0}, + { 0x12007c, 0x0}, + { 0x220024, 0x0}, + { 0x22007d, 0x0}, + { 0x22007c, 0x0}, + { 0x20056, 0x0}, + { 0x120056, 0x0}, + { 0x220056, 0x0}, + { 0x1004d, 0x0}, + { 0x1014d, 0x0}, + { 0x1104d, 0x0}, + { 0x1114d, 0x0}, + { 0x11004d, 0x0}, + { 0x11014d, 0x0}, + { 0x11104d, 0x0}, + { 0x11114d, 0x0}, + { 0x21004d, 0x0}, + { 0x21014d, 0x0}, + { 0x21104d, 0x0}, + { 0x21114d, 0x0}, + { 0x10049, 0x0}, + { 0x10149, 0x0}, + { 0x11049, 0x0}, + { 0x11149, 0x0}, + { 0x110049, 0x0}, + { 0x110149, 0x0}, + { 0x111049, 0x0}, + { 0x111149, 0x0}, + { 0x210049, 0x0}, + { 0x210149, 0x0}, + { 0x211049, 0x0}, + { 0x211149, 0x0}, + { 0x43, 0x0}, + { 0x1043, 0x0}, + { 0x2043, 0x0}, + { 0x20018, 0x0}, + { 0x20075, 0x0}, + { 0x20050, 0x0}, + { 0x2009b, 0x0}, + { 0x20008, 0x0}, + { 0x120008, 0x0}, + { 0x220008, 0x0}, + { 0x20088, 0x0}, + { 0x200b2, 0x0}, + { 0x10043, 0x0}, + { 0x10143, 0x0}, + { 0x11043, 0x0}, + { 0x11143, 0x0}, + { 0x1200b2, 0x0}, + { 0x110043, 0x0}, + { 0x110143, 0x0}, + { 0x111043, 0x0}, + { 0x111143, 0x0}, + { 0x2200b2, 0x0}, + { 0x210043, 0x0}, + { 0x210143, 0x0}, + { 0x211043, 0x0}, + { 0x211143, 0x0}, + { 0x200fa, 0x0}, + { 0x1200fa, 0x0}, + { 0x2200fa, 0x0}, + { 0x20019, 0x0}, + { 0x120019, 0x0}, + { 0x220019, 0x0}, + { 0x200f0, 0x0}, + { 0x200f1, 0x0}, + { 0x200f2, 0x0}, + { 0x200f3, 0x0}, + { 0x200f4, 0x0}, + { 0x200f5, 0x0}, + { 0x200f6, 0x0}, + { 0x200f7, 0x0}, + { 0x1004a, 0x0}, + { 0x1104a, 0x0}, + { 0x20025, 0x0}, + { 0x2002d, 0x0}, + { 0x12002d, 0x0}, + { 0x22002d, 0x0}, + { 0x2002c, 0x0}, + { 0xd0000, 0x0}, + { 0x90000, 0x0}, + { 0x90001, 0x0}, + { 0x90002, 0x0}, + { 0x90003, 0x0}, + { 0x90004, 0x0}, + { 0x90005, 0x0}, + { 0x90029, 0x0}, + { 0x9002a, 0x0}, + { 0x9002b, 0x0}, + { 0x9002c, 0x0}, + { 0x9002d, 0x0}, + { 0x9002e, 0x0}, + { 0x9002f, 0x0}, + { 0x90030, 0x0}, + { 0x90031, 0x0}, + { 0x90032, 0x0}, + { 0x90033, 0x0}, + { 0x90034, 0x0}, + { 0x90035, 0x0}, + { 0x90036, 0x0}, + { 0x90037, 0x0}, + { 0x90038, 0x0}, + { 0x90039, 0x0}, + { 0x9003a, 0x0}, + { 0x9003b, 0x0}, + { 0x9003c, 0x0}, + { 0x9003d, 0x0}, + { 0x9003e, 0x0}, + { 0x9003f, 0x0}, + { 0x90040, 0x0}, + { 0x90041, 0x0}, + { 0x90042, 0x0}, + { 0x90043, 0x0}, + { 0x90044, 0x0}, + { 0x90045, 0x0}, + { 0x90046, 0x0}, + { 0x90047, 0x0}, + { 0x90048, 0x0}, + { 0x90049, 0x0}, + { 0x9004a, 0x0}, + { 0x9004b, 0x0}, + { 0x9004c, 0x0}, + { 0x9004d, 0x0}, + { 0x9004e, 0x0}, + { 0x9004f, 0x0}, + { 0x90050, 0x0}, + { 0x90051, 0x0}, + { 0x90052, 0x0}, + { 0x90053, 0x0}, + { 0x90054, 0x0}, + { 0x90055, 0x0}, + { 0x90056, 0x0}, + { 0x90057, 0x0}, + { 0x90058, 0x0}, + { 0x90059, 0x0}, + { 0x9005a, 0x0}, + { 0x9005b, 0x0}, + { 0x9005c, 0x0}, + { 0x9005d, 0x0}, + { 0x9005e, 0x0}, + { 0x9005f, 0x0}, + { 0x90060, 0x0}, + { 0x90061, 0x0}, + { 0x90062, 0x0}, + { 0x90063, 0x0}, + { 0x90064, 0x0}, + { 0x90065, 0x0}, + { 0x90066, 0x0}, + { 0x90067, 0x0}, + { 0x90068, 0x0}, + { 0x90069, 0x0}, + { 0x9006a, 0x0}, + { 0x9006b, 0x0}, + { 0x9006c, 0x0}, + { 0x9006d, 0x0}, + { 0x9006e, 0x0}, + { 0x9006f, 0x0}, + { 0x90070, 0x0}, + { 0x90071, 0x0}, + { 0x90072, 0x0}, + { 0x90073, 0x0}, + { 0x90074, 0x0}, + { 0x90075, 0x0}, + { 0x90076, 0x0}, + { 0x90077, 0x0}, + { 0x90078, 0x0}, + { 0x90079, 0x0}, + { 0x9007a, 0x0}, + { 0x9007b, 0x0}, + { 0x9007c, 0x0}, + { 0x9007d, 0x0}, + { 0x9007e, 0x0}, + { 0x9007f, 0x0}, + { 0x90080, 0x0}, + { 0x90081, 0x0}, + { 0x90082, 0x0}, + { 0x90083, 0x0}, + { 0x90084, 0x0}, + { 0x90085, 0x0}, + { 0x90086, 0x0}, + { 0x90087, 0x0}, + { 0x90088, 0x0}, + { 0x90089, 0x0}, + { 0x9008a, 0x0}, + { 0x9008b, 0x0}, + { 0x9008c, 0x0}, + { 0x9008d, 0x0}, + { 0x9008e, 0x0}, + { 0x9008f, 0x0}, + { 0x90090, 0x0}, + { 0x90091, 0x0}, + { 0x90092, 0x0}, + { 0x90093, 0x0}, + { 0x90094, 0x0}, + { 0x90095, 0x0}, + { 0x90096, 0x0}, + { 0x90097, 0x0}, + { 0x90098, 0x0}, + { 0x90099, 0x0}, + { 0x9009a, 0x0}, + { 0x9009b, 0x0}, + { 0x9009c, 0x0}, + { 0x9009d, 0x0}, + { 0x9009e, 0x0}, + { 0x9009f, 0x0}, + { 0x900a0, 0x0}, + { 0x900a1, 0x0}, + { 0x900a2, 0x0}, + { 0x900a3, 0x0}, + { 0x900a4, 0x0}, + { 0x900a5, 0x0}, + { 0x900a6, 0x0}, + { 0x900a7, 0x0}, + { 0x900a8, 0x0}, + { 0x900a9, 0x0}, + { 0x40000, 0x0}, + { 0x40020, 0x0}, + { 0x40040, 0x0}, + { 0x40060, 0x0}, + { 0x40001, 0x0}, + { 0x40021, 0x0}, + { 0x40041, 0x0}, + { 0x40061, 0x0}, + { 0x40002, 0x0}, + { 0x40022, 0x0}, + { 0x40042, 0x0}, + { 0x40062, 0x0}, + { 0x40003, 0x0}, + { 0x40023, 0x0}, + { 0x40043, 0x0}, + { 0x40063, 0x0}, + { 0x40004, 0x0}, + { 0x40024, 0x0}, + { 0x40044, 0x0}, + { 0x40064, 0x0}, + { 0x40005, 0x0}, + { 0x40025, 0x0}, + { 0x40045, 0x0}, + { 0x40065, 0x0}, + { 0x40006, 0x0}, + { 0x40026, 0x0}, + { 0x40046, 0x0}, + { 0x40066, 0x0}, + { 0x40007, 0x0}, + { 0x40027, 0x0}, + { 0x40047, 0x0}, + { 0x40067, 0x0}, + { 0x40008, 0x0}, + { 0x40028, 0x0}, + { 0x40048, 0x0}, + { 0x40068, 0x0}, + { 0x40009, 0x0}, + { 0x40029, 0x0}, + { 0x40049, 0x0}, + { 0x40069, 0x0}, + { 0x4000a, 0x0}, + { 0x4002a, 0x0}, + { 0x4004a, 0x0}, + { 0x4006a, 0x0}, + { 0x4000b, 0x0}, + { 0x4002b, 0x0}, + { 0x4004b, 0x0}, + { 0x4006b, 0x0}, + { 0x4000c, 0x0}, + { 0x4002c, 0x0}, + { 0x4004c, 0x0}, + { 0x4006c, 0x0}, + { 0x4000d, 0x0}, + { 0x4002d, 0x0}, + { 0x4004d, 0x0}, + { 0x4006d, 0x0}, + { 0x4000e, 0x0}, + { 0x4002e, 0x0}, + { 0x4004e, 0x0}, + { 0x4006e, 0x0}, + { 0x4000f, 0x0}, + { 0x4002f, 0x0}, + { 0x4004f, 0x0}, + { 0x4006f, 0x0}, + { 0x40010, 0x0}, + { 0x40030, 0x0}, + { 0x40050, 0x0}, + { 0x40070, 0x0}, + { 0x40011, 0x0}, + { 0x40031, 0x0}, + { 0x40051, 0x0}, + { 0x40071, 0x0}, + { 0x40012, 0x0}, + { 0x40032, 0x0}, + { 0x40052, 0x0}, + { 0x40072, 0x0}, + { 0x40013, 0x0}, + { 0x40033, 0x0}, + { 0x40053, 0x0}, + { 0x40073, 0x0}, + { 0x40014, 0x0}, + { 0x40034, 0x0}, + { 0x40054, 0x0}, + { 0x40074, 0x0}, + { 0x40015, 0x0}, + { 0x40035, 0x0}, + { 0x40055, 0x0}, + { 0x40075, 0x0}, + { 0x40016, 0x0}, + { 0x40036, 0x0}, + { 0x40056, 0x0}, + { 0x40076, 0x0}, + { 0x40017, 0x0}, + { 0x40037, 0x0}, + { 0x40057, 0x0}, + { 0x40077, 0x0}, + { 0x40018, 0x0}, + { 0x40038, 0x0}, + { 0x40058, 0x0}, + { 0x40078, 0x0}, + { 0x40019, 0x0}, + { 0x40039, 0x0}, + { 0x40059, 0x0}, + { 0x40079, 0x0}, + { 0x4001a, 0x0}, + { 0x4003a, 0x0}, + { 0x4005a, 0x0}, + { 0x4007a, 0x0}, + { 0x900aa, 0x0}, + { 0x900ab, 0x0}, + { 0x900ac, 0x0}, + { 0x900ad, 0x0}, + { 0x900ae, 0x0}, + { 0x900af, 0x0}, + { 0x900b0, 0x0}, + { 0x900b1, 0x0}, + { 0x900b2, 0x0}, + { 0x900b3, 0x0}, + { 0x900b4, 0x0}, + { 0x900b5, 0x0}, + { 0x900b6, 0x0}, + { 0x900b7, 0x0}, + { 0x900b8, 0x0}, + { 0x900b9, 0x0}, + { 0x900ba, 0x0}, + { 0x900bb, 0x0}, + { 0x900bc, 0x0}, + { 0x900bd, 0x0}, + { 0x900be, 0x0}, + { 0x900bf, 0x0}, + { 0x900c0, 0x0}, + { 0x900c1, 0x0}, + { 0x900c2, 0x0}, + { 0x900c3, 0x0}, + { 0x900c4, 0x0}, + { 0x900c5, 0x0}, + { 0x900c6, 0x0}, + { 0x900c7, 0x0}, + { 0x900c8, 0x0}, + { 0x900c9, 0x0}, + { 0x900ca, 0x0}, + { 0x900cb, 0x0}, + { 0x900cc, 0x0}, + { 0x900cd, 0x0}, + { 0x900ce, 0x0}, + { 0x900cf, 0x0}, + { 0x900d0, 0x0}, + { 0x900d1, 0x0}, + { 0x900d2, 0x0}, + { 0x900d3, 0x0}, + { 0x900d4, 0x0}, + { 0x900d5, 0x0}, + { 0x900d6, 0x0}, + { 0x900d7, 0x0}, + { 0x900d8, 0x0}, + { 0x900d9, 0x0}, + { 0x900da, 0x0}, + { 0x900db, 0x0}, + { 0x900dc, 0x0}, + { 0x900dd, 0x0}, + { 0x900de, 0x0}, + { 0x900df, 0x0}, + { 0x900e0, 0x0}, + { 0x900e1, 0x0}, + { 0x900e2, 0x0}, + { 0x900e3, 0x0}, + { 0x900e4, 0x0}, + { 0x900e5, 0x0}, + { 0x900e6, 0x0}, + { 0x900e7, 0x0}, + { 0x900e8, 0x0}, + { 0x900e9, 0x0}, + { 0x900ea, 0x0}, + { 0x900eb, 0x0}, + { 0x900ec, 0x0}, + { 0x900ed, 0x0}, + { 0x900ee, 0x0}, + { 0x900ef, 0x0}, + { 0x900f0, 0x0}, + { 0x900f1, 0x0}, + { 0x900f2, 0x0}, + { 0x900f3, 0x0}, + { 0x900f4, 0x0}, + { 0x900f5, 0x0}, + { 0x900f6, 0x0}, + { 0x900f7, 0x0}, + { 0x900f8, 0x0}, + { 0x900f9, 0x0}, + { 0x900fa, 0x0}, + { 0x900fb, 0x0}, + { 0x900fc, 0x0}, + { 0x900fd, 0x0}, + { 0x900fe, 0x0}, + { 0x900ff, 0x0}, + { 0x90100, 0x0}, + { 0x90101, 0x0}, + { 0x90102, 0x0}, + { 0x90103, 0x0}, + { 0x90104, 0x0}, + { 0x90105, 0x0}, + { 0x90106, 0x0}, + { 0x90107, 0x0}, + { 0x90108, 0x0}, + { 0x90109, 0x0}, + { 0x9010a, 0x0}, + { 0x9010b, 0x0}, + { 0x9010c, 0x0}, + { 0x9010d, 0x0}, + { 0x9010e, 0x0}, + { 0x9010f, 0x0}, + { 0x90110, 0x0}, + { 0x90111, 0x0}, + { 0x90112, 0x0}, + { 0x90113, 0x0}, + { 0x90114, 0x0}, + { 0x90115, 0x0}, + { 0x90116, 0x0}, + { 0x90117, 0x0}, + { 0x90118, 0x0}, + { 0x90119, 0x0}, + { 0x9011a, 0x0}, + { 0x9011b, 0x0}, + { 0x9011c, 0x0}, + { 0x9011d, 0x0}, + { 0x9011e, 0x0}, + { 0x9011f, 0x0}, + { 0x90120, 0x0}, + { 0x90121, 0x0}, + { 0x90122, 0x0}, + { 0x90123, 0x0}, + { 0x90124, 0x0}, + { 0x90125, 0x0}, + { 0x90126, 0x0}, + { 0x90127, 0x0}, + { 0x90128, 0x0}, + { 0x90129, 0x0}, + { 0x9012a, 0x0}, + { 0x9012b, 0x0}, + { 0x9012c, 0x0}, + { 0x9012d, 0x0}, + { 0x9012e, 0x0}, + { 0x9012f, 0x0}, + { 0x90130, 0x0}, + { 0x90131, 0x0}, + { 0x90132, 0x0}, + { 0x90133, 0x0}, + { 0x90134, 0x0}, + { 0x90135, 0x0}, + { 0x90136, 0x0}, + { 0x90137, 0x0}, + { 0x90138, 0x0}, + { 0x90139, 0x0}, + { 0x9013a, 0x0}, + { 0x9013b, 0x0}, + { 0x9013c, 0x0}, + { 0x9013d, 0x0}, + { 0x9013e, 0x0}, + { 0x9013f, 0x0}, + { 0x90140, 0x0}, + { 0x90141, 0x0}, + { 0x90142, 0x0}, + { 0x90143, 0x0}, + { 0x90144, 0x0}, + { 0x90145, 0x0}, + { 0x90146, 0x0}, + { 0x90147, 0x0}, + { 0x90148, 0x0}, + { 0x90149, 0x0}, + { 0x9014a, 0x0}, + { 0x9014b, 0x0}, + { 0x9014c, 0x0}, + { 0x9014d, 0x0}, + { 0x9014e, 0x0}, + { 0x9014f, 0x0}, + { 0x90150, 0x0}, + { 0x90151, 0x0}, + { 0x90152, 0x0}, + { 0x90153, 0x0}, + { 0x90154, 0x0}, + { 0x90155, 0x0}, + { 0x90156, 0x0}, + { 0x90157, 0x0}, + { 0x90158, 0x0}, + { 0x90159, 0x0}, + { 0x9015a, 0x0}, + { 0x9015b, 0x0}, + { 0x9015c, 0x0}, + { 0x9015d, 0x0}, + { 0x9015e, 0x0}, + { 0x9015f, 0x0}, + { 0x90160, 0x0}, + { 0x90161, 0x0}, + { 0x90162, 0x0}, + { 0x90163, 0x0}, + { 0x90164, 0x0}, + { 0x90165, 0x0}, + { 0x90166, 0x0}, + { 0x90167, 0x0}, + { 0x90168, 0x0}, + { 0x90169, 0x0}, + { 0x9016a, 0x0}, + { 0x9016b, 0x0}, + { 0x9016c, 0x0}, + { 0x9016d, 0x0}, + { 0x9016e, 0x0}, + { 0x9016f, 0x0}, + { 0x90170, 0x0}, + { 0x90171, 0x0}, + { 0x90172, 0x0}, + { 0x90173, 0x0}, + { 0x90174, 0x0}, + { 0x90175, 0x0}, + { 0x90176, 0x0}, + { 0x90177, 0x0}, + { 0x90178, 0x0}, + { 0x90179, 0x0}, + { 0x9017a, 0x0}, + { 0x9017b, 0x0}, + { 0x9017c, 0x0}, + { 0x9017d, 0x0}, + { 0x9017e, 0x0}, + { 0x9017f, 0x0}, + { 0x90180, 0x0}, + { 0x90181, 0x0}, + { 0x90182, 0x0}, + { 0x90183, 0x0}, + { 0x90184, 0x0}, + { 0x90006, 0x0}, + { 0x90007, 0x0}, + { 0x90008, 0x0}, + { 0x90009, 0x0}, + { 0x9000a, 0x0}, + { 0x9000b, 0x0}, + { 0xd00e7, 0x0}, + { 0x90017, 0x0}, + { 0x9001f, 0x0}, + { 0x90026, 0x0}, + { 0x400d0, 0x0}, + { 0x400d1, 0x0}, + { 0x400d2, 0x0}, + { 0x400d3, 0x0}, + { 0x400d4, 0x0}, + { 0x400d5, 0x0}, + { 0x400d6, 0x0}, + { 0x400d7, 0x0}, + { 0x200be, 0x0}, + { 0x2000b, 0x0}, + { 0x2000c, 0x0}, + { 0x2000d, 0x0}, + { 0x2000e, 0x0}, + { 0x12000b, 0x0}, + { 0x12000c, 0x0}, + { 0x12000d, 0x0}, + { 0x12000e, 0x0}, + { 0x22000b, 0x0}, + { 0x22000c, 0x0}, + { 0x22000d, 0x0}, + { 0x22000e, 0x0}, + { 0x9000c, 0x0}, + { 0x9000d, 0x0}, + { 0x9000e, 0x0}, + { 0x9000f, 0x0}, + { 0x90010, 0x0}, + { 0x90011, 0x0}, + { 0x90012, 0x0}, + { 0x90013, 0x0}, + { 0x20010, 0x0}, + { 0x20011, 0x0}, + { 0x120010, 0x0}, + { 0x120011, 0x0}, + { 0x40080, 0x0}, + { 0x40081, 0x0}, + { 0x40082, 0x0}, + { 0x40083, 0x0}, + { 0x40084, 0x0}, + { 0x40085, 0x0}, + { 0x140080, 0x0}, + { 0x140081, 0x0}, + { 0x140082, 0x0}, + { 0x140083, 0x0}, + { 0x140084, 0x0}, + { 0x140085, 0x0}, + { 0x240080, 0x0}, + { 0x240081, 0x0}, + { 0x240082, 0x0}, + { 0x240083, 0x0}, + { 0x240084, 0x0}, + { 0x240085, 0x0}, + { 0x400fd, 0x0}, + { 0x400f1, 0x0}, + { 0x10011, 0x0}, + { 0x10012, 0x0}, + { 0x10013, 0x0}, + { 0x10018, 0x0}, + { 0x10002, 0x0}, + { 0x100b2, 0x0}, + { 0x101b4, 0x0}, + { 0x102b4, 0x0}, + { 0x103b4, 0x0}, + { 0x104b4, 0x0}, + { 0x105b4, 0x0}, + { 0x106b4, 0x0}, + { 0x107b4, 0x0}, + { 0x108b4, 0x0}, + { 0x11011, 0x0}, + { 0x11012, 0x0}, + { 0x11013, 0x0}, + { 0x11018, 0x0}, + { 0x11002, 0x0}, + { 0x110b2, 0x0}, + { 0x111b4, 0x0}, + { 0x112b4, 0x0}, + { 0x113b4, 0x0}, + { 0x114b4, 0x0}, + { 0x115b4, 0x0}, + { 0x116b4, 0x0}, + { 0x117b4, 0x0}, + { 0x118b4, 0x0}, + { 0x20089, 0x0}, + { 0xc0080, 0x0}, + { 0x200cb, 0x0}, + { 0x10068, 0x0}, + { 0x10069, 0x0}, + { 0x10168, 0x0}, + { 0x10169, 0x0}, + { 0x10268, 0x0}, + { 0x10269, 0x0}, + { 0x10368, 0x0}, + { 0x10369, 0x0}, + { 0x10468, 0x0}, + { 0x10469, 0x0}, + { 0x10568, 0x0}, + { 0x10569, 0x0}, + { 0x10668, 0x0}, + { 0x10669, 0x0}, + { 0x10768, 0x0}, + { 0x10769, 0x0}, + { 0x10868, 0x0}, + { 0x10869, 0x0}, + { 0x100aa, 0x0}, + { 0x10062, 0x0}, + { 0x10001, 0x0}, + { 0x100a0, 0x0}, + { 0x100a1, 0x0}, + { 0x100a2, 0x0}, + { 0x100a3, 0x0}, + { 0x100a4, 0x0}, + { 0x100a5, 0x0}, + { 0x100a6, 0x0}, + { 0x100a7, 0x0}, + { 0x11068, 0x0}, + { 0x11069, 0x0}, + { 0x11168, 0x0}, + { 0x11169, 0x0}, + { 0x11268, 0x0}, + { 0x11269, 0x0}, + { 0x11368, 0x0}, + { 0x11369, 0x0}, + { 0x11468, 0x0}, + { 0x11469, 0x0}, + { 0x11568, 0x0}, + { 0x11569, 0x0}, + { 0x11668, 0x0}, + { 0x11669, 0x0}, + { 0x11768, 0x0}, + { 0x11769, 0x0}, + { 0x11868, 0x0}, + { 0x11869, 0x0}, + { 0x110aa, 0x0}, + { 0x11062, 0x0}, + { 0x11001, 0x0}, + { 0x110a0, 0x0}, + { 0x110a1, 0x0}, + { 0x110a2, 0x0}, + { 0x110a3, 0x0}, + { 0x110a4, 0x0}, + { 0x110a5, 0x0}, + { 0x110a6, 0x0}, + { 0x110a7, 0x0}, + { 0x80, 0x0}, + { 0x1080, 0x0}, + { 0x2080, 0x0}, + { 0x10020, 0x0}, + { 0x10080, 0x0}, + { 0x10081, 0x0}, + { 0x100d0, 0x0}, + { 0x100d1, 0x0}, + { 0x1008c, 0x0}, + { 0x1008d, 0x0}, + { 0x10180, 0x0}, + { 0x10181, 0x0}, + { 0x101d0, 0x0}, + { 0x101d1, 0x0}, + { 0x1018c, 0x0}, + { 0x1018d, 0x0}, + { 0x100c0, 0x0}, + { 0x100c1, 0x0}, + { 0x101c0, 0x0}, + { 0x101c1, 0x0}, + { 0x102c0, 0x0}, + { 0x102c1, 0x0}, + { 0x103c0, 0x0}, + { 0x103c1, 0x0}, + { 0x104c0, 0x0}, + { 0x104c1, 0x0}, + { 0x105c0, 0x0}, + { 0x105c1, 0x0}, + { 0x106c0, 0x0}, + { 0x106c1, 0x0}, + { 0x107c0, 0x0}, + { 0x107c1, 0x0}, + { 0x108c0, 0x0}, + { 0x108c1, 0x0}, + { 0x100ae, 0x0}, + { 0x100af, 0x0}, + { 0x11020, 0x0}, + { 0x11080, 0x0}, + { 0x11081, 0x0}, + { 0x110d0, 0x0}, + { 0x110d1, 0x0}, + { 0x1108c, 0x0}, + { 0x1108d, 0x0}, + { 0x11180, 0x0}, + { 0x11181, 0x0}, + { 0x111d0, 0x0}, + { 0x111d1, 0x0}, + { 0x1118c, 0x0}, + { 0x1118d, 0x0}, + { 0x110c0, 0x0}, + { 0x110c1, 0x0}, + { 0x111c0, 0x0}, + { 0x111c1, 0x0}, + { 0x112c0, 0x0}, + { 0x112c1, 0x0}, + { 0x113c0, 0x0}, + { 0x113c1, 0x0}, + { 0x114c0, 0x0}, + { 0x114c1, 0x0}, + { 0x115c0, 0x0}, + { 0x115c1, 0x0}, + { 0x116c0, 0x0}, + { 0x116c1, 0x0}, + { 0x117c0, 0x0}, + { 0x117c1, 0x0}, + { 0x118c0, 0x0}, + { 0x118c1, 0x0}, + { 0x110ae, 0x0}, + { 0x110af, 0x0}, + { 0x90201, 0x0}, + { 0x90202, 0x0}, + { 0x90203, 0x0}, + { 0x90205, 0x0}, + { 0x90206, 0x0}, + { 0x90207, 0x0}, + { 0x90208, 0x0}, + { 0x20020, 0x0}, + { 0x100080, 0x0}, + { 0x101080, 0x0}, + { 0x102080, 0x0}, + { 0x110020, 0x0}, + { 0x110080, 0x0}, + { 0x110081, 0x0}, + { 0x1100d0, 0x0}, + { 0x1100d1, 0x0}, + { 0x11008c, 0x0}, + { 0x11008d, 0x0}, + { 0x110180, 0x0}, + { 0x110181, 0x0}, + { 0x1101d0, 0x0}, + { 0x1101d1, 0x0}, + { 0x11018c, 0x0}, + { 0x11018d, 0x0}, + { 0x1100c0, 0x0}, + { 0x1100c1, 0x0}, + { 0x1101c0, 0x0}, + { 0x1101c1, 0x0}, + { 0x1102c0, 0x0}, + { 0x1102c1, 0x0}, + { 0x1103c0, 0x0}, + { 0x1103c1, 0x0}, + { 0x1104c0, 0x0}, + { 0x1104c1, 0x0}, + { 0x1105c0, 0x0}, + { 0x1105c1, 0x0}, + { 0x1106c0, 0x0}, + { 0x1106c1, 0x0}, + { 0x1107c0, 0x0}, + { 0x1107c1, 0x0}, + { 0x1108c0, 0x0}, + { 0x1108c1, 0x0}, + { 0x1100ae, 0x0}, + { 0x1100af, 0x0}, + { 0x111020, 0x0}, + { 0x111080, 0x0}, + { 0x111081, 0x0}, + { 0x1110d0, 0x0}, + { 0x1110d1, 0x0}, + { 0x11108c, 0x0}, + { 0x11108d, 0x0}, + { 0x111180, 0x0}, + { 0x111181, 0x0}, + { 0x1111d0, 0x0}, + { 0x1111d1, 0x0}, + { 0x11118c, 0x0}, + { 0x11118d, 0x0}, + { 0x1110c0, 0x0}, + { 0x1110c1, 0x0}, + { 0x1111c0, 0x0}, + { 0x1111c1, 0x0}, + { 0x1112c0, 0x0}, + { 0x1112c1, 0x0}, + { 0x1113c0, 0x0}, + { 0x1113c1, 0x0}, + { 0x1114c0, 0x0}, + { 0x1114c1, 0x0}, + { 0x1115c0, 0x0}, + { 0x1115c1, 0x0}, + { 0x1116c0, 0x0}, + { 0x1116c1, 0x0}, + { 0x1117c0, 0x0}, + { 0x1117c1, 0x0}, + { 0x1118c0, 0x0}, + { 0x1118c1, 0x0}, + { 0x1110ae, 0x0}, + { 0x1110af, 0x0}, + { 0x190201, 0x0}, + { 0x190202, 0x0}, + { 0x190203, 0x0}, + { 0x190205, 0x0}, + { 0x190206, 0x0}, + { 0x190207, 0x0}, + { 0x190208, 0x0}, + { 0x120020, 0x0}, + { 0x200080, 0x0}, + { 0x201080, 0x0}, + { 0x202080, 0x0}, + { 0x210020, 0x0}, + { 0x210080, 0x0}, + { 0x210081, 0x0}, + { 0x2100d0, 0x0}, + { 0x2100d1, 0x0}, + { 0x21008c, 0x0}, + { 0x21008d, 0x0}, + { 0x210180, 0x0}, + { 0x210181, 0x0}, + { 0x2101d0, 0x0}, + { 0x2101d1, 0x0}, + { 0x21018c, 0x0}, + { 0x21018d, 0x0}, + { 0x2100c0, 0x0}, + { 0x2100c1, 0x0}, + { 0x2101c0, 0x0}, + { 0x2101c1, 0x0}, + { 0x2102c0, 0x0}, + { 0x2102c1, 0x0}, + { 0x2103c0, 0x0}, + { 0x2103c1, 0x0}, + { 0x2104c0, 0x0}, + { 0x2104c1, 0x0}, + { 0x2105c0, 0x0}, + { 0x2105c1, 0x0}, + { 0x2106c0, 0x0}, + { 0x2106c1, 0x0}, + { 0x2107c0, 0x0}, + { 0x2107c1, 0x0}, + { 0x2108c0, 0x0}, + { 0x2108c1, 0x0}, + { 0x2100ae, 0x0}, + { 0x2100af, 0x0}, + { 0x211020, 0x0}, + { 0x211080, 0x0}, + { 0x211081, 0x0}, + { 0x2110d0, 0x0}, + { 0x2110d1, 0x0}, + { 0x21108c, 0x0}, + { 0x21108d, 0x0}, + { 0x211180, 0x0}, + { 0x211181, 0x0}, + { 0x2111d0, 0x0}, + { 0x2111d1, 0x0}, + { 0x21118c, 0x0}, + { 0x21118d, 0x0}, + { 0x2110c0, 0x0}, + { 0x2110c1, 0x0}, + { 0x2111c0, 0x0}, + { 0x2111c1, 0x0}, + { 0x2112c0, 0x0}, + { 0x2112c1, 0x0}, + { 0x2113c0, 0x0}, + { 0x2113c1, 0x0}, + { 0x2114c0, 0x0}, + { 0x2114c1, 0x0}, + { 0x2115c0, 0x0}, + { 0x2115c1, 0x0}, + { 0x2116c0, 0x0}, + { 0x2116c1, 0x0}, + { 0x2117c0, 0x0}, + { 0x2117c1, 0x0}, + { 0x2118c0, 0x0}, + { 0x2118c1, 0x0}, + { 0x2110ae, 0x0}, + { 0x2110af, 0x0}, + { 0x290201, 0x0}, + { 0x290202, 0x0}, + { 0x290203, 0x0}, + { 0x290205, 0x0}, + { 0x290206, 0x0}, + { 0x290207, 0x0}, + { 0x290208, 0x0}, + { 0x220020, 0x0}, + { 0x20077, 0x0}, + { 0x20072, 0x0}, + { 0x20073, 0x0}, + { 0x400c0, 0x0}, + { 0x10040, 0x0}, + { 0x10140, 0x0}, + { 0x10240, 0x0}, + { 0x10340, 0x0}, + { 0x10440, 0x0}, + { 0x10540, 0x0}, + { 0x10640, 0x0}, + { 0x10740, 0x0}, + { 0x10840, 0x0}, + { 0x11040, 0x0}, + { 0x11140, 0x0}, + { 0x11240, 0x0}, + { 0x11340, 0x0}, + { 0x11440, 0x0}, + { 0x11540, 0x0}, + { 0x11640, 0x0}, + { 0x11740, 0x0}, + { 0x11840, 0x0}, +}; + +static struct dram_cfg_param ddr_fsp0_cfg[] = { + { 0xd0000, 0x0}, + { 0x54003, 0xe94}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x131f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x36e4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x36e4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xe400}, + { 0x54033, 0x3236}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xe400}, + { 0x54039, 0x3236}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp1_cfg[] = { + { 0xd0000, 0x0}, + { 0x54002, 0x1}, + { 0x54003, 0x74a}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x121f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x1bb4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x1bb4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xb400}, + { 0x54033, 0x321b}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xb400}, + { 0x54039, 0x321b}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp2_cfg[] = { + { 0xd0000, 0x0}, + { 0x54002, 0x102}, + { 0x54003, 0x270}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x121f}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54012, 0x310}, + { 0x54019, 0x994}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1100}, + { 0x5401e, 0x4}, + { 0x5401f, 0x994}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1100}, + { 0x54024, 0x4}, + { 0x54032, 0x9400}, + { 0x54033, 0x3209}, + { 0x54034, 0x2600}, + { 0x54035, 0x11}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0x9400}, + { 0x54039, 0x3209}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x11}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { + { 0xd0000, 0x0}, + { 0x54003, 0xe94}, + { 0x54004, 0x4}, + { 0x54006, 0x15}, + { 0x54008, 0x61}, + { 0x54009, 0xc8}, + { 0x5400b, 0x4}, + { 0x5400d, 0x100}, + { 0x5400f, 0x100}, + { 0x54010, 0x2080}, + { 0x54012, 0x310}, + { 0x54019, 0x36e4}, + { 0x5401a, 0x32}, + { 0x5401b, 0x1126}, + { 0x5401c, 0x1108}, + { 0x5401e, 0x4}, + { 0x5401f, 0x36e4}, + { 0x54020, 0x32}, + { 0x54021, 0x1126}, + { 0x54022, 0x1108}, + { 0x54024, 0x4}, + { 0x54032, 0xe400}, + { 0x54033, 0x3236}, + { 0x54034, 0x2600}, + { 0x54035, 0x811}, + { 0x54036, 0x11}, + { 0x54037, 0x400}, + { 0x54038, 0xe400}, + { 0x54039, 0x3236}, + { 0x5403a, 0x2600}, + { 0x5403b, 0x811}, + { 0x5403c, 0x11}, + { 0x5403d, 0x400}, + { 0xd0000, 0x1}, +}; + +static struct dram_cfg_param ddr_phy_pie[] = { + { 0xd0000, 0x0}, + { 0x90000, 0x10}, + { 0x90001, 0x400}, + { 0x90002, 0x10e}, + { 0x90003, 0x0}, + { 0x90004, 0x0}, + { 0x90005, 0x8}, + { 0x90029, 0xb}, + { 0x9002a, 0x480}, + { 0x9002b, 0x109}, + { 0x9002c, 0x8}, + { 0x9002d, 0x448}, + { 0x9002e, 0x139}, + { 0x9002f, 0x8}, + { 0x90030, 0x478}, + { 0x90031, 0x109}, + { 0x90032, 0x0}, + { 0x90033, 0xe8}, + { 0x90034, 0x109}, + { 0x90035, 0x2}, + { 0x90036, 0x10}, + { 0x90037, 0x139}, + { 0x90038, 0xb}, + { 0x90039, 0x7c0}, + { 0x9003a, 0x139}, + { 0x9003b, 0x44}, + { 0x9003c, 0x633}, + { 0x9003d, 0x159}, + { 0x9003e, 0x14f}, + { 0x9003f, 0x630}, + { 0x90040, 0x159}, + { 0x90041, 0x47}, + { 0x90042, 0x633}, + { 0x90043, 0x149}, + { 0x90044, 0x4f}, + { 0x90045, 0x633}, + { 0x90046, 0x179}, + { 0x90047, 0x8}, + { 0x90048, 0xe0}, + { 0x90049, 0x109}, + { 0x9004a, 0x0}, + { 0x9004b, 0x7c8}, + { 0x9004c, 0x109}, + { 0x9004d, 0x0}, + { 0x9004e, 0x1}, + { 0x9004f, 0x8}, + { 0x90050, 0x30}, + { 0x90051, 0x65a}, + { 0x90052, 0x9}, + { 0x90053, 0x0}, + { 0x90054, 0x45a}, + { 0x90055, 0x9}, + { 0x90056, 0x0}, + { 0x90057, 0x448}, + { 0x90058, 0x109}, + { 0x90059, 0x40}, + { 0x9005a, 0x633}, + { 0x9005b, 0x179}, + { 0x9005c, 0x1}, + { 0x9005d, 0x618}, + { 0x9005e, 0x109}, + { 0x9005f, 0x40c0}, + { 0x90060, 0x633}, + { 0x90061, 0x149}, + { 0x90062, 0x8}, + { 0x90063, 0x4}, + { 0x90064, 0x48}, + { 0x90065, 0x4040}, + { 0x90066, 0x633}, + { 0x90067, 0x149}, + { 0x90068, 0x0}, + { 0x90069, 0x4}, + { 0x9006a, 0x48}, + { 0x9006b, 0x40}, + { 0x9006c, 0x633}, + { 0x9006d, 0x149}, + { 0x9006e, 0x0}, + { 0x9006f, 0x658}, + { 0x90070, 0x109}, + { 0x90071, 0x10}, + { 0x90072, 0x4}, + { 0x90073, 0x18}, + { 0x90074, 0x0}, + { 0x90075, 0x4}, + { 0x90076, 0x78}, + { 0x90077, 0x549}, + { 0x90078, 0x633}, + { 0x90079, 0x159}, + { 0x9007a, 0xd49}, + { 0x9007b, 0x633}, + { 0x9007c, 0x159}, + { 0x9007d, 0x94a}, + { 0x9007e, 0x633}, + { 0x9007f, 0x159}, + { 0x90080, 0x441}, + { 0x90081, 0x633}, + { 0x90082, 0x149}, + { 0x90083, 0x42}, + { 0x90084, 0x633}, + { 0x90085, 0x149}, + { 0x90086, 0x1}, + { 0x90087, 0x633}, + { 0x90088, 0x149}, + { 0x90089, 0x0}, + { 0x9008a, 0xe0}, + { 0x9008b, 0x109}, + { 0x9008c, 0xa}, + { 0x9008d, 0x10}, + { 0x9008e, 0x109}, + { 0x9008f, 0x9}, + { 0x90090, 0x3c0}, + { 0x90091, 0x149}, + { 0x90092, 0x9}, + { 0x90093, 0x3c0}, + { 0x90094, 0x159}, + { 0x90095, 0x18}, + { 0x90096, 0x10}, + { 0x90097, 0x109}, + { 0x90098, 0x0}, + { 0x90099, 0x3c0}, + { 0x9009a, 0x109}, + { 0x9009b, 0x18}, + { 0x9009c, 0x4}, + { 0x9009d, 0x48}, + { 0x9009e, 0x18}, + { 0x9009f, 0x4}, + { 0x900a0, 0x58}, + { 0x900a1, 0xb}, + { 0x900a2, 0x10}, + { 0x900a3, 0x109}, + { 0x900a4, 0x1}, + { 0x900a5, 0x10}, + { 0x900a6, 0x109}, + { 0x900a7, 0x5}, + { 0x900a8, 0x7c0}, + { 0x900a9, 0x109}, + { 0x40000, 0x811}, + { 0x40020, 0x880}, + { 0x40040, 0x0}, + { 0x40060, 0x0}, + { 0x40001, 0x4008}, + { 0x40021, 0x83}, + { 0x40041, 0x4f}, + { 0x40061, 0x0}, + { 0x40002, 0x4040}, + { 0x40022, 0x83}, + { 0x40042, 0x51}, + { 0x40062, 0x0}, + { 0x40003, 0x811}, + { 0x40023, 0x880}, + { 0x40043, 0x0}, + { 0x40063, 0x0}, + { 0x40004, 0x720}, + { 0x40024, 0xf}, + { 0x40044, 0x1740}, + { 0x40064, 0x0}, + { 0x40005, 0x16}, + { 0x40025, 0x83}, + { 0x40045, 0x4b}, + { 0x40065, 0x0}, + { 0x40006, 0x716}, + { 0x40026, 0xf}, + { 0x40046, 0x2001}, + { 0x40066, 0x0}, + { 0x40007, 0x716}, + { 0x40027, 0xf}, + { 0x40047, 0x2800}, + { 0x40067, 0x0}, + { 0x40008, 0x716}, + { 0x40028, 0xf}, + { 0x40048, 0xf00}, + { 0x40068, 0x0}, + { 0x40009, 0x720}, + { 0x40029, 0xf}, + { 0x40049, 0x1400}, + { 0x40069, 0x0}, + { 0x4000a, 0xe08}, + { 0x4002a, 0xc15}, + { 0x4004a, 0x0}, + { 0x4006a, 0x0}, + { 0x4000b, 0x625}, + { 0x4002b, 0x15}, + { 0x4004b, 0x0}, + { 0x4006b, 0x0}, + { 0x4000c, 0x4028}, + { 0x4002c, 0x80}, + { 0x4004c, 0x0}, + { 0x4006c, 0x0}, + { 0x4000d, 0xe08}, + { 0x4002d, 0xc1a}, + { 0x4004d, 0x0}, + { 0x4006d, 0x0}, + { 0x4000e, 0x625}, + { 0x4002e, 0x1a}, + { 0x4004e, 0x0}, + { 0x4006e, 0x0}, + { 0x4000f, 0x4040}, + { 0x4002f, 0x80}, + { 0x4004f, 0x0}, + { 0x4006f, 0x0}, + { 0x40010, 0x2604}, + { 0x40030, 0x15}, + { 0x40050, 0x0}, + { 0x40070, 0x0}, + { 0x40011, 0x708}, + { 0x40031, 0x5}, + { 0x40051, 0x0}, + { 0x40071, 0x2002}, + { 0x40012, 0x8}, + { 0x40032, 0x80}, + { 0x40052, 0x0}, + { 0x40072, 0x0}, + { 0x40013, 0x2604}, + { 0x40033, 0x1a}, + { 0x40053, 0x0}, + { 0x40073, 0x0}, + { 0x40014, 0x708}, + { 0x40034, 0xa}, + { 0x40054, 0x0}, + { 0x40074, 0x2002}, + { 0x40015, 0x4040}, + { 0x40035, 0x80}, + { 0x40055, 0x0}, + { 0x40075, 0x0}, + { 0x40016, 0x60a}, + { 0x40036, 0x15}, + { 0x40056, 0x1200}, + { 0x40076, 0x0}, + { 0x40017, 0x61a}, + { 0x40037, 0x15}, + { 0x40057, 0x1300}, + { 0x40077, 0x0}, + { 0x40018, 0x60a}, + { 0x40038, 0x1a}, + { 0x40058, 0x1200}, + { 0x40078, 0x0}, + { 0x40019, 0x642}, + { 0x40039, 0x1a}, + { 0x40059, 0x1300}, + { 0x40079, 0x0}, + { 0x4001a, 0x4808}, + { 0x4003a, 0x880}, + { 0x4005a, 0x0}, + { 0x4007a, 0x0}, + { 0x900aa, 0x0}, + { 0x900ab, 0x790}, + { 0x900ac, 0x11a}, + { 0x900ad, 0x8}, + { 0x900ae, 0x7aa}, + { 0x900af, 0x2a}, + { 0x900b0, 0x10}, + { 0x900b1, 0x7b2}, + { 0x900b2, 0x2a}, + { 0x900b3, 0x0}, + { 0x900b4, 0x7c8}, + { 0x900b5, 0x109}, + { 0x900b6, 0x10}, + { 0x900b7, 0x10}, + { 0x900b8, 0x109}, + { 0x900b9, 0x10}, + { 0x900ba, 0x2a8}, + { 0x900bb, 0x129}, + { 0x900bc, 0x8}, + { 0x900bd, 0x370}, + { 0x900be, 0x129}, + { 0x900bf, 0xa}, + { 0x900c0, 0x3c8}, + { 0x900c1, 0x1a9}, + { 0x900c2, 0xc}, + { 0x900c3, 0x408}, + { 0x900c4, 0x199}, + { 0x900c5, 0x14}, + { 0x900c6, 0x790}, + { 0x900c7, 0x11a}, + { 0x900c8, 0x8}, + { 0x900c9, 0x4}, + { 0x900ca, 0x18}, + { 0x900cb, 0xe}, + { 0x900cc, 0x408}, + { 0x900cd, 0x199}, + { 0x900ce, 0x8}, + { 0x900cf, 0x8568}, + { 0x900d0, 0x108}, + { 0x900d1, 0x18}, + { 0x900d2, 0x790}, + { 0x900d3, 0x16a}, + { 0x900d4, 0x8}, + { 0x900d5, 0x1d8}, + { 0x900d6, 0x169}, + { 0x900d7, 0x10}, + { 0x900d8, 0x8558}, + { 0x900d9, 0x168}, + { 0x900da, 0x1ff8}, + { 0x900db, 0x85a8}, + { 0x900dc, 0x1e8}, + { 0x900dd, 0x50}, + { 0x900de, 0x798}, + { 0x900df, 0x16a}, + { 0x900e0, 0x60}, + { 0x900e1, 0x7a0}, + { 0x900e2, 0x16a}, + { 0x900e3, 0x8}, + { 0x900e4, 0x8310}, + { 0x900e5, 0x168}, + { 0x900e6, 0x8}, + { 0x900e7, 0xa310}, + { 0x900e8, 0x168}, + { 0x900e9, 0xa}, + { 0x900ea, 0x408}, + { 0x900eb, 0x169}, + { 0x900ec, 0x6e}, + { 0x900ed, 0x0}, + { 0x900ee, 0x68}, + { 0x900ef, 0x0}, + { 0x900f0, 0x408}, + { 0x900f1, 0x169}, + { 0x900f2, 0x0}, + { 0x900f3, 0x8310}, + { 0x900f4, 0x168}, + { 0x900f5, 0x0}, + { 0x900f6, 0xa310}, + { 0x900f7, 0x168}, + { 0x900f8, 0x1ff8}, + { 0x900f9, 0x85a8}, + { 0x900fa, 0x1e8}, + { 0x900fb, 0x68}, + { 0x900fc, 0x798}, + { 0x900fd, 0x16a}, + { 0x900fe, 0x78}, + { 0x900ff, 0x7a0}, + { 0x90100, 0x16a}, + { 0x90101, 0x68}, + { 0x90102, 0x790}, + { 0x90103, 0x16a}, + { 0x90104, 0x8}, + { 0x90105, 0x8b10}, + { 0x90106, 0x168}, + { 0x90107, 0x8}, + { 0x90108, 0xab10}, + { 0x90109, 0x168}, + { 0x9010a, 0xa}, + { 0x9010b, 0x408}, + { 0x9010c, 0x169}, + { 0x9010d, 0x58}, + { 0x9010e, 0x0}, + { 0x9010f, 0x68}, + { 0x90110, 0x0}, + { 0x90111, 0x408}, + { 0x90112, 0x169}, + { 0x90113, 0x0}, + { 0x90114, 0x8b10}, + { 0x90115, 0x168}, + { 0x90116, 0x1}, + { 0x90117, 0xab10}, + { 0x90118, 0x168}, + { 0x90119, 0x0}, + { 0x9011a, 0x1d8}, + { 0x9011b, 0x169}, + { 0x9011c, 0x80}, + { 0x9011d, 0x790}, + { 0x9011e, 0x16a}, + { 0x9011f, 0x18}, + { 0x90120, 0x7aa}, + { 0x90121, 0x6a}, + { 0x90122, 0xa}, + { 0x90123, 0x0}, + { 0x90124, 0x1e9}, + { 0x90125, 0x8}, + { 0x90126, 0x8080}, + { 0x90127, 0x108}, + { 0x90128, 0xf}, + { 0x90129, 0x408}, + { 0x9012a, 0x169}, + { 0x9012b, 0xc}, + { 0x9012c, 0x0}, + { 0x9012d, 0x68}, + { 0x9012e, 0x9}, + { 0x9012f, 0x0}, + { 0x90130, 0x1a9}, + { 0x90131, 0x0}, + { 0x90132, 0x408}, + { 0x90133, 0x169}, + { 0x90134, 0x0}, + { 0x90135, 0x8080}, + { 0x90136, 0x108}, + { 0x90137, 0x8}, + { 0x90138, 0x7aa}, + { 0x90139, 0x6a}, + { 0x9013a, 0x0}, + { 0x9013b, 0x8568}, + { 0x9013c, 0x108}, + { 0x9013d, 0xb7}, + { 0x9013e, 0x790}, + { 0x9013f, 0x16a}, + { 0x90140, 0x1f}, + { 0x90141, 0x0}, + { 0x90142, 0x68}, + { 0x90143, 0x8}, + { 0x90144, 0x8558}, + { 0x90145, 0x168}, + { 0x90146, 0xf}, + { 0x90147, 0x408}, + { 0x90148, 0x169}, + { 0x90149, 0xd}, + { 0x9014a, 0x0}, + { 0x9014b, 0x68}, + { 0x9014c, 0x0}, + { 0x9014d, 0x408}, + { 0x9014e, 0x169}, + { 0x9014f, 0x0}, + { 0x90150, 0x8558}, + { 0x90151, 0x168}, + { 0x90152, 0x8}, + { 0x90153, 0x3c8}, + { 0x90154, 0x1a9}, + { 0x90155, 0x3}, + { 0x90156, 0x370}, + { 0x90157, 0x129}, + { 0x90158, 0x20}, + { 0x90159, 0x2aa}, + { 0x9015a, 0x9}, + { 0x9015b, 0x8}, + { 0x9015c, 0xe8}, + { 0x9015d, 0x109}, + { 0x9015e, 0x0}, + { 0x9015f, 0x8140}, + { 0x90160, 0x10c}, + { 0x90161, 0x10}, + { 0x90162, 0x8138}, + { 0x90163, 0x104}, + { 0x90164, 0x8}, + { 0x90165, 0x448}, + { 0x90166, 0x109}, + { 0x90167, 0xf}, + { 0x90168, 0x7c0}, + { 0x90169, 0x109}, + { 0x9016a, 0x0}, + { 0x9016b, 0xe8}, + { 0x9016c, 0x109}, + { 0x9016d, 0x47}, + { 0x9016e, 0x630}, + { 0x9016f, 0x109}, + { 0x90170, 0x8}, + { 0x90171, 0x618}, + { 0x90172, 0x109}, + { 0x90173, 0x8}, + { 0x90174, 0xe0}, + { 0x90175, 0x109}, + { 0x90176, 0x0}, + { 0x90177, 0x7c8}, + { 0x90178, 0x109}, + { 0x90179, 0x8}, + { 0x9017a, 0x8140}, + { 0x9017b, 0x10c}, + { 0x9017c, 0x0}, + { 0x9017d, 0x478}, + { 0x9017e, 0x109}, + { 0x9017f, 0x0}, + { 0x90180, 0x1}, + { 0x90181, 0x8}, + { 0x90182, 0x8}, + { 0x90183, 0x4}, + { 0x90184, 0x0}, + { 0x90006, 0x8}, + { 0x90007, 0x7c8}, + { 0x90008, 0x109}, + { 0x90009, 0x0}, + { 0x9000a, 0x400}, + { 0x9000b, 0x106}, + { 0xd00e7, 0x400}, + { 0x90017, 0x0}, + { 0x9001f, 0x2b}, + { 0x90026, 0x69}, + { 0x400d0, 0x0}, + { 0x400d1, 0x101}, + { 0x400d2, 0x105}, + { 0x400d3, 0x107}, + { 0x400d4, 0x10f}, + { 0x400d5, 0x202}, + { 0x400d6, 0x20a}, + { 0x400d7, 0x20b}, + { 0x2003a, 0x2}, + { 0x200be, 0x3}, + { 0x2000b, 0x75}, + { 0x2000c, 0xe9}, + { 0x2000d, 0x91c}, + { 0x2000e, 0x2c}, + { 0x12000b, 0x3b}, + { 0x12000c, 0x74}, + { 0x12000d, 0x48e}, + { 0x12000e, 0x2c}, + { 0x22000b, 0x14}, + { 0x22000c, 0x27}, + { 0x22000d, 0x186}, + { 0x22000e, 0x10}, + { 0x9000c, 0x0}, + { 0x9000d, 0x173}, + { 0x9000e, 0x60}, + { 0x9000f, 0x6110}, + { 0x90010, 0x2152}, + { 0x90011, 0xdfbd}, + { 0x90012, 0x2060}, + { 0x90013, 0x6152}, + { 0x20010, 0x5a}, + { 0x20011, 0x3}, + { 0x120010, 0x5a}, + { 0x120011, 0x3}, + { 0x40080, 0xe0}, + { 0x40081, 0x12}, + { 0x40082, 0xe0}, + { 0x40083, 0x12}, + { 0x40084, 0xe0}, + { 0x40085, 0x12}, + { 0x140080, 0xe0}, + { 0x140081, 0x12}, + { 0x140082, 0xe0}, + { 0x140083, 0x12}, + { 0x140084, 0xe0}, + { 0x140085, 0x12}, + { 0x240080, 0xe0}, + { 0x240081, 0x12}, + { 0x240082, 0xe0}, + { 0x240083, 0x12}, + { 0x240084, 0xe0}, + { 0x240085, 0x12}, + { 0x400fd, 0xf}, + { 0x400f1, 0xe}, + { 0x10011, 0x1}, + { 0x10012, 0x1}, + { 0x10013, 0x180}, + { 0x10018, 0x1}, + { 0x10002, 0x6209}, + { 0x100b2, 0x1}, + { 0x101b4, 0x1}, + { 0x102b4, 0x1}, + { 0x103b4, 0x1}, + { 0x104b4, 0x1}, + { 0x105b4, 0x1}, + { 0x106b4, 0x1}, + { 0x107b4, 0x1}, + { 0x108b4, 0x1}, + { 0x11011, 0x1}, + { 0x11012, 0x1}, + { 0x11013, 0x180}, + { 0x11018, 0x1}, + { 0x11002, 0x6209}, + { 0x110b2, 0x1}, + { 0x111b4, 0x1}, + { 0x112b4, 0x1}, + { 0x113b4, 0x1}, + { 0x114b4, 0x1}, + { 0x115b4, 0x1}, + { 0x116b4, 0x1}, + { 0x117b4, 0x1}, + { 0x118b4, 0x1}, + { 0x20089, 0x1}, + { 0x20088, 0x19}, + { 0xc0080, 0x0}, + /* workaround STAR_3256585 marker */ + { 0x2000b, 0x41a}, + /* workaround STAR_3256585 marker */ + { 0x12000b, 0x20d}, + /* workaround STAR_3256585 marker */ + { 0x22000b, 0xb0}, + { 0xd0000, 0x1}, +}; + +static struct dram_fsp_msg ddr_dram_fsp_msg[] = { + { + /* P0 3733mts 1D */ + .drate = 3733, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), + }, + { + /* P1 1866mts 1D */ + .drate = 1866, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), + }, + { + /* P2 625mts 1D */ + .drate = 625, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = ddr_fsp2_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), + }, + { + /* P0 3733mts 2D */ + .drate = 3733, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = ddr_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_2CS_2GB = { + .ddrc_cfg = ddr_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), + .ddrphy_cfg = ddr_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), + .fsp_msg = ddr_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), + .ddrphy_trained_csr = ddr_ddrphy_trained_csr, + .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), + .ddrphy_pie = ddr_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), + .fsp_table = { 3733, 1866, 625, }, + .fsp_cfg = ddr_dram_fsp_cfg, + .fsp_cfg_num = ARRAY_SIZE(ddr_dram_fsp_cfg), +}; diff --git a/board/nxp/imx93_frdm/spl.c b/board/nxp/imx93_frdm/spl.c index 068091ba0e9..40054ff72d0 100644 --- a/board/nxp/imx93_frdm/spl.c +++ b/board/nxp/imx93_frdm/spl.c @@ -33,9 +33,10 @@ static struct _drams { u8 mr8; struct dram_timing_info *pdram_timing; char *name; -} frdm_drams[2] = { +} frdm_drams[3] = { {0x10, &dram_timing_1GB, "1GB DRAM" }, - {0x18, &dram_timing_2GB, "2GB DRAM" }, + {0x12, &dram_timing_2CS_2GB, "2CS_2GB DRAM" }, + {0x18, &dram_timing_1CS_2GB, "1CS_2GB DRAM" }, }; int spl_board_boot_device(enum boot_device boot_dev_spl) diff --git a/board/nxp/imx93_qsb/imx93_qsb.env b/board/nxp/imx93_qsb/imx93_qsb.env index d669c6e3133..d14a1b6c9bd 100644 --- a/board/nxp/imx93_qsb/imx93_qsb.env +++ b/board/nxp/imx93_qsb/imx93_qsb.env @@ -10,6 +10,10 @@ fdt_addr_r=0x83000000 fdt_addr=0x83000000 fdtfile=DEFAULT_FDT_FILE image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX mmcpart=1 mmcroot=/dev/mmcblk1p2 rootwait rw diff --git a/board/nxp/imx94_evk/imx94_evk.env b/board/nxp/imx94_evk/imx94_evk.env index 894f5975812..c2006c95529 100644 --- a/board/nxp/imx94_evk/imx94_evk.env +++ b/board/nxp/imx94_evk/imx94_evk.env @@ -19,7 +19,10 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 +ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 image=Image splashimage=0xA0000000 console=ttyLP0,115200 earlycon diff --git a/board/nxp/imx952_evk/imx952_evk.env b/board/nxp/imx952_evk/imx952_evk.env index 6ecaf9724c1..07faeb9fc9a 100644 --- a/board/nxp/imx952_evk/imx952_evk.env +++ b/board/nxp/imx952_evk/imx952_evk.env @@ -52,7 +52,10 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 +ip_dyn=yes kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 image=Image splashimage=0xA0000000 console=ttyLP0,115200 earlycon diff --git a/board/nxp/imx95_evk/imx95_evk.env b/board/nxp/imx95_evk/imx95_evk.env index 19f9bd5c16e..1d63a74aefa 100644 --- a/board/nxp/imx95_evk/imx95_evk.env +++ b/board/nxp/imx95_evk/imx95_evk.env @@ -3,8 +3,11 @@ initrd_addr=0x93800000 emmc_dev=0 sd_dev=1 scriptaddr=0x93500000 -kernel_addr_r=CONFIG_SYS_LOAD_ADDR image=Image +ip_dyn=yes +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0xC0000000 +kernel_comp_size=0x2000000 splashimage=0xA0000000 console=ttyLP0,115200 earlycon fdt_addr_r=0x93000000 diff --git a/board/nxp/ls1012ardb/Kconfig b/board/nxp/ls1012ardb/Kconfig index bbe5ce21109..ff5a57aaa41 100644 --- a/board/nxp/ls1012ardb/Kconfig +++ b/board/nxp/ls1012ardb/Kconfig @@ -63,7 +63,7 @@ config SYS_BOARD default "ls1012ardb" config SYS_VENDOR - default "nxp" + default "nxp" config SYS_SOC default "fsl-layerscape" diff --git a/board/nxp/ls1028a/ls1028ardb.env b/board/nxp/ls1028a/ls1028ardb.env new file mode 100644 index 00000000000..dc1cb01e50a --- /dev/null +++ b/board/nxp/ls1028a/ls1028ardb.env @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ + +board=ls1028ardb +hwconfig=fsl_ddr:bank_intlv=auto +fdtfile=fsl-ls1028a-rdb.dtb +image=Image +extra_bootargs=iommu.passthrough=1 arm-smmu.disable_bypass=0 +othbootargs=video=1920x1080-32@60 cma=640M +ramdisk_addr=0x800000 +ramdisk_size=0x2000000 +bootm_size=0x10000000 +kernel_addr=0x01000000 +scriptaddr=0x80000000 +scripthdraddr=0x80080000 +fdtheader_addr_r=0x80100000 +kernelheader_addr_r=0x80200000 +load_addr=0xa0000000 +kernel_addr_r=0x81000000 +fdt_addr_r=0x90000000 +ramdisk_addr_r=0xa0000000 +kernel_start=0x1000000 +kernelheader_start=0x600000 +kernel_load=0xa0000000 +kernel_size=0x2800000 +kernelheader_size=0x40000 +kernel_addr_sd=0x8000 +kernel_size_sd=0x14000 +kernelhdr_addr_sd=0x3000 +kernelhdr_size_sd=0x20 +console=ttyS0,115200 +console_dbg=earlycon=uart8250,mmio,0x21c0500 +boot_script_hdr=hdr_ls1028ardb_bs.out +xspi_bootcmd=echo Trying load from FlexSPI flash ...;sf probe 0:0 && sf read $load_addr + $kernel_start $kernel_size ; env exists secureboot &&sf read $kernelheader_addr_r + $kernelheader_start $kernelheader_size && esbc_validate ${kernelheader_addr_r}; bootm + $load_addr#$board +xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;sf probe 0:0 && sf read + $load_addr 0x940000 0x30000 && hdp load $load_addr 0x2000 +sd_bootcmd=echo Trying load from SD ...;mmc dev 0;mmcinfo; mmc read $load_addr $kernel_addr_sd + $kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r $kernelhdr_addr_sd + $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm $load_addr#$board +sd_hdploadcmd=echo Trying load HDP firmware from SD..;mmc dev 0;mmcinfo;mmc read $load_addr + 0x4a00 0x200 && hdp load $load_addr 0x2000 +emmc_bootcmd=echo Trying load from EMMC ..;mmc dev 1;mmcinfo; mmc read $load_addr + $kernel_addr_sd $kernel_size_sd && env exists secureboot && mmc read $kernelheader_addr_r + $kernelhdr_addr_sd $kernelhdr_size_sd && esbc_validate ${kernelheader_addr_r};bootm + $load_addr#$board +emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;mmc dev 1;mmcinfo;mmc read $load_addr + 0x4a00 0x200 && hdp load $load_addr 0x2000 diff --git a/board/nxp/mx6memcal/Kconfig b/board/nxp/mx6memcal/Kconfig index a6c39d5e4d1..03d8422242f 100644 --- a/board/nxp/mx6memcal/Kconfig +++ b/board/nxp/mx6memcal/Kconfig @@ -35,30 +35,30 @@ choice The choices below reflect the most commonly used options for your UART. - config UART2_EIM_D26_27 - bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)" - depends on SERIAL_CONSOLE_UART2 - help - Choose this configuration if you're using pads - EIM_D26 and D27 for a console on UART2. - This is typical for designs that are based on the - NXP SABRELite. +config UART2_EIM_D26_27 + bool "UART2 on EIM_D26/27 (SabreLite, Nitrogen6x)" + depends on SERIAL_CONSOLE_UART2 + help + Choose this configuration if you're using pads + EIM_D26 and D27 for a console on UART2. + This is typical for designs that are based on the + NXP SABRELite. - config UART1_CSI0_DAT10_11 - bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)" - depends on SERIAL_CONSOLE_UART1 - help - Choose this configuration if you're using pads - CSI0_DAT10 and DAT11 for a console on UART1 as - is done on the i.MX6 Wand board and i.MX6 SabreSD. +config UART1_CSI0_DAT10_11 + bool "UART1 on CSI0_DAT10/11 (Wand, SabreSD)" + depends on SERIAL_CONSOLE_UART1 + help + Choose this configuration if you're using pads + CSI0_DAT10 and DAT11 for a console on UART1 as + is done on the i.MX6 Wand board and i.MX6 SabreSD. - config UART1_UART1 - bool "UART1 on UART1 (i.MX6SL EVK, WaRP)" - depends on SERIAL_CONSOLE_UART1 - help - Choose this configuration if you're using pads - UART1_TXD/RXD for a console on UART1 as is done - on most i.MX6SL designs. +config UART1_UART1 + bool "UART1 on UART1 (i.MX6SL EVK, WaRP)" + depends on SERIAL_CONSOLE_UART1 + help + Choose this configuration if you're using pads + UART1_TXD/RXD for a console on UART1 as is done + on most i.MX6SL designs. endchoice @@ -215,12 +215,12 @@ config REFR range 0 7 default 7 help - This selects the number of refreshes (-1) during each period. - i.e.: - 0 == 1 refresh (tRFC) - 7 == 8 refreshes (tRFC*8) - See the description of MDREF[REFR] in the reference manual for - details. + This selects the number of refreshes (-1) during each period. + i.e.: + 0 == 1 refresh (tRFC) + 7 == 8 refreshes (tRFC*8) + See the description of MDREF[REFR] in the reference manual for + details. endmenu diff --git a/board/nxp/mx6sabreauto/mx6sabreauto.env b/board/nxp/mx6sabreauto/mx6sabreauto.env new file mode 100644 index 00000000000..31a16905ef5 --- /dev/null +++ b/board/nxp/mx6sabreauto/mx6sabreauto.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc3 + +#include <env/nxp/mx6sabre_common.env> diff --git a/board/nxp/mx6sabresd/mx6sabresd.env b/board/nxp/mx6sabresd/mx6sabresd.env new file mode 100644 index 00000000000..3608e931665 --- /dev/null +++ b/board/nxp/mx6sabresd/mx6sabresd.env @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +console=ttymxc0 + +#include <env/nxp/mx6sabre_common.env> diff --git a/board/nxp/mx6ullevk/mx6ullevk.env b/board/nxp/mx6ullevk/mx6ullevk.env new file mode 100644 index 00000000000..0fce3aaaa4e --- /dev/null +++ b/board/nxp/mx6ullevk/mx6ullevk.env @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttymxc0 +initrd_high=0xffffffff +fdt_file=undefined +fdt_addr=0x83000000 +boot_fdt=try +ip_dyn=yes +videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0 +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk1p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +findfdt=if test $fdt_file = undefined; then + if test $board_name = ULZ-EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ulz-14x14-evk.dtb; + fi; + if test $board_name = EVK && test $board_rev = 14X14; then + setenv fdt_file imx6ull-14x14-evk.dtb; + fi; + if test $fdt_file = undefined; then + echo WARNING: Could not determine dtb to use; + fi; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/board/nxp/mx7ulp_evk/mx7ulp_evk.env b/board/nxp/mx7ulp_evk/mx7ulp_evk.env new file mode 100644 index 00000000000..f5a384a61de --- /dev/null +++ b/board/nxp/mx7ulp_evk/mx7ulp_evk.env @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +console=ttyLP0 +initrd_high=0xffffffff +fdt_file=imx7ulp-evk.dtb +fdt_addr=0x63000000 +boot_fdt=try +earlycon=lpuart32,0x402D0010 +ip_dyn=yes +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +mmcroot=/dev/mmcblk0p2 rootwait rw +mmcautodetect=yes +mmcargs=setenv bootargs console=${console},${baudrate} root=${mmcroot} +loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} +loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} +mmcboot=echo Booting from mmc ...; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + usb start; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdt_file}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; diff --git a/board/out4/o4-imx6ull-nano/Kconfig b/board/out4/o4-imx6ull-nano/Kconfig index e2ab80b6d4d..1b948fdc9ff 100644 --- a/board/out4/o4-imx6ull-nano/Kconfig +++ b/board/out4/o4-imx6ull-nano/Kconfig @@ -13,21 +13,21 @@ choice prompt "Memory model" default K4B4G1646D_BCMA help - Memory type setup. + Memory type setup. Please choose correct memory model here. config K4B4G1646D_BCMA bool "K4B4G1646D-BCMA 256Mx16 (512 MiB/chip)" help - Samsung DDR3 SDRAM - K4B4G1646D-BCMA + Samsung DDR3 SDRAM + K4B4G1646D-BCMA config MT41K256M16HA_125E bool "MT41K256M16HA-125:E 256Mx16 (512 MiB/chip)" help - Micron DDR3L SDRAM - MT41K256M16HA-125:E + Micron DDR3L SDRAM + MT41K256M16HA-125:E endchoice @@ -35,21 +35,21 @@ choice prompt "Mainboard model" default O4_IMX_NANO help - Mainboard setup. + Mainboard setup. Please choose correct main board model here. config O4_IMX_NANO bool "O4-iMX-NANO" help - A baseboard for EV-iMX280-NANO module: - https://out4.ru/products/board/18-o4-imx-nano.html + A baseboard for EV-iMX280-NANO module: + https://out4.ru/products/board/18-o4-imx-nano.html config EV_IMX280_NANO_X_MB bool "EV-IMX280-NANO-X-MB" help - A simple baseboard for EV-iMX280-NANO module: - http://evodbg.net/products/mx28-eval-kits/14-ev-imx280-nano-x-mb.html + A simple baseboard for EV-iMX280-NANO module: + http://evodbg.net/products/mx28-eval-kits/14-ev-imx280-nano-x-mb.html endchoice diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 6afd03086f7..87fa70632e5 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -2,14 +2,14 @@ config PHYTEC_SOM_DETECTION bool "Support SoM detection for PHYTEC platforms" select SPL_CRC8 if SPL help - Support of I2C EEPROM based SoM detection. + Support of I2C EEPROM based SoM detection. config PHYTEC_SOM_DETECTION_BLOCKS bool "Extend SoM detection with block support" depends on PHYTEC_SOM_DETECTION help - Extend the I2C EEPROM based SoM detection with API v3. This API - introduces blocks with different payloads. + Extend the I2C EEPROM based SoM detection with API v3. This API + introduces blocks with different payloads. config PHYTEC_IMX8M_SOM_DETECTION bool "Support SoM detection for i.MX8M PHYTEC platforms" @@ -35,8 +35,8 @@ config PHYTEC_AM62_SOM_DETECTION depends on SPL_I2C && DM_I2C default y help - Support of I2C EEPROM based SoM detection. Supported - for PHYTEC AM62x boards. + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC AM62x boards. config PHYTEC_AM62A_SOM_DETECTION bool "Support SoM detection for AM62Ax PHYTEC platforms" @@ -46,8 +46,8 @@ config PHYTEC_AM62A_SOM_DETECTION depends on SPL_I2C && DM_I2C default y help - Support of I2C EEPROM based SoM detection. Supported - for PHYTEC AM62Ax boards. + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC AM62Ax boards. config PHYTEC_AM64_SOM_DETECTION bool "Support SoM detection for AM64x PHYTEC platforms" @@ -57,8 +57,8 @@ config PHYTEC_AM64_SOM_DETECTION depends on SPL_I2C && DM_I2C default y help - Support of I2C EEPROM based SoM detection. Supported - for PHYTEC AM64x boards. + Support of I2C EEPROM based SoM detection. Supported + for PHYTEC AM64x boards. config PHYTEC_EEPROM_BUS int "Board EEPROM's I2C bus number" diff --git a/board/phytec/common/k3/Kconfig b/board/phytec/common/k3/Kconfig index 282f4b79742..4bbe1a5ec3c 100644 --- a/board/phytec/common/k3/Kconfig +++ b/board/phytec/common/k3/Kconfig @@ -1,5 +1,5 @@ config PHYTEC_K3_DDR_PATCH bool "Patch DDR timings on PHYTEC K3 SoMs" help - Allow to override default DDR timings prior to - DDRSS driver probing. + Allow to override default DDR timings prior to + DDRSS driver probing. diff --git a/board/phytec/phycore_am62ax/Kconfig b/board/phytec/phycore_am62ax/Kconfig index 516dc8e2020..e7943c51dbc 100644 --- a/board/phytec/phycore_am62ax/Kconfig +++ b/board/phytec/phycore_am62ax/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "phycore_am62ax" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am62ax" @@ -24,7 +24,7 @@ config SYS_BOARD default "phycore_am62ax" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am62ax" diff --git a/board/phytec/phycore_am62x/Kconfig b/board/phytec/phycore_am62x/Kconfig index ecee5873c0c..feacc3d6d40 100644 --- a/board/phytec/phycore_am62x/Kconfig +++ b/board/phytec/phycore_am62x/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "phycore_am62x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am62x" @@ -24,7 +24,7 @@ config SYS_BOARD default "phycore_am62x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am62x" @@ -38,31 +38,31 @@ source "board/phytec/common/k3/Kconfig" endif config PHYCORE_AM62X_RAM_SIZE_FIX - bool "Set phyCORE-AM62x RAM size fix instead of detecting" - default false - help - RAM size is automatic being detected with the help of - the EEPROM introspection data. Set RAM size to a fix value - instead. + bool "Set phyCORE-AM62x RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. choice - prompt "phyCORE-AM62x RAM size" - depends on PHYCORE_AM62X_RAM_SIZE_FIX - default PHYCORE_AM62X_RAM_SIZE_2GB + prompt "phyCORE-AM62x RAM size" + depends on PHYCORE_AM62X_RAM_SIZE_FIX + default PHYCORE_AM62X_RAM_SIZE_2GB config PHYCORE_AM62X_RAM_SIZE_1GB - bool "1GB RAM" - help - Set RAM size fix to 1GB for phyCORE-AM62x. + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-AM62x. config PHYCORE_AM62X_RAM_SIZE_2GB - bool "2GB RAM" - help - Set RAM size fix to 2GB for phyCORE-AM62x. + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-AM62x. config PHYCORE_AM62X_RAM_SIZE_4GB - bool "4GB RAM" - help - Set RAM size fix to 4GB for phyCORE-AM62x. + bool "4GB RAM" + help + Set RAM size fix to 4GB for phyCORE-AM62x. endchoice diff --git a/board/phytec/phycore_am64x/Kconfig b/board/phytec/phycore_am64x/Kconfig index a709b71ba4d..a4d25b84b96 100644 --- a/board/phytec/phycore_am64x/Kconfig +++ b/board/phytec/phycore_am64x/Kconfig @@ -12,7 +12,7 @@ config SYS_BOARD default "phycore_am64x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am64x" @@ -27,7 +27,7 @@ config SYS_BOARD default "phycore_am64x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am64x" @@ -37,26 +37,26 @@ source "board/phytec/common/Kconfig" endif config PHYCORE_AM64X_RAM_SIZE_FIX - bool "Set phyCORE-AM64x RAM size fix instead of detecting" - default false - help - RAM size is automatic being detected with the help of - the EEPROM introspection data. Set RAM size to a fix value - instead. + bool "Set phyCORE-AM64x RAM size fix instead of detecting" + default false + help + RAM size is automatic being detected with the help of + the EEPROM introspection data. Set RAM size to a fix value + instead. choice - prompt "phyCORE-AM64x RAM size" - depends on PHYCORE_AM64X_RAM_SIZE_FIX - default PHYCORE_AM64X_RAM_SIZE_2GB + prompt "phyCORE-AM64x RAM size" + depends on PHYCORE_AM64X_RAM_SIZE_FIX + default PHYCORE_AM64X_RAM_SIZE_2GB config PHYCORE_AM64X_RAM_SIZE_1GB - bool "1GB RAM" - help - Set RAM size fix to 1GB for phyCORE-AM64x. + bool "1GB RAM" + help + Set RAM size fix to 1GB for phyCORE-AM64x. config PHYCORE_AM64X_RAM_SIZE_2GB - bool "2GB RAM" - help - Set RAM size fix to 2GB for phyCORE-AM64x. + bool "2GB RAM" + help + Set RAM size fix to 2GB for phyCORE-AM64x. endchoice diff --git a/board/phytec/phycore_am68x/Kconfig b/board/phytec/phycore_am68x/Kconfig index 37912fb4ed3..d82cdaf819b 100644 --- a/board/phytec/phycore_am68x/Kconfig +++ b/board/phytec/phycore_am68x/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "phycore_am68x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am68x" @@ -27,7 +27,7 @@ config SYS_BOARD default "phycore_am68x" config SYS_VENDOR - default "phytec" + default "phytec" config SYS_CONFIG_NAME default "phycore_am68x" diff --git a/board/qualcomm/qcom-phone.config b/board/qualcomm/qcom-phone.config index d24094eefdd..1387aa1dfa2 100644 --- a/board/qualcomm/qcom-phone.config +++ b/board/qualcomm/qcom-phone.config @@ -13,6 +13,7 @@ CONFIG_FASTBOOT_BUF_ADDR=0x1A000000 CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_USB_FUNCTION_ACM=y CONFIG_CMD_UMS_ABORT_KEYED=y +CONFIG_CMD_FASTBOOT_ABORT_KEYED=y # Record all console output and let it be dumped via fastboot CONFIG_CONSOLE_RECORD=y diff --git a/board/qualcomm/qcom-phone.env b/board/qualcomm/qcom-phone.env index 42f58c3bac6..5eaa2ceada8 100644 --- a/board/qualcomm/qcom-phone.env +++ b/board/qualcomm/qcom-phone.env @@ -32,7 +32,7 @@ menucmd=setenv bootcmd run menucmd; bootmenu -1 bootmenu_0=Boot=bootefi bootmgr; pause bootmenu_1=Enable serial console gadget=run serial_gadget bootmenu_2=Enable USB mass storage=echo "Press any key to exit UMS mode"; ums 0 scsi 0 -bootmenu_3=Enable fastboot mode=run fastboot +bootmenu_3=Enable fastboot mode=echo "Press any key to exit fastboot mode"; run fastboot # Disabling bootretry means we'll just drop the shell bootmenu_4=Drop to shell=setenv bootretry -1 bootmenu_5=Reset device=reset diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c index f06df824019..b2f6087a943 100644 --- a/board/renesas/common/gen5-cm33.c +++ b/board/renesas/common/gen5-cm33.c @@ -21,9 +21,6 @@ DECLARE_GLOBAL_DATA_PTR; -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - #define PKC_PROT_LOCK 0xa5a5a500 #define PKC_PROT_UNLOCK 0xa5a5a501 diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS index 7e17a6a987a..3e2d864901f 100644 --- a/board/rockchip/evb_rk3568/MAINTAINERS +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -1,9 +1,19 @@ +9TRIPOD-X3568-V4 +M: Coia Prant <[email protected]> +S: Maintained +F: configs/9tripod-x3568-v4-rk3568_defconfig + BANANAPI-BPI-R2-PRO M: Frank Wunderlich <[email protected]> S: Maintained F: configs/bpi-r2-pro-rk3568_defconfig F: arch/arm/dts/rk3568-bpi-r2-pro* +EASEPI-R1 +M: Liangbin Lian <[email protected]> +S: Maintained +F: configs/easepi-r1-rk3568_defconfig + EVB-RK3568 M: Joseph Chen <[email protected]> S: Maintained diff --git a/board/samsung/axy17lte/Kconfig b/board/samsung/axy17lte/Kconfig index 64a4ffa7e67..d98da0ecab5 100644 --- a/board/samsung/axy17lte/Kconfig +++ b/board/samsung/axy17lte/Kconfig @@ -11,8 +11,8 @@ config SYS_CONFIG_NAME default "exynos78x0-common" config EXYNOS7880 - bool "Exynos 7880 SOC support" - default y + bool "Exynos 7880 SOC support" + default y endif if TARGET_A7Y17LTE @@ -28,8 +28,8 @@ config SYS_CONFIG_NAME default "exynos78x0-common" config EXYNOS7880 - bool "Exynos 7880 SOC support" - default y + bool "Exynos 7880 SOC support" + default y endif if TARGET_A3Y17LTE @@ -45,6 +45,6 @@ config SYS_CONFIG_NAME default "exynos78x0-common" config EXYNOS7870 - bool "Exynos 7870 SOC support" - default y + bool "Exynos 7870 SOC support" + default y endif diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig index 9d45c4239be..3f2e75b03fe 100644 --- a/board/siemens/draco/Kconfig +++ b/board/siemens/draco/Kconfig @@ -33,10 +33,10 @@ endif if TARGET_ETAMIN config SYS_BOARD - default "draco" + default "draco" config SYS_VENDOR - default "siemens" + default "siemens" config SYS_SOC default "am33xx" diff --git a/board/socionext/developerbox/Kconfig b/board/socionext/developerbox/Kconfig index c181d26a44a..1b1c9181bad 100644 --- a/board/socionext/developerbox/Kconfig +++ b/board/socionext/developerbox/Kconfig @@ -11,10 +11,10 @@ config TARGET_DEVELOPERBOX select SYS_DISABLE_DCACHE_OPS select OF_BOARD_SETUP help - Choose this option if you build the U-Boot for the DeveloperBox - 96boards Enterprise Edition. - This board will booted from SCP firmware and it enables SMMU, thus - the dcache is updated automatically when DMA operation is executed. + Choose this option if you build the U-Boot for the DeveloperBox + 96boards Enterprise Edition. + This board will booted from SCP firmware and it enables SMMU, thus + the dcache is updated automatically when DMA operation is executed. endchoice config SYS_SOC diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig index 3d00f3f3331..aafbffbf6db 100644 --- a/board/st/common/Kconfig +++ b/board/st/common/Kconfig @@ -14,7 +14,7 @@ config DFU_ALT_RAM0 This defines the partitions of ram used to build dfu dynamically. config TYPEC_STUSB160X - tristate "STMicroelectronics STUSB160X Type-C controller driver" + bool "STMicroelectronics STUSB160X Type-C controller driver" depends on DM_I2C help Say Y if your system has STMicroelectronics STUSB160X Type-C port diff --git a/board/sysam/amcore/Kconfig b/board/sysam/amcore/Kconfig index b5c81dda237..7efd857dc32 100644 --- a/board/sysam/amcore/Kconfig +++ b/board/sysam/amcore/Kconfig @@ -4,13 +4,13 @@ config SYS_CPU default "mcf530x" config SYS_BOARD - default "amcore" + default "amcore" config SYS_VENDOR - default "sysam" + default "sysam" config SYS_CONFIG_NAME - default "amcore" + default "amcore" endif diff --git a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c index 3f484646701..5177aa9d6e8 100644 --- a/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c +++ b/board/theobroma-systems/jaguar_rk3588/jaguar_rk3588.c @@ -54,6 +54,8 @@ int rockchip_early_misc_init_r(void) #define GPIO0B7_PU_EN BIT(15) +#define M2_NVME_PERSTN 24 /* GPIO0_D0, PERSTN signal to the M.2 NVMe slot */ + void spl_board_init(void) { /* @@ -67,6 +69,24 @@ void spl_board_init(void) * pull-up. */ struct rk3588_pmu2_ioc * const ioc = (void *)PMU2_IOC_BASE; + int ret; + /* TODO: once we have a U-Boot TPL, move this to tpl_board_init() */ rk_setreg(&ioc->gpio0b_p, GPIO0B7_PU_EN); + + /* + * Set the M.2 NVMe slot PERSTN to a defined low + * state as early as possible + */ + ret = gpio_request(M2_NVME_PERSTN, "M2_NVME_PERSTN"); + if (ret) { + log_err("M2_NVME_PERSTN: gpio request failed: %d\n", ret); + return; + } + + ret = gpio_direction_output(M2_NVME_PERSTN, 0); + if (ret) { + log_err("M2_NVME_PERSTN: gpio direction set failed: %d\n", ret); + return; + } } diff --git a/board/ti/am62ax/Kconfig b/board/ti/am62ax/Kconfig index 51e7b3e0eab..a80ea9149b1 100644 --- a/board/ti/am62ax/Kconfig +++ b/board/ti/am62ax/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "am62ax" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am62ax_evm" diff --git a/board/ti/am62px/Kconfig b/board/ti/am62px/Kconfig index 9d95ffd9b29..1011b89d75f 100644 --- a/board/ti/am62px/Kconfig +++ b/board/ti/am62px/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "am62px" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am62px_evm" diff --git a/board/ti/am62x/Kconfig b/board/ti/am62x/Kconfig index 610dacfdc08..eb54154d1ce 100644 --- a/board/ti/am62x/Kconfig +++ b/board/ti/am62x/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "am62x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am62x_evm" @@ -24,7 +24,7 @@ config SYS_BOARD default "am62x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am62x_evm" diff --git a/board/ti/am64x/Kconfig b/board/ti/am64x/Kconfig index b873476a9d5..c727b7f8c16 100644 --- a/board/ti/am64x/Kconfig +++ b/board/ti/am64x/Kconfig @@ -8,7 +8,7 @@ config SYS_BOARD default "am64x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am64x_evm" @@ -23,7 +23,7 @@ config SYS_BOARD default "am64x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am64x_evm" diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig index eb47a25c70a..fe3fa13dc4b 100644 --- a/board/ti/am65x/Kconfig +++ b/board/ti/am65x/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "am65x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am65x_evm" @@ -24,7 +24,7 @@ config SYS_BOARD default "am65x" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "am65x_evm" diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig index 149909093b3..6762d08d400 100644 --- a/board/ti/common/Kconfig +++ b/board/ti/common/Kconfig @@ -1,8 +1,8 @@ config TI_I2C_BOARD_DETECT bool "Support for Board detection for TI platforms" help - Support for detection board information on Texas Instrument's - Evaluation Boards which have I2C based EEPROM detection + Support for detection board information on Texas Instrument's + Evaluation Boards which have I2C based EEPROM detection config EEPROM_BUS_ADDRESS int "Board EEPROM's I2C bus address" diff --git a/board/ti/j7200/Kconfig b/board/ti/j7200/Kconfig index 093d23e7bf8..38edbe12968 100644 --- a/board/ti/j7200/Kconfig +++ b/board/ti/j7200/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "j7200" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721e_evm" @@ -27,7 +27,7 @@ config SYS_BOARD default "j7200" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721e_evm" diff --git a/board/ti/j721e/Kconfig b/board/ti/j721e/Kconfig index 7c7e23988d8..d85056e65bb 100644 --- a/board/ti/j721e/Kconfig +++ b/board/ti/j721e/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "j721e" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721e_evm" @@ -27,7 +27,7 @@ config SYS_BOARD default "j721e" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721e_evm" diff --git a/board/ti/j721s2/Kconfig b/board/ti/j721s2/Kconfig index 40853a8fd66..34a3e6ef187 100644 --- a/board/ti/j721s2/Kconfig +++ b/board/ti/j721s2/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "j721s2" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721s2_evm" @@ -27,7 +27,7 @@ config SYS_BOARD default "j721s2" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j721s2_evm" diff --git a/board/ti/j722s/Kconfig b/board/ti/j722s/Kconfig index 68c214e473b..e819ba2f554 100644 --- a/board/ti/j722s/Kconfig +++ b/board/ti/j722s/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "j722s" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j722s_evm" diff --git a/board/ti/j784s4/Kconfig b/board/ti/j784s4/Kconfig index de95ac575d7..40c4913aea1 100644 --- a/board/ti/j784s4/Kconfig +++ b/board/ti/j784s4/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "j784s4" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j784s4_evm" @@ -24,7 +24,7 @@ config SYS_BOARD default "j784s4" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j784s4_evm" @@ -42,7 +42,7 @@ config SYS_BOARD default "j784s4" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j784s4_evm" @@ -57,7 +57,7 @@ config SYS_BOARD default "j784s4" config SYS_VENDOR - default "ti" + default "ti" config SYS_CONFIG_NAME default "j784s4_evm" diff --git a/board/toradex/apalis_imx6/Kconfig b/board/toradex/apalis_imx6/Kconfig index c6ff387351c..fc4cbe3323c 100644 --- a/board/toradex/apalis_imx6/Kconfig +++ b/board/toradex/apalis_imx6/Kconfig @@ -35,7 +35,7 @@ config TDX_CMD_IMX_MFGR bool "Enable factory testing commands for Toradex iMX 6 modules" help This adds the commands - pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 + pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 If executed on already fused modules it doesn't change any fuse setting. default y @@ -43,11 +43,11 @@ config TDX_APALIS_IMX6_V1_0 bool "Apalis iMX6 V1.0 HW" help Apalis iMX6 V1.0 HW has a different pinout for the UART. - The UARTs must be used in DCE mode, RTS/CTS are swapped and - thus unusable on standard carrier boards. - This option configures DCE mode unconditionally. Whithout this - option the config block stating V1.0 HW selects DCE mode, - otherwise the UARTs are configuered in DTE mode. + The UARTs must be used in DCE mode, RTS/CTS are swapped and + thus unusable on standard carrier boards. + This option configures DCE mode unconditionally. Whithout this + option the config block stating V1.0 HW selects DCE mode, + otherwise the UARTs are configuered in DTE mode. source "board/toradex/common/Kconfig" diff --git a/board/toradex/aquila-am69/Kconfig b/board/toradex/aquila-am69/Kconfig index 6afa97e2c82..b44b9247603 100644 --- a/board/toradex/aquila-am69/Kconfig +++ b/board/toradex/aquila-am69/Kconfig @@ -9,7 +9,7 @@ config SYS_BOARD default "aquila-am69" config SYS_VENDOR - default "toradex" + default "toradex" config SYS_CONFIG_NAME default "aquila-am69" @@ -48,7 +48,7 @@ config SYS_BOARD default "aquila-am69" config SYS_VENDOR - default "toradex" + default "toradex" config SYS_CONFIG_NAME default "aquila-am69" diff --git a/board/toradex/aquila-imx95/Kconfig b/board/toradex/aquila-imx95/Kconfig new file mode 100644 index 00000000000..5936946e1af --- /dev/null +++ b/board/toradex/aquila-imx95/Kconfig @@ -0,0 +1,36 @@ +if TARGET_AQUILA_IMX95 + +config SYS_BOARD + default "aquila-imx95" + +config SYS_VENDOR + default "toradex" + +config SYS_CONFIG_NAME + default "aquila-imx95" + +config TDX_CFG_BLOCK + default y + +config TDX_CFG_BLOCK_2ND_ETHADDR + default y + +config TDX_CFG_BLOCK_DEV + default "0" + +# Toradex config block in eMMC, at the end of 1st "boot sector" +config TDX_CFG_BLOCK_OFFSET + default "-512" + +config TDX_CFG_BLOCK_PART + default "1" + +config TDX_HAVE_EEPROM_EXTRA + default y + +config TDX_HAVE_MMC + default y + +source "board/toradex/common/Kconfig" + +endif diff --git a/board/toradex/aquila-imx95/MAINTAINERS b/board/toradex/aquila-imx95/MAINTAINERS new file mode 100644 index 00000000000..d2a74a53f5e --- /dev/null +++ b/board/toradex/aquila-imx95/MAINTAINERS @@ -0,0 +1,11 @@ +Aquila iMX95 +F: arch/arm/dts/imx95-aquila.dtsi +F: arch/arm/dts/imx95-aquila-dev.dts +F: arch/arm/dts/imx95-aquila-dev-u-boot.dtsi +F: board/toradex/aquila-imx95/ +F: configs/aquila-imx95_defconfig +F: doc/board/toradex/aquila-imx95.rst +F: include/configs/aquila-imx95.h +M: Francesco Dolcini <[email protected]> +S: Maintained +W: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 diff --git a/board/toradex/aquila-imx95/Makefile b/board/toradex/aquila-imx95/Makefile new file mode 100644 index 00000000000..caaf09465c8 --- /dev/null +++ b/board/toradex/aquila-imx95/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (c) Toradex + +obj-y += aquila-imx95.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +endif diff --git a/board/toradex/aquila-imx95/aquila-imx95.c b/board/toradex/aquila-imx95/aquila-imx95.c new file mode 100644 index 00000000000..0c6473e4b3a --- /dev/null +++ b/board/toradex/aquila-imx95/aquila-imx95.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <fdt_support.h> +#include <init.h> + +#include "../common/tdx-cfg-block.h" + +int board_phys_sdram_size(phys_size_t *size) +{ + *size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE; + + return 0; +} + +#if IS_ENABLED(CONFIG_OF_LIBFDT) && IS_ENABLED(CONFIG_OF_BOARD_SETUP) +int ft_board_setup(void *blob, struct bd_info *bd) +{ + return ft_common_board_setup(blob, bd); +} +#endif diff --git a/board/toradex/aquila-imx95/aquila-imx95.env b/board/toradex/aquila-imx95/aquila-imx95.env new file mode 100644 index 00000000000..5ca6cb18aaa --- /dev/null +++ b/board/toradex/aquila-imx95/aquila-imx95.env @@ -0,0 +1,20 @@ +boot_scripts=boot.scr +boot_script_dhcp=boot.scr +boot_targets=mmc1 mmc0 dhcp +console=ttyLP2 +fdt_board=dev +fdt_addr=0x9c400000 +fdt_addr_r=0x9c400000 +kernel_addr_r=CONFIG_SYS_LOAD_ADDR +kernel_comp_addr_r=0x94400000 +kernel_comp_size=0x8000000 +ramdisk_addr_r=0x9c800000 +scriptaddr=0x9c600000 + +update_uboot= + askenv confirm Did you load flash.bin (y/N)?; + if test "$confirm" = y; then + setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt + ${blkcnt} / 0x200; mmc dev 0 1; mmc write ${loadaddr} 0x0 + ${blkcnt}; + fi diff --git a/board/toradex/aquila-imx95/spl.c b/board/toradex/aquila-imx95/spl.c new file mode 100644 index 00000000000..9f501c11c1d --- /dev/null +++ b/board/toradex/aquila-imx95/spl.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Copyright (c) Toradex */ + +#include <asm/arch/clock.h> +#include <asm/arch/mu.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> +#include <asm/mach-imx/ele_api.h> +#include <asm/sections.h> +#include <asm/global_data.h> +#include <clk.h> +#include <dm/uclass.h> +#include <hang.h> +#include <i2c.h> +#include <init.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int spl_board_boot_device(enum boot_device boot_dev_spl) +{ + switch (boot_dev_spl) { + case SD1_BOOT: + case MMC1_BOOT: + return BOOT_DEVICE_MMC1; + case SD2_BOOT: + case MMC2_BOOT: + return BOOT_DEVICE_MMC2; + case USB_BOOT: + return BOOT_DEVICE_BOARD; + default: + return BOOT_DEVICE_NONE; + } +} + +void spl_board_init(void) +{ + int ret; + + ret = ele_start_rng(); + if (ret) + printf("Fail to start RNG: %d\n", ret); +} + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + if (IS_ENABLED(CONFIG_SPL_RECOVER_DATA_SECTION)) + spl_save_restore_data(); + + timer_init(); + + /* Need dm_init() to run before any SCMI calls */ + spl_early_init(); + + /* Need to enable SCMI drivers and ELE driver before console */ + ret = imx9_probe_mu(); + if (ret) + hang(); /* MU not probed, nothing can be outputed, hang */ + + arch_cpu_init(); + + preloader_console_init(); + + debug("SOC: 0x%x\n", gd->arch.soc_rev); + debug("LC: 0x%x\n", gd->arch.lifecycle); + + get_reset_reason(true, false); + + board_init_r(NULL, 0); +} diff --git a/board/toradex/colibri_imx6/Kconfig b/board/toradex/colibri_imx6/Kconfig index d2ad1ce2a03..53d3469d439 100644 --- a/board/toradex/colibri_imx6/Kconfig +++ b/board/toradex/colibri_imx6/Kconfig @@ -35,7 +35,7 @@ config TDX_CMD_IMX_MFGR bool "Enable factory testing commands for Toradex iMX 6 modules" help This adds the commands - pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 + pf0100_otp_prog - Program the OTP fuses on the PMIC PF0100 If executed on already fused modules it doesn't change any fuse setting. default y diff --git a/board/toradex/verdin-am62p/Kconfig b/board/toradex/verdin-am62p/Kconfig index a65caf3c26d..4f5968bca2e 100644 --- a/board/toradex/verdin-am62p/Kconfig +++ b/board/toradex/verdin-am62p/Kconfig @@ -8,22 +8,22 @@ choice optional config TARGET_VERDIN_AM62P_A53 - bool "Toradex Verdin AM62P running on A53" - select ARM64 - select BINMAN - select OF_SYSTEM_SETUP - imply OF_UPSTREAM + bool "Toradex Verdin AM62P running on A53" + select ARM64 + select BINMAN + select OF_SYSTEM_SETUP + imply OF_UPSTREAM config TARGET_VERDIN_AM62P_R5 - bool "Toradex Verdin AM62P running on R5" - select CPU_V7R - select SYS_THUMB_BUILD - select K3_LOAD_SYSFW - select RAM - select SPL_RAM - select K3_DDRSS - select BINMAN - imply SYS_K3_SPL_ATF + bool "Toradex Verdin AM62P running on R5" + select CPU_V7R + select SYS_THUMB_BUILD + select K3_LOAD_SYSFW + select RAM + select SPL_RAM + select K3_DDRSS + select BINMAN + imply SYS_K3_SPL_ATF endchoice diff --git a/board/traverse/common/Kconfig b/board/traverse/common/Kconfig index d34832bd0d3..96b2566b697 100644 --- a/board/traverse/common/Kconfig +++ b/board/traverse/common/Kconfig @@ -2,5 +2,5 @@ config TEN64_CONTROLLER bool "Enable Ten64 board controller driver" depends on TARGET_TEN64 help - Support for the board microcontroller on the Traverse - Ten64 family of boards. + Support for the board microcontroller on the Traverse + Ten64 family of boards. diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index 5c3240da073..07fc8da1b71 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -67,7 +67,7 @@ config BOOT_SCRIPT_OFFSET default 0x7F80000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default 0 if TARGET_XILINX_MBV help - Specifies distro boot script offset in NAND/QSPI/NOR flash. + Specifies distro boot script offset in NAND/QSPI/NOR flash. config CMD_FRU bool "FRU information for product" diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 65b2a451ad7..ddac92660df 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -12,6 +12,7 @@ #include <env_internal.h> #include <log.h> #include <malloc.h> +#include <mmc.h> #include <spi.h> #include <time.h> #include <asm/cache.h> @@ -21,11 +22,9 @@ #include <asm/arch/sys_proto.h> #include <dm/device.h> #include <dm/uclass.h> -#include <zynqmp_firmware.h> #include <versalpl.h> #include "../common/board.h" -#include <linux/bitfield.h> #include <debug_uart.h> #include <generated/dt.h> @@ -49,92 +48,6 @@ int board_init(void) return 0; } -static u32 platform_id, platform_version; - -char *soc_name_decode(void) -{ - char *name, *platform_name; - - switch (platform_id) { - case VERSAL_NET_SPP: - platform_name = "ipp"; - break; - case VERSAL_NET_EMU: - platform_name = "emu"; - break; - case VERSAL_NET_QEMU: - platform_name = "qemu"; - break; - default: - return NULL; - } - - /* - * --rev. are 6 chars - * max platform name is qemu which is 4 chars - * platform version number are 1+1 - * Plus 1 char for \n - */ - name = calloc(1, strlen(CONFIG_SYS_BOARD) + 13); - if (!name) - return NULL; - - sprintf(name, "%s-%s-rev%d.%d", CONFIG_SYS_BOARD, - platform_name, platform_version / 10, - platform_version % 10); - - return name; -} - -bool soc_detection(void) -{ - u32 version, ps_version; - - version = readl(PMC_TAP_VERSION); - platform_id = FIELD_GET(PLATFORM_MASK, version); - ps_version = FIELD_GET(PS_VERSION_MASK, version); - - debug("idcode %x, version %x, usercode %x\n", - readl(PMC_TAP_IDCODE), version, - readl(PMC_TAP_USERCODE)); - - debug("pmc_ver %lx, ps version %x, rtl version %lx\n", - FIELD_GET(PMC_VERSION_MASK, version), - ps_version, - FIELD_GET(RTL_VERSION_MASK, version)); - - platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); - - if (platform_id == VERSAL_NET_SPP || - platform_id == VERSAL_NET_EMU) { - if (ps_version == PS_VERSION_PRODUCTION) { - /* - * ES1 version ends at 1.9 version where there was +9 - * used because of IPP/SPP conversion. Production - * version have platform_version started from 0 again - * that's why adding +20 to continue with the same line. - * It means the last ES1 version ends at 1.9 version and - * new PRODUCTION line starts at 2.0. - */ - platform_version += 20; - } else { - /* - * 9 is diff for - * 0 means 0.9 version - * 1 means 1.0 version - * 2 means 1.1 version - * etc, - */ - platform_version += 9; - } - } - - debug("Platform id: %d version: %d.%d\n", platform_id, - platform_version / 10, platform_version % 10); - - return true; -} - int board_early_init_f(void) { if (IS_ENABLED(CONFIG_DEBUG_UART)) { @@ -148,118 +61,103 @@ int board_early_init_f(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - debug("iou_switch ctrl div0 %x\n", - readl(&crlapb_base->iou_switch_ctrl)); - - writel(IOU_SWITCH_CTRL_CLKACT_BIT | - (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), - &crlapb_base->iou_switch_ctrl); - - /* Global timer init - Program time stamp reference clk */ - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - debug("ref ctrl 0x%x\n", - readl(&crlapb_base->timestamp_ref_ctrl)); - - /* Clear reset of timestamp reg */ - writel(0, &crlapb_base->rst_timestamp); - - /* - * Program freq register in System counter and - * enable system counter. - */ - writel(CONFIG_COUNTER_FREQUENCY, - &iou_scntr_secure->base_frequency_id_register); - - debug("counter val 0x%x\n", - readl(&iou_scntr_secure->base_frequency_id_register)); - - writel(IOU_SCNTRS_CONTROL_EN, - &iou_scntr_secure->counter_control_register); - - debug("scntrs control 0x%x\n", - readl(&iou_scntr_secure->counter_control_register)); - debug("timer 0x%llx\n", get_ticks()); - debug("timer 0x%llx\n", get_ticks()); + versal_net_timer_setup(); return 0; } -static u8 versal_net_get_bootmode(void) +static int spi_get_bootseq(u8 bootmode, const char **modename) { - u8 bootmode; - u32 reg = 0; + struct udevice *dev; + const char *name; + int bootseq; - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) { - reg = zynqmp_pm_get_bootmode_reg(); - } else { - reg = readl(&crp_base->boot_mode_usr); + switch (bootmode) { + case QSPI_MODE_24BIT: + if (modename) + *modename = "QSPI_MODE_24\n"; + name = "spi@f1030000"; + break; + case QSPI_MODE_32BIT: + if (modename) + *modename = "QSPI_MODE_32\n"; + name = "spi@f1030000"; + break; + case OSPI_MODE: + if (modename) + *modename = "OSPI_MODE\n"; + name = "spi@f1010000"; + break; + default: + return -1; } - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; + if (uclass_get_device_by_name(UCLASS_SPI, name, &dev)) { + debug("SPI driver for %s is not present\n", name); + return -1; + } - bootmode = reg & BOOT_MODES_MASK; + bootseq = dev_seq(dev); + debug("bootseq %d\n", bootseq); - return bootmode; + return bootseq; } int spi_get_env_dev(void) { + return spi_get_bootseq(versal_net_get_bootmode(), NULL); +} + +static int mmc_get_bootseq(u8 bootmode, const char **modename) +{ struct udevice *dev; - int bootseq = -1; + const char *name; - switch (versal_net_get_bootmode()) { - case QSPI_MODE_24BIT: - puts("QSPI_MODE_24\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - bootseq = dev_seq(dev); + switch (bootmode) { + case SD_MODE: + if (modename) + *modename = "SD_MODE\n"; + name = "mmc@f1040000"; break; - case QSPI_MODE_32BIT: - puts("QSPI_MODE_32\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - bootseq = dev_seq(dev); + case EMMC_MODE: + if (modename) + *modename = "EMMC_MODE\n"; + name = "mmc@f1050000"; break; - case OSPI_MODE: - puts("OSPI_MODE\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1010000", &dev)) { - debug("OSPI driver for OSPI device is not present\n"); - break; - } - bootseq = dev_seq(dev); + case SD_MODE1: + case SD1_LSHFT_MODE: + if (modename) + *modename = "SD_MODE1\n"; + name = "mmc@f1050000"; break; default: - break; + return -1; } - debug("bootseq %d\n", bootseq); - return bootseq; + if (uclass_get_device_by_name(UCLASS_MMC, name, &dev)) { + debug("MMC driver for %s is not present\n", name); + return -1; + } + + return dev_seq(dev); +} + +int mmc_get_env_dev(void) +{ + return mmc_get_bootseq(versal_net_get_bootmode(), NULL); } static int boot_targets_setup(void) { u8 bootmode; - struct udevice *dev; int bootseq = -1; int bootseq_len = 0; int env_targets_len = 0; const char *mode = NULL; + const char *modename = NULL; char *new_targets; char *env_targets; @@ -276,69 +174,28 @@ static int boot_targets_setup(void) mode = "jtag pxe dhcp"; break; case QSPI_MODE_24BIT: - puts("QSPI_MODE_24\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - mode = "xspi"; - bootseq = dev_seq(dev); - break; case QSPI_MODE_32BIT: - puts("QSPI_MODE_32\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1030000", &dev)) { - debug("QSPI driver for QSPI device is not present\n"); - break; - } - mode = "xspi"; - bootseq = dev_seq(dev); - break; case OSPI_MODE: - puts("OSPI_MODE\n"); - if (uclass_get_device_by_name(UCLASS_SPI, - "spi@f1010000", &dev)) { - debug("OSPI driver for OSPI device is not present\n"); - break; - } - mode = "xspi"; - bootseq = dev_seq(dev); - break; - case EMMC_MODE: - puts("EMMC_MODE\n"); - mode = "mmc"; - bootseq = dev_seq(dev); + bootseq = spi_get_bootseq(bootmode, &modename); + if (modename) + puts(modename); + if (bootseq >= 0) + mode = "xspi"; break; case SELECTMAP_MODE: puts("SELECTMAP_MODE\n"); break; - case SD_MODE: - puts("SD_MODE\n"); - if (uclass_get_device_by_name(UCLASS_MMC, - "mmc@f1040000", &dev)) { - debug("SD0 driver for SD0 device is not present\n"); - break; - } - debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev)); - - mode = "mmc"; - bootseq = dev_seq(dev); - break; case SD1_LSHFT_MODE: puts("LVL_SHFT_"); fallthrough; + case SD_MODE: + case EMMC_MODE: case SD_MODE1: - puts("SD_MODE1\n"); - if (uclass_get_device_by_name(UCLASS_MMC, - "mmc@f1050000", &dev)) { - debug("SD1 driver for SD1 device is not present\n"); - break; - } - debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev)); - - mode = "mmc"; - bootseq = dev_seq(dev); + bootseq = mmc_get_bootseq(bootmode, &modename); + if (modename) + puts(modename); + if (bootseq >= 0) + mode = "mmc"; break; default: printf("Invalid Boot Mode:0x%x\n", bootmode); diff --git a/board/xilinx/versal/board.c b/board/xilinx/versal/board.c index 8666f2ceff4..0537517b1b2 100644 --- a/board/xilinx/versal/board.c +++ b/board/xilinx/versal/board.c @@ -28,7 +28,6 @@ #include <dm/device.h> #include <dm/uclass.h> #include <versalpl.h> -#include <zynqmp_firmware.h> #include "../common/board.h" DECLARE_GLOBAL_DATA_PTR; @@ -40,40 +39,15 @@ static xilinx_desc versalpl = { }; #endif -static u8 versal_get_bootmode(void) -{ - u8 bootmode; - u32 reg = 0; - - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) { - reg = zynqmp_pm_get_bootmode_reg(); - } else { - reg = readl(&crp_base->boot_mode_usr); - } - - if (reg >> BOOT_MODE_ALT_SHIFT) - reg >>= BOOT_MODE_ALT_SHIFT; - - bootmode = reg & BOOT_MODES_MASK; - - return bootmode; -} - static u32 versal_multi_boot(void) { u8 bootmode = versal_get_bootmode(); - u32 reg = 0; /* Mostly workaround for QEMU CI pipeline */ if (bootmode == JTAG_MODE) return 0; - if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE) && current_el() != 3) - reg = zynqmp_pm_get_pmc_multi_boot_reg(); - else - reg = readl(PMC_MULTI_BOOT_REG); - - return reg & PMC_MULTI_BOOT_MASK; + return versal_pmc_multi_boot(); } int board_init(void) @@ -94,46 +68,10 @@ int board_init(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - debug("iou_switch ctrl div0 %x\n", - readl(&crlapb_base->iou_switch_ctrl)); - - writel(IOU_SWITCH_CTRL_CLKACT_BIT | - (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT), - &crlapb_base->iou_switch_ctrl); - - /* Global timer init - Program time stamp reference clk */ - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT; - writel(val, &crlapb_base->timestamp_ref_ctrl); - - debug("ref ctrl 0x%x\n", - readl(&crlapb_base->timestamp_ref_ctrl)); - - /* Clear reset of timestamp reg */ - writel(0, &crlapb_base->rst_timestamp); - - /* - * Program freq register in System counter and - * enable system counter. - */ - writel(CONFIG_COUNTER_FREQUENCY, - &iou_scntr_secure->base_frequency_id_register); - - debug("counter val 0x%x\n", - readl(&iou_scntr_secure->base_frequency_id_register)); - - writel(IOU_SCNTRS_CONTROL_EN, - &iou_scntr_secure->counter_control_register); - - debug("scntrs control 0x%x\n", - readl(&iou_scntr_secure->counter_control_register)); - debug("timer 0x%llx\n", get_ticks()); - debug("timer 0x%llx\n", get_ticks()); + versal_timer_setup(); return 0; } diff --git a/board/xilinx/zynqmp/zynqmp.c b/board/xilinx/zynqmp/zynqmp.c index a12c039d8c9..5d13881f3ec 100644 --- a/board/xilinx/zynqmp/zynqmp.c +++ b/board/xilinx/zynqmp/zynqmp.c @@ -24,7 +24,6 @@ #include <malloc.h> #include <memalign.h> #include <wdt.h> -#include <asm/arch/clk.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> #include <asm/arch/psu_init_gpl.h> @@ -214,26 +213,11 @@ int board_init(void) int board_early_init_r(void) { - u32 val; - if (current_el() != 3) return 0; - val = readl(&crlapb_base->timestamp_ref_ctrl); - val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - - if (!val) { - val = readl(&crlapb_base->timestamp_ref_ctrl); - val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT; - writel(val, &crlapb_base->timestamp_ref_ctrl); + zynqmp_timer_setup(); - /* Program freq register in System counter */ - writel(zynqmp_get_system_timer_freq(), - &iou_scntr_secure->base_frequency_id_register); - /* And enable system counter */ - writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN, - &iou_scntr_secure->counter_control_register); - } return 0; } diff --git a/boot/Kconfig b/boot/Kconfig index e6927d60b7b..8e468c56176 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -686,9 +686,9 @@ config BOOTMETH_QFW depends on QFW default y help - Use QEMU parameters -kernel, -initrd, -append to determine the kernel, - initial RAM disk, and kernel command line parameters to boot an - operating system. U-Boot's control device-tree is passed to the kernel. + Use QEMU parameters -kernel, -initrd, -append to determine the kernel, + initial RAM disk, and kernel command line parameters to boot an + operating system. U-Boot's control device-tree is passed to the kernel. config BOOTMETH_VBE bool "Bootdev support for Verified Boot for Embedded" @@ -1084,7 +1084,7 @@ config MEASURED_BOOT to use some attestation tools on your system. if MEASURED_BOOT - config MEASURE_DEVICETREE +config MEASURE_DEVICETREE bool "Measure the devicetree image" default y if MEASURED_BOOT help @@ -1093,7 +1093,7 @@ if MEASURED_BOOT Therefore, it should not be measured into the TPM. In that case, disable the measurement here. - config MEASURE_IGNORE_LOG +config MEASURE_IGNORE_LOG bool "Ignore the existing event log" help On platforms that use an event log memory region that persists diff --git a/boot/bootdev-uclass.c b/boot/bootdev-uclass.c index 657804949f8..55e1a6c4e02 100644 --- a/boot/bootdev-uclass.c +++ b/boot/bootdev-uclass.c @@ -669,8 +669,6 @@ int bootdev_next_prio(struct bootflow_iter *iter, struct udevice **devp) BOOTFLOWIF_SHOW); log_debug("- bootdev_hunt_prio() ret %d\n", ret); - if (ret) - return log_msg_ret("hun", ret); } } else { ret = device_probe(dev); diff --git a/boot/bootm.c b/boot/bootm.c index 4c260a5f5ce..803d6406be4 100644 --- a/boot/bootm.c +++ b/boot/bootm.c @@ -330,6 +330,10 @@ static int bootm_find_os(const char *cmd_name, const char *addr_fit) images.os.type = image_get_type(os_hdr); images.os.comp = image_get_comp(os_hdr); images.os.os = image_get_os(os_hdr); + if (images.os.os >= IH_OS_COUNT) { + printf("Unsupported OS type %d\n", images.os.os); + return 1; + } images.os.end = image_get_image_end(os_hdr); images.os.load = image_get_load(os_hdr); @@ -371,11 +375,17 @@ static int bootm_find_os(const char *cmd_name, const char *addr_fit) images.os.end = fit_get_end(images.fit_hdr_os); if (fit_image_get_load(images.fit_hdr_os, images.fit_noffset_os, - &images.os.load)) { + &images.os.load) && + images.os.type != IH_TYPE_KERNEL_NOLOAD) { puts("Can't get image load address!\n"); bootstage_error(BOOTSTAGE_ID_FIT_LOADADDR); return 1; } + if (images.os.load && images.os.type == IH_TYPE_KERNEL_NOLOAD) { + puts("WARNING: load address set for kernel_noload image, ignoring\n"); + images.os.load = 0; + } + break; #endif #ifdef CONFIG_ANDROID_BOOT_IMAGE @@ -423,7 +433,7 @@ static int bootm_find_os(const char *cmd_name, const char *addr_fit) ret = fit_image_get_entry(images.fit_hdr_os, images.fit_noffset_os, &images.ep); - if (ret) { + if (ret && images.os.type != IH_TYPE_KERNEL_NOLOAD) { puts("Can't get entry point property!\n"); return 1; } @@ -618,7 +628,7 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) ulong image_start = os.image_start; ulong image_len = os.image_len; ulong decomp_len = CONFIG_SYS_BOOTM_LEN; - ulong flush_start = ALIGN_DOWN(load, ARCH_DMA_MINALIGN); + ulong flush_start; bool no_overlap; void *load_buf, *image_buf; int err; @@ -663,6 +673,7 @@ static int bootm_load_os(struct bootm_headers *images, int boot_progress) /* We need the decompressed image size in the next steps */ images->os.image_len = load_end - load; + flush_start = ALIGN_DOWN(load, ARCH_DMA_MINALIGN); flush_cache(flush_start, ALIGN(load_end, ARCH_DMA_MINALIGN) - flush_start); debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, load_end); diff --git a/boot/bootm_os.c b/boot/bootm_os.c index 69aa577a2fc..ae20b555f5c 100644 --- a/boot/bootm_os.c +++ b/boot/bootm_os.c @@ -599,7 +599,5 @@ int boot_selected_os(int state, struct bootm_info *bmi, boot_os_fn *boot_fn) boot_os_fn *bootm_os_get_boot_func(int os) { - if (os < 0 || os >= ARRAY_SIZE(boot_os)) - return NULL; return boot_os[os]; } diff --git a/cmd/Kconfig b/cmd/Kconfig index 032e55e8127..a527b218949 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -881,12 +881,12 @@ config EEPROM_LAYOUT_VERSIONS via the -l option. config EEPROM_LAYOUT_HELP_STRING - string "Tells user what layout names are supported" - depends on EEPROM_LAYOUT_VERSIONS - default "<not defined>" - help - Help printed with the LAYOUT VERSIONS part of the 'eeprom' - command's help. + string "Tells user what layout names are supported" + depends on EEPROM_LAYOUT_VERSIONS + default "<not defined>" + help + Help printed with the LAYOUT VERSIONS part of the 'eeprom' + command's help. config SYS_I2C_EEPROM_BUS int "I2C bus of the EEPROM device." @@ -967,14 +967,14 @@ config CMD_MEMORY default y help Memory commands. - md - memory display - mm - memory modify (auto-incrementing address) - nm - memory modify (constant address) - mw - memory write (fill) - cp - memory copy - cmp - memory compare - base - print or set address offset - loop - initialize loop on address range + md - memory display + mm - memory modify (auto-incrementing address) + nm - memory modify (constant address) + mw - memory write (fill) + cp - memory copy + cmp - memory compare + base - print or set address offset + loop - initialize loop on address range config CMD_MEM_SEARCH bool "ms - Memory search" @@ -1115,9 +1115,9 @@ config CMD_ARMFFA help Provides a test command for the FF-A support supported options: - - Listing the partition(s) info - - Sending a data pattern to the specified partition - - Displaying the arm_ffa device info + - Listing the partition(s) info + - Sending a data pattern to the specified partition + - Displaying the arm_ffa device info config CMD_ARMFLASH bool "armflash" @@ -1208,15 +1208,22 @@ config CMD_FASTBOOT See doc/android/fastboot.rst for more information. +config CMD_FASTBOOT_ABORT_KEYED + bool "fastboot abort with any key" + depends on CMD_FASTBOOT && USB_FUNCTION_FASTBOOT + help + Allow interruption of USB fastboot mode by any key presses, + rather than just Ctrl-c. + config CMD_FLASH bool "flinfo, erase, protect" default y depends on FLASH_CFI_DRIVER || MTD_NOR_FLASH help NOR flash support. - flinfo - print FLASH memory information - erase - FLASH memory - protect - enable or disable FLASH write protection + flinfo - print FLASH memory information + erase - FLASH memory + protect - enable or disable FLASH write protection config CMD_FPGA bool "fpga" @@ -1392,6 +1399,7 @@ config CMD_IOTRACE config CMD_I2C bool "i2c" + depends on DM_I2C || SYS_I2C_LEGACY help I2C support. @@ -1548,7 +1556,7 @@ config CMD_OPTEE bool "Enable OP-TEE commands" depends on OPTEE help - OP-TEE commands support. + OP-TEE commands support. config CMD_MTD bool "mtd" @@ -1606,7 +1614,7 @@ config CMD_MUX bool "mux" depends on MULTIPLEXER help - List, select, and deselect mux controllers on the fly. + List, select, and deselect mux controllers on the fly. config CMD_NAND bool "nand" @@ -1814,7 +1822,7 @@ config CMD_UFS depends on UFS help "This provides commands to initialise and configure universal flash - subsystem devices" + subsystem devices" config CMD_USB bool "usb" @@ -1936,7 +1944,7 @@ config CMD_SETEXPR default y help Evaluate boolean and math expressions and store the result in an env - variable. + variable. Also supports loading the value at a memory location into a variable. If CONFIG_REGEX is enabled, setexpr also supports a gsub function. @@ -2642,9 +2650,9 @@ config CMD_PSTORE_ECC_SIZE depends on CMD_PSTORE default "0" help - if non-zero, the option enables ECC support and specifies ECC buffer - size in bytes (1 is a special value, means 16 bytes ECC), should be - identical to ramoops.ramoops_ecc parameter used by kernel + if non-zero, the option enables ECC support and specifies ECC buffer + size in bytes (1 is a special value, means 16 bytes ECC), should be + identical to ramoops.ramoops_ecc parameter used by kernel endif @@ -3156,15 +3164,15 @@ config CMD_AVB help Enables a "avb" command to perform verification of partitions using Android Verified Boot 2.0 functionality. It includes such subcommands: - avb init - initialize avb2 subsystem - avb read_rb - read rollback index - avb write_rb - write rollback index - avb is_unlocked - check device lock state - avb get_uuid - read and print uuid of a partition - avb read_part - read data from partition - avb read_part_hex - read data from partition and output to stdout - avb write_part - write data to partition - avb verify - run full verification chain + avb init - initialize avb2 subsystem + avb read_rb - read rollback index + avb write_rb - write rollback index + avb is_unlocked - check device lock state + avb get_uuid - read and print uuid of a partition + avb read_part - read data from partition + avb read_part_hex - read data from partition and output to stdout + avb write_part - write data to partition + avb verify - run full verification chain config CMD_STACKPROTECTOR_TEST bool "Test command for stack protector" @@ -3177,7 +3185,7 @@ config CMD_STACKPROTECTOR_TEST endmenu config CMD_UBI - tristate "Enable UBI - Unsorted block images commands" + bool "Enable UBI - Unsorted block images commands" select MTD_UBI help UBI is a software layer above MTD layer which admits use of LVM-like @@ -3194,10 +3202,10 @@ config CMD_UBI_RENAME depends on CMD_UBI help Enable a "ubi" command to rename ubi volume: - ubi rename <oldname> <newname> + ubi rename <oldname> <newname> config CMD_UBIFS - tristate "Enable UBIFS - Unsorted block images filesystem commands" + bool "Enable UBIFS - Unsorted block images filesystem commands" depends on CMD_UBI default y if CMD_UBI select LZO diff --git a/cmd/boot.c b/cmd/boot.c index 29cdf4a9a81..23496cafdf5 100644 --- a/cmd/boot.c +++ b/cmd/boot.c @@ -60,12 +60,6 @@ U_BOOT_CMD( reset, 2, 0, do_reset, "Perform RESET of the CPU", "- cold boot without level specifier\n" -#if IS_ENABLED(CONFIG_SYSRESET_CMD_RESET_ARGS) -// All options handled by sysreset drivers via their sysreset_ops.request_arg callback -#ifdef CONFIG_SYSRESET_QCOM_PSCI - "reset -edl - Boot to Emergency DownLoad mode\n" -#endif -#endif "reset -w - warm reset if implemented" ); diff --git a/cmd/clone.c b/cmd/clone.c index 1f3cff1836d..371f06d917a 100644 --- a/cmd/clone.c +++ b/cmd/clone.c @@ -97,7 +97,7 @@ read: write: ret = blk_dwrite(destdesc, destblk, towrite, buf + offset); if (ret < 0) { - printf("Dest write error @blk %ld\n", srcblk); + printf("Dest write error @blk %ld\n", destblk); goto exit; } wrcnt += ret * destbz; diff --git a/cmd/fastboot.c b/cmd/fastboot.c index e71f873527b..f3929f88dfa 100644 --- a/cmd/fastboot.c +++ b/cmd/fastboot.c @@ -103,8 +103,15 @@ static int do_fastboot_usb(int argc, char *const argv[], while (1) { if (g_dnl_detach()) break; - if (ctrlc()) + if (IS_ENABLED(CONFIG_CMD_FASTBOOT_ABORT_KEYED)) { + if (tstc()) { + getchar(); + puts("\rOperation aborted.\n"); + break; + } + } else if (ctrlc()) { break; + } schedule(); dm_usb_gadget_handle_interrupts(udc); } diff --git a/cmd/host.c b/cmd/host.c index e03576b4d2d..47a59f5ff20 100644 --- a/cmd/host.c +++ b/cmd/host.c @@ -132,10 +132,7 @@ static int do_host_unbind(struct cmd_tbl *cmdtp, int flag, int argc, ret = device_unbind(dev); if (ret) { - printf("Cannot attach file\n"); - ret = device_unbind(dev); - if (ret) - printf("Cannot unbind device '%s'\n", dev->name); + printf("Cannot unbind device '%s'\n", dev->name); return CMD_RET_FAILURE; } diff --git a/cmd/ini.c b/cmd/ini.c index 96399017691..3fe86209c32 100644 --- a/cmd/ini.c +++ b/cmd/ini.c @@ -229,6 +229,7 @@ static int ini_handler(void *user, char *section, char *name, char *value) static int do_ini(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { const char *section; + const char *addr_str, *size_str; char *file_address; size_t file_size; @@ -236,10 +237,16 @@ static int do_ini(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return CMD_RET_USAGE; section = argv[1]; - file_address = (char *)hextoul(argc < 3 ? env_get("loadaddr") : argv[2], - NULL); - file_size = (size_t)hextoul(argc < 4 ? env_get("filesize") : argv[3], - NULL); + addr_str = argc < 3 ? env_get("loadaddr") : argv[2]; + size_str = argc < 4 ? env_get("filesize") : argv[3]; + + if (!addr_str || !size_str) { + printf("ini: loadaddr/filesize not set\n"); + return CMD_RET_USAGE; + } + + file_address = (char *)hextoul(addr_str, NULL); + file_size = (size_t)hextoul(size_str, NULL); return ini_parse(file_address, file_size, ini_handler, (void *)section); } diff --git a/cmd/lwip/ping.c b/cmd/lwip/ping.c index fc4cf7bde5f..98fa8e22bce 100644 --- a/cmd/lwip/ping.c +++ b/cmd/lwip/ping.c @@ -163,6 +163,7 @@ static int ping_loop(struct udevice *udev, const ip_addr_t *addr) int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { ip_addr_t addr; + int ret; if (argc < 2) return CMD_RET_USAGE; @@ -171,13 +172,15 @@ int do_ping(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return CMD_RET_USAGE; net_try_count = 1; -restart: - if (net_lwip_eth_start() < 0 || ping_loop(eth_get_dev(), &addr) < 0) { - if (net_start_again() == 0) - goto restart; - else - return CMD_RET_FAILURE; - } - return CMD_RET_SUCCESS; + do { + if (net_lwip_eth_start() == 0) { + ret = ping_loop(eth_get_dev(), &addr); + net_lwip_eth_stop(); + if (ret == 0) + return CMD_RET_SUCCESS; + } + } while (net_start_again() == 0); + + return CMD_RET_FAILURE; } diff --git a/cmd/lwip/sntp.c b/cmd/lwip/sntp.c index 608345c873b..5fa400b104a 100644 --- a/cmd/lwip/sntp.c +++ b/cmd/lwip/sntp.c @@ -101,6 +101,7 @@ int do_sntp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ip_addr_t *srvip; char *server; ip_addr_t ipaddr; + int ret = CMD_RET_FAILURE; switch (argc) { case 1: @@ -127,7 +128,12 @@ int do_sntp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return CMD_RET_FAILURE; if (sntp_loop(eth_get_dev(), srvip) < 0) - return CMD_RET_FAILURE; + goto out; + + ret = CMD_RET_SUCCESS; + +out: + net_lwip_eth_stop(); - return CMD_RET_SUCCESS; + return ret; } diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig index 43fe9ef2f08..17cf867dd91 100644 --- a/cmd/ti/Kconfig +++ b/cmd/ti/Kconfig @@ -4,24 +4,24 @@ config CMD_DDR3 bool "command for verifying DDR features" depends on ARCH_KEYSTONE || DRA7XX help - Support for testing ddr3 on TI platforms. This command - supports memory verification, memory comapre and ecc - verification if supported. + Support for testing ddr3 on TI platforms. This command + supports memory verification, memory comapre and ecc + verification if supported. config CMD_DDR4 bool "command for verifying DDRSS Inline ECC features" depends on ARCH_K3 help - Support for testing DDRSS on TI platforms. This command supports - memory verification, memory compare and inline ECC verification - if supported. + Support for testing DDRSS on TI platforms. This command supports + memory verification, memory compare and inline ECC verification + if supported. config CMD_PD bool "command for verifying power domains" depends on TI_POWER_DOMAIN help - Debug command for K3 power domains. For this to work, the - K3 power domain driver must be enabled for the u-boot; by - default it is only enabled for SPL. + Debug command for K3 power domains. For this to work, the + K3 power domain driver must be enabled for the u-boot; by + default it is only enabled for SPL. endmenu diff --git a/cmd/ubi.c b/cmd/ubi.c index 93de6f3aea2..2b206141a21 100644 --- a/cmd/ubi.c +++ b/cmd/ubi.c @@ -39,7 +39,7 @@ static struct ubi_device *ubi; #include <ubifs_uboot.h> #endif -static void display_volume_info(struct ubi_device *ubi) +static void display_volume_info(const struct ubi_device *ubi) { int i; @@ -50,7 +50,7 @@ static void display_volume_info(struct ubi_device *ubi) } } -static void display_ubi_info(struct ubi_device *ubi) +static void display_ubi_info(const struct ubi_device *ubi) { ubi_msg("MTD device name: \"%s\"", ubi->mtd->name); ubi_msg("MTD device size: %llu MiB", ubi->flash_size >> 20); @@ -149,12 +149,12 @@ static int ubi_list(const char *var, int numeric) return 0; } -static int ubi_check_volumename(const struct ubi_volume *vol, char *name) +static int ubi_check_volumename(const struct ubi_volume *vol, const char *name) { return strcmp(vol->name, name); } -static int ubi_check(char *name) +static int ubi_check(const char *name) { int i; @@ -172,7 +172,7 @@ static int ubi_check(char *name) static int verify_mkvol_req(const struct ubi_device *ubi, const struct ubi_mkvol_req *req) { - int n, err = EINVAL; + int n, err = -EINVAL; if (req->bytes < 0 || req->alignment < 0 || req->vol_type < 0 || req->name_len < 0) @@ -187,7 +187,7 @@ static int verify_mkvol_req(const struct ubi_device *ubi, if (req->bytes == 0) { printf("No space left in UBI device!\n"); - err = ENOMEM; + err = -ENOMEM; goto bad; } @@ -204,7 +204,7 @@ static int verify_mkvol_req(const struct ubi_device *ubi, if (req->name_len > UBI_VOL_NAME_MAX) { printf("Name too long!\n"); - err = ENAMETOOLONG; + err = -ENAMETOOLONG; goto bad; } @@ -213,8 +213,8 @@ bad: return err; } -static int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id, - bool skipcheck) +int ubi_create_vol(const char *volume, int64_t size, bool dynamic, int vol_id, + bool skipcheck) { struct ubi_mkvol_req req; int err; @@ -226,7 +226,11 @@ static int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id, req.vol_id = vol_id; req.alignment = 1; - req.bytes = size; + + if (size < 0) + req.bytes = ubi->avail_pebs * ubi->leb_size; + else + req.bytes = size; strcpy(req.name, volume); req.name_len = strlen(volume); @@ -241,13 +245,12 @@ static int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id, printf("verify_mkvol_req failed %d\n", err); return err; } - printf("Creating %s volume %s of size %lld\n", - dynamic ? "dynamic" : "static", volume, size); + /* Call real ubi create volume */ return ubi_create_volume(ubi, &req); } -static struct ubi_volume *ubi_find_volume(char *volume) +struct ubi_volume *ubi_find_volume(const char *volume) { struct ubi_volume *vol; int i; @@ -258,24 +261,26 @@ static struct ubi_volume *ubi_find_volume(char *volume) return vol; } - printf("Volume %s not found!\n", volume); return NULL; } -static int ubi_remove_vol(char *volume) +static struct ubi_volume *ubi_require_volume(const char *volume) { - int err, reserved_pebs, i; - struct ubi_volume *vol; + struct ubi_volume *vol = ubi_find_volume(volume); - vol = ubi_find_volume(volume); - if (vol == NULL) - return ENODEV; + if (!vol) + printf("Volume %s not found!\n", volume); + + return vol; +} - printf("Remove UBI volume %s (id %d)\n", vol->name, vol->vol_id); +static int __ubi_remove_vol(struct ubi_volume *vol) +{ + int err, reserved_pebs, i; if (ubi->ro_mode) { printf("It's read-only mode\n"); - err = EROFS; + err = -EROFS; goto out_err; } @@ -310,35 +315,40 @@ static int ubi_remove_vol(char *volume) return 0; out_err: - ubi_err(ubi, "cannot remove volume %s, error %d", volume, err); - if (err < 0) - err = -err; + ubi_err(ubi, "cannot remove volume %s, error %d", vol->name, err); return err; } -static int ubi_rename_vol(char *oldname, char *newname) +int ubi_remove_vol(const char *volume) +{ + struct ubi_volume *vol; + + vol = ubi_require_volume(volume); + if (!vol) + return -ENODEV; + + return __ubi_remove_vol(vol); +} + +static int ubi_rename_vol(const char *oldname, const char *newname) { struct ubi_volume *vol; struct ubi_rename_entry rename; struct ubi_volume_desc desc; struct list_head list; - vol = ubi_find_volume(oldname); - if (!vol) { - printf("%s: volume %s doesn't exist\n", __func__, oldname); - return ENODEV; - } + vol = ubi_require_volume(oldname); + if (!vol) + return -ENODEV; if (!ubi_check(newname)) { printf("%s: volume %s already exist\n", __func__, newname); - return EINVAL; + return -EINVAL; } - printf("Rename UBI volume %s to %s\n", oldname, newname); - if (ubi->ro_mode) { printf("%s: ubi device is in read-only mode\n", __func__); - return EROFS; + return -EROFS; } rename.new_name_len = strlen(newname); @@ -354,24 +364,25 @@ static int ubi_rename_vol(char *oldname, char *newname) return ubi_rename_volumes(ubi, &list); } -static int ubi_volume_continue_write(char *volume, void *buf, size_t size) +static int ubi_volume_continue_write(const char *volume, const void *buf, + size_t size) { int err; struct ubi_volume *vol; - vol = ubi_find_volume(volume); + vol = ubi_require_volume(volume); if (vol == NULL) - return ENODEV; + return -ENODEV; if (!vol->updating) { printf("UBI volume update was not initiated\n"); - return EINVAL; + return -EINVAL; } err = ubi_more_update_data(ubi, vol, buf, size); if (err < 0) { printf("Couldnt or partially wrote data\n"); - return -err; + return err; } if (err) { @@ -379,7 +390,7 @@ static int ubi_volume_continue_write(char *volume, void *buf, size_t size) err = ubi_check_volume(ubi, vol->vol_id); if (err < 0) - return -err; + return err; if (err) { ubi_warn(ubi, "volume %d on UBI device %d is corrupt", @@ -394,27 +405,27 @@ static int ubi_volume_continue_write(char *volume, void *buf, size_t size) return 0; } -int ubi_volume_begin_write(char *volume, void *buf, size_t size, - size_t full_size) +int ubi_volume_begin_write(const char *volume, const void *buf, size_t size, + size_t full_size) { int err; int rsvd_bytes; struct ubi_volume *vol; - vol = ubi_find_volume(volume); + vol = ubi_require_volume(volume); if (vol == NULL) - return ENODEV; + return -ENODEV; rsvd_bytes = vol->reserved_pebs * (ubi->leb_size - vol->data_pad); if (size > rsvd_bytes) { printf("size > volume size! Aborting!\n"); - return EINVAL; + return -EINVAL; } err = ubi_start_update(ubi, vol, full_size); if (err < 0) { printf("Cannot start volume update\n"); - return -err; + return err; } /* The volume is just wiped out */ @@ -424,8 +435,8 @@ int ubi_volume_begin_write(char *volume, void *buf, size_t size, return ubi_volume_continue_write(volume, buf, size); } -static int ubi_volume_offset_write(char *volume, void *buf, loff_t offset, - size_t size) +static int ubi_volume_offset_write(const char *volume, const void *buf, + loff_t offset, size_t size) { int len, tbuf_size, ret; u64 lnum; @@ -433,7 +444,7 @@ static int ubi_volume_offset_write(char *volume, void *buf, loff_t offset, loff_t off = offset; void *tbuf; - vol = ubi_find_volume(volume); + vol = ubi_require_volume(volume); if (!vol) return -ENODEV; @@ -487,7 +498,8 @@ exit: return ret; } -int ubi_volume_write(char *volume, void *buf, loff_t offset, size_t size) +int ubi_volume_write(const char *volume, const void *buf, loff_t offset, + size_t size) { int ret; @@ -503,36 +515,28 @@ int ubi_volume_write(char *volume, void *buf, loff_t offset, size_t size) return ret; } -int ubi_volume_read(char *volume, char *buf, loff_t offset, size_t size) +static int __ubi_volume_read(struct ubi_volume *vol, void *buf, loff_t offset, + size_t size) { int err, lnum, off, len, tbuf_size; void *tbuf; unsigned long long tmp; - struct ubi_volume *vol; loff_t offp = offset; size_t len_read; - vol = ubi_find_volume(volume); - if (vol == NULL) - return ENODEV; - if (vol->updating) { printf("updating"); - return EBUSY; + return -EBUSY; } if (vol->upd_marker) { printf("damaged volume, update marker is set"); - return EBADF; + return -EBADF; } if (offp == vol->used_bytes) return 0; - if (size == 0) { - printf("No size specified -> Using max size (%lld)\n", vol->used_bytes); + if (size == 0) size = vol->used_bytes; - } - - printf("Read %zu bytes from volume %s to %p\n", size, volume, buf); if (vol->corrupted) printf("read from corrupted volume %d", vol->vol_id); @@ -545,7 +549,7 @@ int ubi_volume_read(char *volume, char *buf, loff_t offset, size_t size) tbuf = malloc_cache_aligned(tbuf_size); if (!tbuf) { printf("NO MEM\n"); - return ENOMEM; + return -ENOMEM; } len = size > tbuf_size ? tbuf_size : size; @@ -561,7 +565,6 @@ int ubi_volume_read(char *volume, char *buf, loff_t offset, size_t size) err = ubi_eba_read_leb(ubi, vol, lnum, tbuf, off, len, 0); if (err) { printf("read err %x\n", err); - err = -err; break; } off += len; @@ -587,7 +590,19 @@ int ubi_volume_read(char *volume, char *buf, loff_t offset, size_t size) return err; } -static int ubi_dev_scan(struct mtd_info *info, const char *vid_header_offset) +int ubi_volume_read(const char *volume, void *buf, loff_t offset, size_t size) +{ + struct ubi_volume *vol; + + vol = ubi_require_volume(volume); + if (!vol) + return -ENODEV; + + return __ubi_volume_read(vol, buf, offset, size); +} + +static int ubi_dev_scan(const struct mtd_info *info, + const char *vid_header_offset) { char ubi_mtd_param_buffer[80]; int err; @@ -600,28 +615,25 @@ static int ubi_dev_scan(struct mtd_info *info, const char *vid_header_offset) err = ubi_mtd_param_parse(ubi_mtd_param_buffer, NULL); if (err) - return -err; + return err; led_activity_blink(); err = ubi_init(); led_activity_off(); if (err) - return -err; + return err; return 0; } -static int ubi_set_skip_check(char *volume, bool skip_check) +static int ubi_set_skip_check(const char *volume, bool skip_check) { struct ubi_vtbl_record vtbl_rec; struct ubi_volume *vol; - vol = ubi_find_volume(volume); + vol = ubi_require_volume(volume); if (!vol) - return ENODEV; - - printf("%sing skip_check on volume %s\n", - skip_check ? "Sett" : "Clear", volume); + return -ENODEV; vtbl_rec = ubi->vtbl[vol->vol_id]; if (skip_check) { @@ -635,7 +647,7 @@ static int ubi_set_skip_check(char *volume, bool skip_check) return ubi_change_vtbl_record(ubi, vol->vol_id, &vtbl_rec); } -static int ubi_detach(void) +int ubi_detach(void) { #ifdef CONFIG_CMD_UBIFS /* @@ -658,7 +670,7 @@ static int ubi_detach(void) return 0; } -int ubi_part(char *part_name, const char *vid_header_offset) +int ubi_part(const char *part_name, const char *vid_header_offset) { struct mtd_info *mtd; int err; @@ -674,7 +686,7 @@ int ubi_part(char *part_name, const char *vid_header_offset) mtd = get_mtd_device_nm(part_name); if (IS_ERR(mtd)) { printf("Partition %s not found!\n", part_name); - return 1; + return -ENODEV; } put_mtd_device(mtd); @@ -695,6 +707,8 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) int64_t size; ulong addr = 0; bool skipcheck = false; + struct ubi_volume *vol; + int ret; if (argc < 2) return CMD_RET_USAGE; @@ -709,7 +723,7 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (argc == 2) { if (!ubi) { printf("Error, no UBI device selected!\n"); - return 1; + return CMD_RET_FAILURE; } printf("Device %d: %s, MTD partition %s\n", @@ -723,12 +737,13 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (argc > 3) vid_header_offset = argv[3]; - return ubi_part(argv[2], vid_header_offset); + ret = ubi_part(argv[2], vid_header_offset); + return ret ? CMD_RET_FAILURE : 0; } if ((strcmp(argv[1], "part") != 0) && !ubi) { printf("Error, no UBI device selected!\n"); - return 1; + return CMD_RET_FAILURE; } if (strcmp(argv[1], "info") == 0) { @@ -758,11 +773,11 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return ubi_check(argv[2]); printf("Error, no volume name passed\n"); - return 1; + return CMD_RET_USAGE; } if (strncmp(argv[1], "create", 6) == 0) { - int dynamic = 1; /* default: dynamic volume */ + bool dynamic = true; /* default: dynamic volume */ int id = UBI_VOL_NUM_AUTO; /* Use maximum available size */ @@ -783,10 +798,10 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) /* E.g., create volume size type */ if (argc == 5) { if (strncmp(argv[4], "s", 1) == 0) - dynamic = 0; + dynamic = false; else if (strncmp(argv[4], "d", 1) != 0) { printf("Incorrect type\n"); - return 1; + return CMD_RET_USAGE; } argc--; } @@ -799,38 +814,80 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) /* Use maximum available size */ if (!size) { size = (int64_t)ubi->avail_pebs * ubi->leb_size; - printf("No size specified -> Using max size (%lld)\n", size); + if (size) + printf("No size specified -> Using max size (%lld)\n", + size); } /* E.g., create volume */ if (argc == 3) { - return ubi_create_vol(argv[2], size, dynamic, id, - skipcheck); + ret = ubi_create_vol(argv[2], size, dynamic, id, + skipcheck); + if (ret) + return CMD_RET_FAILURE; + + printf("Created %s volume %s of size %lld\n", + dynamic ? "dynamic" : "static", argv[2], size); + + return 0; } } if (strncmp(argv[1], "remove", 6) == 0) { /* E.g., remove volume */ - if (argc == 3) - return ubi_remove_vol(argv[2]); + if (argc == 3) { + int vol_id; + + vol = ubi_require_volume(argv[2]); + if (!vol) + return CMD_RET_FAILURE; + + vol_id = vol->vol_id; + + ret = __ubi_remove_vol(vol); + if (ret) + return CMD_RET_FAILURE; + + printf("Removed UBI volume %s (id %d)\n", argv[2], + vol_id); + + return 0; + } } - if (IS_ENABLED(CONFIG_CMD_UBI_RENAME) && !strncmp(argv[1], "rename", 6)) - return ubi_rename_vol(argv[2], argv[3]); + if (IS_ENABLED(CONFIG_CMD_UBI_RENAME) && !strncmp(argv[1], "rename", 6)) { + if (argc < 4) { + printf("Please see usage\n"); + return CMD_RET_USAGE; + } + + ret = ubi_rename_vol(argv[2], argv[3]); + if (ret) + return CMD_RET_FAILURE; + + printf("UBI volume %s renamed to %s\n", argv[2], argv[3]); + + return 0; + } if (strncmp(argv[1], "skipcheck", 9) == 0) { /* E.g., change skip_check flag */ if (argc == 4) { skipcheck = strncmp(argv[3], "on", 2) == 0; - return ubi_set_skip_check(argv[2], skipcheck); + ret = ubi_set_skip_check(argv[2], skipcheck); + if (ret) + return CMD_RET_FAILURE; + + printf("%s skip_check on volume %s\n", + skipcheck ? "Set" : "Cleared", argv[2]); + + return 0; } } if (strncmp(argv[1], "write", 5) == 0) { - int ret; - if (argc < 5) { printf("Please see usage\n"); - return 1; + return CMD_RET_USAGE; } addr = hextoul(argv[2], NULL); @@ -855,7 +912,7 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) argv[3]); } - return ret; + return ret ? CMD_RET_FAILURE : 0; } if (strncmp(argv[1], "read", 4) == 0) { @@ -874,12 +931,29 @@ static int do_ubi(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } if (argc == 3) { - return ubi_volume_read(argv[3], (char *)addr, 0, size); + vol = ubi_require_volume(argv[3]); + if (!vol) + return CMD_RET_FAILURE; + + if (!size) { + printf("No size specified -> Using max size (%lld)\n", + vol->used_bytes); + size = vol->used_bytes; + } + + ret = __ubi_volume_read(vol, (void *)addr, 0, size); + if (ret) + return CMD_RET_FAILURE; + + printf("%lld bytes read from volume %s to 0x%lx\n", + size, argv[3], addr); + + return 0; } } printf("Please see usage\n"); - return 1; + return CMD_RET_USAGE; } U_BOOT_CMD( diff --git a/cmd/ubifs.c b/cmd/ubifs.c index 22e95db8ca5..81f2d37fc7b 100644 --- a/cmd/ubifs.c +++ b/cmd/ubifs.c @@ -19,7 +19,7 @@ static int ubifs_initialized; static int ubifs_mounted; -int cmd_ubifs_mount(char *vol_name) +int cmd_ubifs_mount(const char *vol_name) { int ret; diff --git a/cmd/upl.c b/cmd/upl.c index ef2183d8528..be21ec258cb 100644 --- a/cmd/upl.c +++ b/cmd/upl.c @@ -93,7 +93,7 @@ static int do_upl_read(struct cmd_tbl *cmdtp, int flag, int argc, ulong addr; int ret; - if (argc < 1) + if (argc < 2) return CMD_RET_USAGE; addr = hextoul(argv[1], NULL); diff --git a/cmd/x86/zboot.c b/cmd/x86/zboot.c index 3876d163236..cc7292e10b7 100644 --- a/cmd/x86/zboot.c +++ b/cmd/x86/zboot.c @@ -66,9 +66,6 @@ static int do_zboot_setup(struct cmd_tbl *cmdtp, int flag, int argc, return CMD_RET_FAILURE; } - if (zboot_setup()) - return CMD_RET_FAILURE; - return 0; } diff --git a/common/Kconfig b/common/Kconfig index 8e8c733aa29..345be4b8ca1 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -78,7 +78,7 @@ config SYS_PBSIZE config DISABLE_CONSOLE bool "Add functionality to disable console completely" help - Disable console (in & out). + Disable console (in & out). config IDENT_STRING string "Board specific string to be added to uboot version string" @@ -884,9 +884,9 @@ config AVB_VERIFY help This option enables compilation of bootloader-dependent operations, used by Android Verified Boot 2.0 library (libavb). Includes: - * Helpers to process strings in order to build OS bootargs. - * Helpers to access MMC, similar to drivers/fastboot/fb_mmc.c. - * Helpers to alloc/init/free avb ops. + * Helpers to process strings in order to build OS bootargs. + * Helpers to access MMC, similar to drivers/fastboot/fb_mmc.c. + * Helpers to alloc/init/free avb ops. if AVB_VERIFY diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2e2863a0dd3..0618f42c941 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1321,10 +1321,10 @@ config SPL_PCI config SPL_PCI_ENDPOINT bool "Support for PCI endpoint drivers" help - Enable this configuration option to support configurable PCI - endpoints at SPL. This should be enabled if the platform has - a PCI controllers that can operate in endpoint mode (as a device - connected to PCI host or bridge). + Enable this configuration option to support configurable PCI + endpoints at SPL. This should be enabled if the platform has + a PCI controllers that can operate in endpoint mode (as a device + connected to PCI host or bridge). config SPL_PCH bool "Support PCH drivers" @@ -1552,18 +1552,18 @@ config SPL_SPI_FLASH_TINY depends on !SPI_FLASH_BAR default y if SPI_FLASH help - Enable lightweight SPL SPI Flash support that supports just reading - data/images from flash. No support to write/erase flash. Enable - this if you have SPL size limitations and don't need full - fledged SPI flash support. + Enable lightweight SPL SPI Flash support that supports just reading + data/images from flash. No support to write/erase flash. Enable + this if you have SPL size limitations and don't need full + fledged SPI flash support. config SPL_SPI_FLASH_SFDP_SUPPORT bool "SFDP table parsing support for SPI NOR flashes" depends on !SPI_FLASH_BAR && !SPL_SPI_FLASH_TINY help - Enable support for parsing and auto discovery of parameters for - SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) - tables as per JESD216 standard in SPL. + Enable support for parsing and auto discovery of parameters for + SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) + tables as per JESD216 standard in SPL. config SPL_SPI_FLASH_MTD bool "Support for SPI flash MTD drivers in SPL" @@ -1584,22 +1584,22 @@ config SYS_SPI_U_BOOT_OFFS default 0x0 depends on SPL_SPI_LOAD || SPL_SPI_SUNXI help - Address within SPI-Flash from where the u-boot payload is fetched - from. + Address within SPI-Flash from where the u-boot payload is fetched + from. config SYS_SPI_KERNEL_OFFS hex "Falcon mode: address of kernel payload in SPI flash" depends on SPL_SPI_FLASH_SUPPORT && SPL_OS_BOOT help - Address within SPI-Flash from where the kernel payload is fetched - in falcon boot. + Address within SPI-Flash from where the kernel payload is fetched + in falcon boot. config SYS_SPI_ARGS_OFFS hex "Falcon mode: address of args payload in SPI flash" depends on SPL_SPI_FLASH_SUPPORT && SPL_OS_BOOT_ARGS help - Address within SPI-Flash from where the args payload (usually the - dtb) is fetched in falcon boot. + Address within SPI-Flash from where the args payload (usually the + dtb) is fetched in falcon boot. config SYS_SPI_ARGS_SIZE hex "Falcon mode: size of args payload in SPI flash" diff --git a/common/usb_onboard_hub.c b/common/usb_onboard_hub.c index 6fc34489a98..0684f7bfd47 100644 --- a/common/usb_onboard_hub.c +++ b/common/usb_onboard_hub.c @@ -262,6 +262,12 @@ static int usb_onboard_hub_remove(struct udevice *dev) return ret; } +static const struct onboard_hub_data corechips_sl6341_data = { + .reset_us = 10000, + .num_supplies = 2, + .supply_names = { "vdd1v1-supply", "vdd3v3-supply" }, +}; + static const struct onboard_hub_data usb2514_data = { .power_on_delay_us = 500, .reset_us = 1, @@ -285,7 +291,13 @@ static const struct onboard_hub_data usbhx3_data = { static const struct udevice_id usb_onboard_hub_ids[] = { /* Use generic usbVID,PID dt-bindings (usb-device.yaml) */ - { .compatible = "usb424,2514", /* USB2514B USB 2.0 */ + { .compatible = "usb3431,6241", /* Corechips SL6341 USB 2.0 */ + .data = (ulong)&corechips_sl6341_data, + }, { + .compatible = "usb3431,6341", /* Corechips SL6341 USB 3.0 */ + .data = (ulong)&corechips_sl6341_data, + }, { + .compatible = "usb424,2514", /* USB2514B USB 2.0 */ .data = (ulong)&usb2514_data, }, { .compatible = "usb424,2744", /* USB2744 USB 2.0 */ diff --git a/configs/9tripod-x3568-v4-rk3568_defconfig b/configs/9tripod-x3568-v4-rk3568_defconfig new file mode 100644 index 00000000000..c0e7a565359 --- /dev/null +++ b/configs/9tripod-x3568-v4-rk3568_defconfig @@ -0,0 +1,76 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-9tripod-x3568-v4" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_SERIAL=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-9tripod-x3568-v4.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SYSCON=y +CONFIG_AHCI=y +CONFIG_DWC_AHCI=y +CONFIG_SPL_CLK=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_PHY_MOTORCOMM=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_SCSI=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_ERRNO_STR=y diff --git a/configs/an7581_evb_defconfig b/configs/an7581_evb_defconfig index 07569fa0a4e..a615994cc76 100644 --- a/configs/an7581_evb_defconfig +++ b/configs/an7581_evb_defconfig @@ -72,7 +72,7 @@ CONFIG_PCS_AIROHA_AN7581=y CONFIG_AIROHA_ETH=y CONFIG_PHY=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y +CONFIG_PINCTRL_AIROHA_AN7581=y CONFIG_POWER_DOMAIN=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/aquila-imx95_defconfig b/configs/aquila-imx95_defconfig new file mode 100644 index 00000000000..bb3d475ef4d --- /dev/null +++ b/configs/aquila-imx95_defconfig @@ -0,0 +1,186 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX9=y +CONFIG_TEXT_BASE=0x90200000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SPL_GPIO=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=3 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0xFFFFDE00 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx95-aquila-dev" +CONFIG_TARGET_AQUILA_IMX95=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_SYS_MONITOR_LEN=524288 +CONFIG_SPL_MMC=y +CONFIG_SPL_SERIAL=y +CONFIG_SPL_DRIVERS_MISC=y +CONFIG_SPL_STACK=0x204d6000 +CONFIG_SPL_TEXT_BASE=0x20480000 +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0x204d6000 +CONFIG_SPL_BSS_MAX_SIZE=0x2000 +CONFIG_SYS_LOAD_ADDR=0x90400000 +CONFIG_WATCHDOG_TIMEOUT_MSECS=30000 +CONFIG_SPL=y +CONFIG_SPL_RECOVER_DATA_SECTION=y +CONFIG_PCI=y +CONFIG_SYS_MEMTEST_START=0x90000000 +CONFIG_SYS_MEMTEST_END=0xA0000000 +CONFIG_REMAKE_ELF=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTSTD_FULL=y +CONFIG_BOOTDELAY=1 +CONFIG_OF_SYSTEM_SETUP=y +CONFIG_BOOTCOMMAND="bootflow scan -b" +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="test -n \"${fdtfile}\" || setenv fdtfile imx95-aquila-${fdt_board}.dtb" +CONFIG_SYS_CBSIZE=2048 +CONFIG_SYS_PBSIZE=2074 +CONFIG_LOG=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +# CONFIG_BOARD_INIT is not set +CONFIG_PCI_INIT_R=y +CONFIG_SPL_MAX_SIZE=0x30000 +CONFIG_SPL_BOARD_INIT=y +CONFIG_SPL_LOAD_IMX_CONTAINER=y +CONFIG_IMX_CONTAINER_CFG="arch/arm/mach-imx/imx9/scmi/container.cfg" +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_SPL_HAVE_INIT_STACK=y +CONFIG_SPL_SYS_MALLOC=y +CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y +CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x93200000 +CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 +CONFIG_SPL_SYS_MMCSD_RAW_MODE=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1040 +CONFIG_SPL_I2C=y +CONFIG_SPL_DM_MAILBOX=y +CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_THERMAL=y +CONFIG_SPL_WATCHDOG=y +CONFIG_SYS_PROMPT="Aquila iMX95 # " +CONFIG_CMD_ASKENV=y +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CRC32_VERIFY=y +CONFIG_CMD_MD5SUM=y +CONFIG_MD5SUM_VERIFY=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_READ=y +CONFIG_CMD_REMOTEPROC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_SDP=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_BOOTCOUNT=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_SYSBOOT=y +CONFIG_CMD_UUID=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_HASH=y +CONFIG_CMD_SCMI=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_RELOC_GD_ENV_ADDR=y +CONFIG_ENV_MMC_EMMC_HW_PARTITION=1 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_USE_ETHPRIME=y +CONFIG_ETHPRIME="eth0" +CONFIG_VERSION_VARIABLE=y +CONFIG_PROT_UDP=y +CONFIG_IP_DEFRAG=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_TFTP_BLOCKSIZE=4096 +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SYSCON=y +CONFIG_SPL_OF_TRANSLATE=y +CONFIG_BOOTCOUNT_LIMIT=y +CONFIG_BOOTCOUNT_ENV=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_SPL_CLK_CCF=y +CONFIG_CLK_CCF=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x90400000 +CONFIG_FASTBOOT_BUF_SIZE=0x20000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_UUU_SUPPORT=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_SPL_FIRMWARE=y +# CONFIG_SCMI_AGENT_SMCCC is not set +CONFIG_IMX_SM_CPU=y +CONFIG_IMX_SM_LMM=y +CONFIG_IMX_RGPIO2P=y +CONFIG_DM_PCA953X=y +CONFIG_SPL_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_IMX_LPI2C=y +CONFIG_IMX_MU_MBOX=y +CONFIG_I2C_EEPROM=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS400_ES_SUPPORT=y +CONFIG_MMC_HS400_SUPPORT=y +CONFIG_FSL_USDHC=y +CONFIG_DM_MDIO=y +CONFIG_MII=y +CONFIG_FSL_ENETC=y +CONFIG_PHYLIB=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PCIE_ECAM_GENERIC=y +CONFIG_PHY_IMX8MQ_USB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_IMX_SCMI=y +CONFIG_POWER_DOMAIN=y +CONFIG_SCMI_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_SPL_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_SPL_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REMOTEPROC_IMX=y +CONFIG_DM_RNG=y +CONFIG_DM_SERIAL=y +CONFIG_FSL_LPUART=y +CONFIG_SPI=y +CONFIG_DM_THERMAL=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Toradex" +CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 +CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 +CONFIG_USB_GADGET_OS_DESCRIPTORS=y +CONFIG_SDP_LOADADDR=0x90400000 +CONFIG_SPL_USB_SDP_SUPPORT=y +CONFIG_ULP_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_SHA1 is not set +CONFIG_LZO=y diff --git a/configs/easepi-r1-rk3568_defconfig b/configs/easepi-r1-rk3568_defconfig new file mode 100644 index 00000000000..fa400956b63 --- /dev/null +++ b/configs/easepi-r1-rk3568_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_COUNTER_FREQUENCY=24000000 +CONFIG_ARCH_ROCKCHIP=y +CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-easepi-r1" +CONFIG_ROCKCHIP_RK3568=y +CONFIG_SPL_SERIAL=y +CONFIG_SYS_LOAD_ADDR=0xc00800 +CONFIG_DEBUG_UART_BASE=0xFE660000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_FIT_SIGNATURE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-easepi-r1.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_MAX_SIZE=0x40000 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +CONFIG_SPL_ATF=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_GPT=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_USB=y +CONFIG_CMD_ROCKUSB=y +CONFIG_CMD_USB_MASS_STORAGE=y +CONFIG_CMD_PMIC=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_SYSCON=y +CONFIG_SPL_CLK=y +# CONFIG_USB_FUNCTION_FASTBOOT is not set +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_SUPPORT_EMMC_RPMB=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DWC_ETH_QOS=y +CONFIG_DWC_ETH_QOS_ROCKCHIP=y +CONFIG_RTL8169=y +CONFIG_PHY_REALTEK=y +CONFIG_NVME_PCI=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_SPL_RAM=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550_MEM32=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_SPL_USB_DWC3_GENERIC=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_USB_FUNCTION_ROCKUSB=y +CONFIG_ERRNO_STR=y diff --git a/configs/en7523_evb_defconfig b/configs/en7523_evb_defconfig index d3137a0ae44..8b1f3c71e9b 100644 --- a/configs/en7523_evb_defconfig +++ b/configs/en7523_evb_defconfig @@ -54,7 +54,7 @@ CONFIG_DM_MDIO=y CONFIG_AIROHA_ETH=y CONFIG_PHY=y CONFIG_PINCTRL=y -CONFIG_PINCONF=y +CONFIG_PINCTRL_AIROHA_EN7523=y CONFIG_RAM=y CONFIG_DM_SERIAL=y CONFIG_SYS_NS16550=y diff --git a/configs/evb-ast2700_defconfig b/configs/evb-ast2700_defconfig new file mode 100644 index 00000000000..d0733e14c67 --- /dev/null +++ b/configs/evb-ast2700_defconfig @@ -0,0 +1,160 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_POSITION_INDEPENDENT=y +# CONFIG_INIT_SP_RELATIVE is not set +CONFIG_ARM_SMCCC=y +CONFIG_ARCH_ASPEED=y +CONFIG_TEXT_BASE=0x400000000 +CONFIG_SYS_MALLOC_LEN=0x2000000 +CONFIG_ASPEED_AST2700=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x403000000 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_ENV_SECT_SIZE=0x20000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="ast2700-evb" +CONFIG_DM_RESET=y +CONFIG_SYS_LOAD_ADDR=0x403000000 +CONFIG_DEBUG_UART_BASE=0x14c33b00 +CONFIG_DEBUG_UART_CLOCK=1846154 +# CONFIG_PSCI_RESET is not set +CONFIG_ARMV8_CRYPTO=y +CONFIG_ENV_ADDR=0x400000 +CONFIG_SYS_PCI_64BIT=y +CONFIG_PCI=y +CONFIG_DEBUG_UART=y +CONFIG_SYS_MEMTEST_START=0x403000000 +CONFIG_SYS_MEMTEST_END=0x403001000 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +# CONFIG_BOOTMETH_EFILOADER is not set +CONFIG_LEGACY_IMAGE_FORMAT=y +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS12,115200n8 root=/dev/ram rw earlycon" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="echo Boot from ${boot_device}; if test ${boot_device} = mmc; then run bootmmc; fi; if test ${boot_device} = spi; then run bootspi; fi; if test ${boot_device} = ufs; then run bootufs; fi;" +CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_PBSIZE=276 +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +# CONFIG_AUTO_COMPLETE is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTFLOW is not set +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_BOOTEFI is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_EEPROM=y +CONFIG_CMD_MEMTEST=y +CONFIG_SYS_ALT_MEMTEST=y +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNLZ4 is not set +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MISC=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_UFS=y +CONFIG_CMD_NCSI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_EFICONFIG is not set +CONFIG_CMD_TPM=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +# CONFIG_CMD_CYCLIC is not set +CONFIG_DOS_PARTITION=y +CONFIG_EFI_PARTITION=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_MMC_USE_DT=y +CONFIG_USE_HOSTNAME=y +CONFIG_HOSTNAME="ast2700-evb" +CONFIG_BOOTP_SEND_HOSTNAME=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_DM_HASH=y +CONFIG_DFU_RAM=y +CONFIG_GPIO_HOG=y +CONFIG_ASPEED_G7_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AST2600=y +# CONFIG_INPUT is not set +CONFIG_DM_MAILBOX=y +CONFIG_I2C_EEPROM=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ASPEED=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SFDP_SUPPORT=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_DM_MDIO=y +CONFIG_FTGMAC100=y +CONFIG_ASPEED_MDIO=y +CONFIG_PHY_BROADCOM=y +CONFIG_PHY_AIROHA=y +CONFIG_PHY_REALTEK=y +CONFIG_PHY_TI_DP83867=y +CONFIG_PHY_NCSI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCI_CONFIG_HOST_BRIDGE=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +CONFIG_SCSI=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SPI_DIRMAP=y +CONFIG_SPI_ASPEED_SMC=y +CONFIG_SYSRESET=y +# CONFIG_TPM_V1 is not set +CONFIG_TPM2_TIS_SPI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="ASPEED" +CONFIG_USB_GADGET_VENDOR_NUM=0x2245 +CONFIG_USB_GADGET_PRODUCT_NUM=0x2700 +CONFIG_USB_GADGET_OS_DESCRIPTORS=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_UFS=y +# CONFIG_WATCHDOG_AUTOSTART is not set +CONFIG_WDT=y +# CONFIG_WDT_ASPEED is not set +CONFIG_ECDSA=y +CONFIG_ECDSA_VERIFY=y +CONFIG_TPM=y +CONFIG_LZ4=y +CONFIG_LZMA=y +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index 4039ef298d3..20294756d90 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -136,7 +136,6 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_TPM2_TIS_SPI=y CONFIG_TPM2_FTPM_TEE=y CONFIG_USB=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index 489d1ff2d32..ccd7bf6ed8e 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -139,7 +139,6 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_TPM2_TIS_SPI=y CONFIG_TPM2_FTPM_TEE=y CONFIG_USB=y diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index 2db503652ee..d84d60a7baf 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -88,4 +88,3 @@ CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y -CONFIG_DM_THERMAL=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 7650d7b734d..82fdd16c4d6 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -88,4 +88,3 @@ CONFIG_MXC_UART=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y -CONFIG_DM_THERMAL=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index f8a7d6060ee..3f954976c0a 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -149,7 +149,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mm-phygate-tauri-l_defconfig b/configs/imx8mm-phygate-tauri-l_defconfig index e34f12cabf3..9dc7fe21820 100644 --- a/configs/imx8mm-phygate-tauri-l_defconfig +++ b/configs/imx8mm-phygate-tauri-l_defconfig @@ -105,5 +105,4 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 04daa0040c1..32339e7f6e2 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -135,7 +135,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mm_beacon_fspi_defconfig b/configs/imx8mm_beacon_fspi_defconfig index 6017f50e51e..8c66fad7390 100644 --- a/configs/imx8mm_beacon_fspi_defconfig +++ b/configs/imx8mm_beacon_fspi_defconfig @@ -133,7 +133,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 7521df31f2f..05ecaeaebe4 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -18,7 +18,7 @@ CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x40400000 CONFIG_SPL=y CONFIG_EFI_MM_COMM_TEE=y CONFIG_EFI_VAR_BUF_SIZE=139264 @@ -71,6 +71,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y @@ -120,7 +121,6 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index 8ab6ee24b23..6d531efc5f7 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -21,7 +21,7 @@ CONFIG_SPL_TEXT_BASE=0x7E2000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x40400000 CONFIG_SPL=y CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 @@ -59,6 +59,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_RELOC_GD_ENV_ADDR=y @@ -107,7 +108,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y CONFIG_FSPI_CONF_HEADER=y CONFIG_FSPI_CONF_FILE="fspi_header.bin" diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig index c99b8e22bac..26bb5c12f02 100644 --- a/configs/imx8mm_phg_defconfig +++ b/configs/imx8mm_phg_defconfig @@ -103,7 +103,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index 0cde12d9d78..d9d1b7c6e71 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -157,7 +157,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y # CONFIG_TPM_V1 is not set CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index fd80c3065ed..83db14dc5bc 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -131,7 +131,6 @@ CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_PSCI=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index bc2d6014b21..6a1be97318a 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -138,7 +138,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mn_beacon_fspi_defconfig b/configs/imx8mn_beacon_fspi_defconfig index 800f851edbc..662f8f902d0 100644 --- a/configs/imx8mn_beacon_fspi_defconfig +++ b/configs/imx8mn_beacon_fspi_defconfig @@ -137,7 +137,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 18c44e801f4..033d1670d47 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -62,6 +62,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y @@ -97,7 +98,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_USB_EHCI_HCD=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 3233686034b..b7bee8cf276 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -80,6 +80,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y @@ -126,6 +127,5 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y CONFIG_SHA384=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index 54dce09bc9f..c5685c84d2a 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -152,7 +152,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y # CONFIG_TPM_V1 is not set CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y diff --git a/configs/imx8mp-libra-fpsc_defconfig b/configs/imx8mp-libra-fpsc_defconfig index 44f3c9fd796..142cbcf9888 100644 --- a/configs/imx8mp-libra-fpsc_defconfig +++ b/configs/imx8mp-libra-fpsc_defconfig @@ -156,7 +156,6 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/imx8mp_beacon_defconfig b/configs/imx8mp_beacon_defconfig index 1693264c9d6..8359f748244 100644 --- a/configs/imx8mp_beacon_defconfig +++ b/configs/imx8mp_beacon_defconfig @@ -152,7 +152,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 7af538ee367..12dcf3d1435 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -19,7 +19,7 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x98fc00 CONFIG_SPL_BSS_MAX_SIZE=0x400 CONFIG_SYS_BOOTM_LEN=0x2000000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x40600000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x20400 CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 @@ -75,6 +75,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index 401ad666011..eafaf4140be 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -159,7 +159,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index fdfd72fcd7b..6e8bb06d019 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -160,7 +160,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 49f0e0e829f..990d100f253 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -157,7 +157,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y # CONFIG_TPM_V1 is not set CONFIG_TPM2_TIS_SPI=y CONFIG_USB=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index 79c51191be0..9a8c16ccb19 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -94,6 +94,5 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y -CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y CONFIG_WDT=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index 67a7f339816..cc40e7b9bf3 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -19,7 +19,7 @@ CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x180000 CONFIG_SPL_BSS_MAX_SIZE=0x2000 -CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_LOAD_ADDR=0x40400000 CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_IMX_BOOTAUX=y @@ -70,6 +70,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIVE=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_REDUNDANT=y @@ -107,7 +108,6 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 64e3ee04293..9138bca067d 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -93,4 +93,3 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y -CONFIG_DM_THERMAL=y diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig index 23ee6278503..a63a01ba8d9 100644 --- a/configs/imx8mq_reform2_defconfig +++ b/configs/imx8mq_reform2_defconfig @@ -93,7 +93,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/imx952_evk_defconfig b/configs/imx952_evk_defconfig index b74df3a5d5f..9c12d2b32ac 100644 --- a/configs/imx952_evk_defconfig +++ b/configs/imx952_evk_defconfig @@ -35,7 +35,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_SYSTEM_SETUP=y CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd" -CONFIG_DEFAULT_FDT_FILE="freescale/imx952-evk.dtb" +CONFIG_DEFAULT_FDT_FILE="imx952-evk.dtb" CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=2074 CONFIG_BOARD_LATE_INIT=y diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index f999ed073e8..1673cf7efad 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -192,7 +192,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y @@ -210,5 +209,4 @@ CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_ETHER=y CONFIG_USB_ETH_CDC=y CONFIG_SPL_USB_SDP_SUPPORT=y -# CONFIG_WATCHDOG_AUTOSTART is not set CONFIG_IMX_WATCHDOG=y diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index b216a0bb270..1b175670ffd 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -106,7 +106,6 @@ CONFIG_DM_RTC=y CONFIG_RTC_RV8803=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig index 7e450e2d356..72ffb72a137 100644 --- a/configs/librem5_defconfig +++ b/configs/librem5_defconfig @@ -130,7 +130,6 @@ CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig index 6917fe7783b..a8c7c89c9d3 100644 --- a/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1028ardb_tfa_SECURE_BOOT_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SOURCE_FILE="ls1028ardb" CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_DM_GPIO=y diff --git a/configs/ls1028ardb_tfa_defconfig b/configs/ls1028ardb_tfa_defconfig index f1c13afbb2e..ca19d6035ee 100644 --- a/configs/ls1028ardb_tfa_defconfig +++ b/configs/ls1028ardb_tfa_defconfig @@ -6,6 +6,7 @@ CONFIG_TARGET_LS1028ARDB=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_LEN=0x202000 CONFIG_SYS_MALLOC_F_LEN=0x6000 +CONFIG_ENV_SOURCE_FILE="ls1028ardb" CONFIG_NR_DRAM_BANKS=2 CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0x500000 diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index 3767fdfb23b..10061a1ba4c 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -131,5 +131,4 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index 2b2aa899632..a116c65a99e 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -162,7 +162,6 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TEE=y CONFIG_OPTEE=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index 2d5bfffa093..dc2263368ab 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -91,4 +91,3 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y -CONFIG_DM_THERMAL=y diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig index ecd77388763..c52f619850d 100644 --- a/configs/qcom_defconfig +++ b/configs/qcom_defconfig @@ -135,8 +135,6 @@ CONFIG_QCOM_RPMH=y CONFIG_SPMI_MSM=y CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y -CONFIG_SYSRESET_CMD_RESET_ARGS=y -CONFIG_SYSRESET_QCOM_PSCI=y CONFIG_SYSRESET_QCOM_PSHOLD=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/configs/toradex-smarc-imx8mp_defconfig b/configs/toradex-smarc-imx8mp_defconfig index c0185ed9ca5..7301d7a4ace 100644 --- a/configs/toradex-smarc-imx8mp_defconfig +++ b/configs/toradex-smarc-imx8mp_defconfig @@ -160,7 +160,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_DM_USB_GADGET=y diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index c8a2a057135..16e5ce7f406 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -145,7 +145,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index 3c9dab36d90..778d56ad55d 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -162,7 +162,6 @@ CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y -CONFIG_DM_THERMAL=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set CONFIG_DM_USB_GADGET=y diff --git a/disk/Kconfig b/disk/Kconfig index 937ae1da61d..672ad46a48f 100644 --- a/disk/Kconfig +++ b/disk/Kconfig @@ -8,11 +8,11 @@ config PARTITIONS Zero or more of the following: - CONFIG_MAC_PARTITION Apple's MacOS partition table. - CONFIG_DOS_PARTITION MS Dos partition table, traditional on the - Intel architecture, USB sticks, etc. + Intel architecture, USB sticks, etc. - CONFIG_ISO_PARTITION ISO partition table, used on CDROM etc. - CONFIG_EFI_PARTITION GPT partition table, common when EFI is the - bootloader. Note 2TB partition limit; see - disk/part_efi.c + bootloader. Note 2TB partition limit; see + disk/part_efi.c - CONFIG_MTD_PARTITIONS Memory Technology Device partition table. If IDE or SCSI support is enabled (CONFIG_CMD_IDE or CONFIG_SCSI) you must configure support for at least one non-MTD partition type diff --git a/doc/android/fastboot.rst b/doc/android/fastboot.rst index 818b8815ebd..96c544ae11b 100644 --- a/doc/android/fastboot.rst +++ b/doc/android/fastboot.rst @@ -217,6 +217,10 @@ It's possible to interrupt the fastboot command using Ctrl-c:: => fastboot usb 0 Operation aborted. +``CONFIG_CMD_FASTBOOT_ABORT_KEYED`` can be enabled so that *any* keypress +will interrupt the fastboot command, rather than just Ctrl-c. This can be +quite useful on mobile devices which lack a means to input Ctrl-c. + You can also specify a kernel image to boot. You have to either specify the an image in Android format *or* pass a binary kernel and let the fastboot client wrap the Android suite around it. On OMAP for instance you diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index a31ee7100b9..f77f1e78f38 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -126,6 +126,7 @@ List of mainline supported Rockchip boards: - Xunlong Orange Pi 3B (orangepi-3b-rk3566) * rk3568 + - 9Tripod X3568 v4 (9tripod-x3568-v4-rk3568) - Rockchip Evb-RK3568 (evb-rk3568) - Banana Pi BPI-R2 Pro (bpi-r2-pro-rk3568) - EmbedFire LubanCat 2 (lubancat-2-rk3568) @@ -133,6 +134,7 @@ List of mainline supported Rockchip boards: - FriendlyElec NanoPi R5S (nanopi-r5s-rk3568) - Generic RK3566/RK3568 (generic-rk3568) - Hardkernel ODROID-M1 (odroid-m1-rk3568) + - LinkEase EasePi R1 (easepi-r1-rk3568) - Lunzn FastRhino R66S (fastrhino-r66s-rk3568) - QNAP TS-433 (qnap-ts433-rk3568) - Radxa E25 Carrier Board (radxa-e25-rk3568) @@ -248,7 +250,7 @@ To build rk3288 boards: .. code-block:: bash - make evb-rk3288-mk808_defconfig + make evb-rk3288-rk808_defconfig make CROSS_COMPILE=arm-linux-gnueabihf- To build rk3308 boards: diff --git a/doc/board/toradex/aquila-imx95.rst b/doc/board/toradex/aquila-imx95.rst new file mode 100644 index 00000000000..edd40252657 --- /dev/null +++ b/doc/board/toradex/aquila-imx95.rst @@ -0,0 +1,175 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Toradex Aquila iMX95 Module +=========================== + +- SoM: https://www.toradex.com/computer-on-modules/aquila-arm-family/nxp-imx95 +- Carrier board: https://www.toradex.com/products/carrier-board/aquila-development-board-kit + +Quick Start +----------- + +- Setup environment +- Get ahab-container.img +- Get DDR PHY Firmware Images +- Get and Build OEI Images +- Get and Build System Manager Image +- Get and Build the ARM Trusted Firmware +- Build the Bootloader Image +- Boot + +Setup environment +----------------- + +Suggested current toolchains are ARM 14.3 (https://developer.arm.com/downloads/-/arm-gnu-toolchain-downloads): + +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-arm-none-linux-gnueabihf.tar.xz +- https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/arm-gnu-toolchain-14.3.rel1-x86_64-aarch64-none-linux-gnu.tar.xz + +.. code-block:: console + + $ export TOOLS=<path/to/directory/with/toolchains> + $ export CROSS_COMPILE_32=<path/to/arm/toolchain/bin/>arm-none-linux-gnueabihf- + $ export CROSS_COMPILE_64=<path/to/arm64/toolchain/bin/>aarch64-none-linux-gnu- + +Get ahab-container.img +---------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-ele-imx-2.0.2-89161a8.bin + $ sh firmware-ele-imx-2.0.2-89161a8.bin --auto-accept + $ cp firmware-ele-imx-2.0.2-89161a8/mx95b0-ahab-container.img $(srctree) + +Get DDR PHY Firmware Images +--------------------------- + +Note: `$srctree` is the U-Boot source directory + +.. code-block:: console + + $ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.28-994fa14.bin + $ sh firmware-imx-8.28-994fa14.bin --auto-accept + $ cp firmware-imx-8.28-994fa14/firmware/ddr/synopsys/lpddr5*v202409.bin $(srctree) + +Get and Build OEI Images +------------------------ + +Note: `$srctree` is the U-Boot source directory +Get OEI from: https://git.toradex.com/cgit/imx-oei-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-oei-toradex.git/ + $ cd imx-oei-toradex + + $ make board=toradex-aquila-imx95 oei=ddr DEBUG=1 r=B0 all + $ cp build/toradex-aquila-imx95/ddr/oei-m33-ddr.bin $(srctree) + + $ make board=toradex-aquila-imx95 oei=tcm DEBUG=1 r=B0 all + $ cp build/toradex-aquila-imx95/tcm/oei-m33-tcm.bin $(srctree) + +The Makefile will set `DDR_CONFIG` automatically based on the selected silicon +revision. + +Get and Build the System Manager Image +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get System Manager from: https://git.toradex.com/cgit/imx-sm-toradex.git/ +branch: main + +.. code-block:: console + + $ git clone -b main https://git.toradex.com/cgit/imx-sm-toradex.git/ + $ cd imx-sm-toradex + $ make config=aquila-imx95 all + $ cp build/aquila-imx95/m33_image.bin $(srctree) + +Get and Build the ARM Trusted Firmware +-------------------------------------- + +Note: `$srctree` is the U-Boot source directory +Get ATF from: https://github.com/nxp-imx/imx-atf/ +branch: lf_v2.12 + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ unset LDFLAGS + $ unset AS + $ git clone -b lf_v2.12 https://github.com/nxp-imx/imx-atf.git + $ cd imx-atf + $ make PLAT=imx95 bl31 + $ cp build/imx95/release/bl31.bin $(srctree) + +Build the Bootloader Image +-------------------------- + +.. code-block:: console + + $ export CROSS_COMPILE=$CROSS_COMPILE_64 + $ make aquila-imx95_defconfig + $ make + +Flash to eMMC +------------- + +.. code-block:: console + + > tftpboot ${loadaddr} flash.bin + > setexpr blkcnt ${filesize} + 0x1ff && setexpr blkcnt ${blkcnt} / 0x200 + > mmc dev 0 1 && mmc write ${loadaddr} 0x0 ${blkcnt} + +As a convenience, instead of the last two commands, one may also use the update +U-Boot wrapper: + +.. code-block:: console + + > run update_uboot + +Boot +---- + +Boot sequence is: + +* SPL ---> ATF (TF-A) ---> U-Boot proper + +Output: + +.. code-block:: console + + U-Boot SPL 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200) + SYS Boot reason: por, origin: -1, errid: -1 + WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) + Trying to boot from MMC1 + Load image from MMC/SD 0xd2800 + NOTICE: BL31: v2.10.0 (release):lf-6.6.52-2.2.1-dirty + NOTICE: BL31: Built : 06:40:36, Jul 7 2025 + + + U-Boot 2026.07-rc3-00300-ge16706b72e14 (Jun 11 2026 - 13:07:49 +0200) + + CPU: NXP i.MX95 Rev2.0 A55 at 1800 MHz - invalid sensor data + DRAM: 7.8 GiB + Core: 321 devices, 30 uclasses, devicetree: separate + WDT: Started watchdog@42490000 with servicing every 1000ms (40s timeout) + MMC: FSL_SDHC: 0, FSL_SDHC: 1 + Loading Environment from MMC... Reading from MMC(0)... OK + In: serial@44380000 + Out: serial@44380000 + Err: serial@44380000 + Model: Toradex 0098 Aquila iMX95 Hexa 8GB WB IT V1.0A + Serial#: 12594391 + + BuildInfo: + - ELE firmware version 2.0.2-c110ba4b + + Net: WARNING: no MAC address assigned for MAC0 + imx_get_mac_from_fuse: fuse read err: 0 + eth0: enetc-0 [PRIME] + Hit any key to stop autoboot: 0 + Aquila iMX95 # diff --git a/doc/board/toradex/index.rst b/doc/board/toradex/index.rst index 2a45bde6991..c5955ea1ad8 100644 --- a/doc/board/toradex/index.rst +++ b/doc/board/toradex/index.rst @@ -8,6 +8,7 @@ Toradex apalis-imx8 aquila-am69 + aquila-imx95 colibri_imx7 colibri-imx8x smarc-imx8mp diff --git a/doc/chromium/chainload.rst b/doc/chromium/chainload.rst index b00ee94eaa4..0f61e020db8 100644 --- a/doc/chromium/chainload.rst +++ b/doc/chromium/chainload.rst @@ -42,9 +42,9 @@ Nyan-big Compiled based on information here:: - https://lists.denx.de/pipermail/u-boot/2015-March/209530.html + https://patch.msgid.link/[email protected]/ https://git.collabora.com/cgit/user/tomeu/u-boot.git/commit/?h=nyan-big - https://lists.denx.de/pipermail/u-boot/2017-May/289491.html + https://patch.msgid.link/CALr8Vo1WvO=m1W2zvT=MOQ3k-fNtcCtBjk2+zgKha0j28s8g6A@mail.gmail.com/ https://github.com/chromeos-nvidia-androidtv/gnu-linux-on-acer-chromebook-13#copy-data-to-the-sd-card 1. Build U-Boot diff --git a/doc/develop/codingstyle.rst b/doc/develop/codingstyle.rst index 26881cf3900..b8d2bf23a54 100644 --- a/doc/develop/codingstyle.rst +++ b/doc/develop/codingstyle.rst @@ -24,54 +24,6 @@ The following rules apply: <https://peps.python.org/pep-0008/>`_. Use `pylint <https://github.com/pylint-dev/pylint>`_ for checking the code. -.. _b4_contrib: - -* Use the `b4 <https://b4.docs.kernel.org/en/latest/>`__ tool to prepare and - send your patches. b4 has become the preferred tool to sending patches for many - Linux kernel contributors, and U-Boot ships with a ready-to-use ``.b4-config`` that - targets ``[email protected]`` and integrates with ``scripts/get_maintainer.pl`` for - recipient discovery. - - Start a topical series with ``b4 prep`` and keep the commits organised with - ``git rebase -i``. ``b4 prep --edit-cover`` opens an editor for the cover - letter, while ``b4 prep --auto-to-cc`` collects reviewers and maintainers from - both the configuration file and ``scripts/get_maintainer.pl``. - - .. code-block:: bash - - b4 prep -n mmc-fixes - git rebase -i origin/master - b4 prep --edit-cover - b4 prep --auto-to-cc - - Run the style checks before sending. ``b4 prep --check`` wraps the existing - tooling so you see the output from ``scripts/checkpatch.pl`` alongside b4's - own validation. You can always invoke ``scripts/checkpatch.pl`` directly for - additional runs. - - .. code-block:: bash - - b4 prep --check - - When the series is ready, use ``b4 send``. Begin with ``--dry-run`` to review - the generated emails and ``--reflect`` to copy yourself for records before - dispatching to ``[email protected]``. - - .. code-block:: bash - - b4 send --dry-run - b4 send --reflect - b4 send - - After reviews arrive, collect Acked-by/Tested-by tags with ``b4 trailers -u`` - and fold them into your commits before resending the updated series. - - .. code-block:: bash - - b4 trailers -u - git rebase -i origin/master - b4 send - * Run ``scripts/checkpatch.pl`` directly or via ``b4 prep --check`` so that all issues are resolved *before* posting on the mailing list. For more information, read :doc:`checkpatch`. diff --git a/doc/develop/driver-model/spi-howto.rst b/doc/develop/driver-model/spi-howto.rst index 9dc3b9b4aac..65dd50e7d55 100644 --- a/doc/develop/driver-model/spi-howto.rst +++ b/doc/develop/driver-model/spi-howto.rst @@ -649,8 +649,8 @@ board. Prepare patches and send them to the mailing lists -------------------------------------------------- -You can use 'tools/patman/patman' to prepare, check and send patches for -your work. See tools/patman/README for details. +You can prepare, check and send patches for your work using the tools described +in :doc:`/develop/sending_patches`. A little note about SPI uclass features --------------------------------------- diff --git a/doc/develop/historical/generic_board.rst b/doc/develop/historical/generic_board.rst index 12550a140e0..17a92687c5b 100644 --- a/doc/develop/historical/generic_board.rst +++ b/doc/develop/historical/generic_board.rst @@ -64,17 +64,17 @@ separate function calls so that they can easily be included or excluded for a particular architecture. It also makes it easier to adopt Graeme's initcall proposal when it is ready. -http://lists.denx.de/pipermail/u-boot/2012-January/114499.html +https://patch.msgid.link/[email protected]/ This series removes the dependency on generic relocation. So relocation happens as one big chunk and is still completely arch-specific. See the relocation series for a proposed solution to this for ARM: -http://lists.denx.de/pipermail/u-boot/2011-December/112928.html +https://patch.msgid.link/CAPnjgZ0jesqX1Y71S5xoYQDGPuARfOX48RGbU9Mw=P5HGYcOKg@mail.gmail.com/ or Graeme's recent x86 series v2: -http://lists.denx.de/pipermail/u-boot/2012-January/114467.html +https://patch.msgid.link/[email protected]/ Instead of moving over a whole architecture, this series takes the approach of simply enabling generic board support for an architecture. It is then up diff --git a/doc/develop/index.rst b/doc/develop/index.rst index 3c044e67927..51fd68fa04b 100644 --- a/doc/develop/index.rst +++ b/doc/develop/index.rst @@ -16,7 +16,6 @@ General docstyle kconfig memory - patman process release_cycle security diff --git a/doc/develop/patman.rst b/doc/develop/patman.rst deleted file mode 120000 index 0fcb7d61d40..00000000000 --- a/doc/develop/patman.rst +++ /dev/null @@ -1 +0,0 @@ -../../tools/patman/patman.rst
\ No newline at end of file diff --git a/doc/develop/release_cycle.rst b/doc/develop/release_cycle.rst index 2f024905157..a454d343676 100644 --- a/doc/develop/release_cycle.rst +++ b/doc/develop/release_cycle.rst @@ -1,4 +1,4 @@ -.. |next_ver| replace:: v2026.07 +.. |next_ver| replace:: v2026.10 Release Cycle ============= @@ -53,15 +53,15 @@ Examples:: Current Status -------------- -* U-Boot v2026.04 was released on Monday, 06 April 2026. +* U-Boot v2026.07 was released on Monday, 06 July 2026. -* The Merge Window for the next release (|next_ver|) is **closed** with the -rc1 - release on Monday, 27 April 2026. +* The Merge Window for the next release (|next_ver|) is **open** until the -rc1 + release on Monday, 27 July 2026. -* The next branch is now **open** with the -rc2 release on Monday, 11 - May 2026. +* The next branch is now **closed** until the -rc2 release on Monday, 10 + August 2026. -* Release "|next_ver|" is scheduled for Monday, 06 July 2026. +* Release "|next_ver|" is scheduled for Monday, 05 October 2026. Future Releases --------------- @@ -69,29 +69,29 @@ Future Releases .. The following commented out dates are for when release candidates are planned to be tagged. -For the next scheduled release, release candidates were made on: +.. For the next scheduled release, release candidates were made on: -* U-Boot |next_ver|-rc1 was released on Mon 27 April 2026. +.. * U-Boot |next_ver|-rc1 was released on Mon 27 July 2026. -* U-Boot |next_ver|-rc2 was released on Mon 11 May 2026. +.. * U-Boot |next_ver|-rc2 was released on Mon 10 August 2026. -* U-Boot |next_ver|-rc3 was released on Mon 25 May 2026. +.. * U-Boot |next_ver|-rc3 was released on Mon 24 August 2026. -* U-Boot |next_ver|-rc4 was released on Mon 08 June 2026. +.. * U-Boot |next_ver|-rc4 was released on Mon 07 September 2026. -* U-Boot |next_ver|-rc5 was released on Mon 22 June 2026. +.. * U-Boot |next_ver|-rc5 was released on Mon 21 September 2026. Please note that the following dates are planned only and may be deviated from as needed. -* "v2026.07": end of MW = Mon, Apr 27, 2026; release = Mon, Jul 06, 2026 - * "v2026.10": end of MW = Mon, Jul 27, 2026; release = Mon, Oct 05, 2026 * "v2027.01": end of MW = Mon, Oct 26, 2026; release = Mon, Jan 04, 2027 * "v2027.04": end of MW = Mon, Jan 25, 2027; release = Mon, Apr 05, 2027 +* "v2027.07": end of MW = Mon, Apr 26, 2027; release = Mon, Jul 05, 2027 + Previous Releases ----------------- @@ -99,6 +99,8 @@ Note: these statistics are generated by our fork of `gitdm <https://source.denx.de/u-boot/gitdm>`_, which was originally created by Jonathan Corbet. +* :doc:`statistics/u-boot-stats-v2026.07` which was released on 06 July 2026. + * :doc:`statistics/u-boot-stats-v2026.04` which was released on 06 April 2026. * :doc:`statistics/u-boot-stats-v2026.01` which was released on 05 January 2026. diff --git a/doc/develop/sending_patches.rst b/doc/develop/sending_patches.rst index e29fa175727..c3e0ef27824 100644 --- a/doc/develop/sending_patches.rst +++ b/doc/develop/sending_patches.rst @@ -17,14 +17,71 @@ A good introduction how to prepare for submitting patches can be found in the LWN article `How to Get Your Change Into the Linux Kernel <http://lwn.net/Articles/139918/>`_ as the same rules apply to U-Boot, too. +.. _b4_contrib: + +Using b4 +-------- + +Use the `b4 <https://b4.docs.kernel.org/en/latest/>`__ tool to prepare and send +your patches. b4 has become the preferred tool to sending patches for many Linux +kernel contributors, and U-Boot ships with a ready-to-use ``.b4-config`` that +targets ``[email protected]`` and integrates with ``scripts/get_maintainer.pl`` +for recipient discovery. + +Start a topical series with ``b4 prep`` and keep the commits organised with +``git rebase -i``. ``b4 prep --edit-cover`` opens an editor for the cover letter, +while ``b4 prep --auto-to-cc`` collects reviewers and maintainers from both the +configuration file and ``scripts/get_maintainer.pl``. + +.. code-block:: bash + + b4 prep -n mmc-fixes + git rebase -i origin/master + b4 prep --edit-cover + b4 prep --auto-to-cc + +Run the style checks before sending. ``b4 prep --check`` wraps the existing +tooling so you see the output from ``scripts/checkpatch.pl`` alongside b4's own +validation. You can always invoke ``scripts/checkpatch.pl`` directly for +additional runs. + +.. code-block:: bash + + b4 prep --check + +When the series is ready, use ``b4 send``. Begin with ``--dry-run`` to review the +generated emails and ``--reflect`` to copy yourself for records before +dispatching to ``[email protected]``. + +.. code-block:: bash + + b4 send --dry-run + b4 send --reflect + b4 send + +After reviews arrive, collect Acked-by/Tested-by tags with ``b4 trailers -u`` and +fold them into your commits before resending the updated series. + +.. code-block:: bash + + b4 trailers -u + git rebase -i origin/master + b4 send + Using patman ------------ You can use a tool called patman to prepare, check and send patches. It creates change logs, cover letters and patch notes. It also simplifies the process of -sending multiple versions of a series. +sending multiple versions of a series. patman is driven by tags in your commit +messages, and can collect Reviewed-by and other tags from patchwork when you +send a new version. It can optionally keep a local database of all your series, +tracking each version and their review / applied status over time, so you can +easily track upstreaming progress. -See more details at :doc:`patman`. +patman now lives outside the U-Boot tree; install it with +``pip install patch-manager``. See the +`patman documentation <https://deinde.dev/patman>`_ for details. General Patch Submission Rules ------------------------------ diff --git a/doc/develop/statistics/u-boot-stats-v2026.07.rst b/doc/develop/statistics/u-boot-stats-v2026.07.rst new file mode 100644 index 00000000000..724419a444a --- /dev/null +++ b/doc/develop/statistics/u-boot-stats-v2026.07.rst @@ -0,0 +1,884 @@ +:orphan: + +Release Statistics for U-Boot v2026.07 +====================================== + +* Processed 1328 changesets from 212 developers + +* 25 employers found + +* A total of 255173 lines added, 91237 removed (delta 163936) + +.. table:: Developers with the most changesets + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + David Lechner 139 (10.5%) + Tom Rini 96 (7.2%) + Simon Glass 94 (7.1%) + Marek Vasut 72 (5.4%) + Peng Fan 56 (4.2%) + Heinrich Schuchardt 42 (3.2%) + Julien Stephan 32 (2.4%) + Michal Simek 27 (2.0%) + Jonas Karlman 24 (1.8%) + Dario Binacchi 19 (1.4%) + Ye Li 17 (1.3%) + Quentin Schulz 16 (1.2%) + Mikhail Kshevetskiy 15 (1.1%) + Svyatoslav Ryhel 15 (1.1%) + Francois Berder 14 (1.1%) + Raymond Mao 13 (1.0%) + Neha Malcom Francis 12 (0.9%) + Janne Grunau 12 (0.9%) + Kory Maincent 12 (0.9%) + Richard Genoud 12 (0.9%) + Casey Connolly 11 (0.8%) + Emanuele Ghidoli 11 (0.8%) + Rasmus Villemoes 11 (0.8%) + Francesco Dolcini 11 (0.8%) + Balaji Selvanathan 11 (0.8%) + Alice Guo 10 (0.8%) + Michael Walle 10 (0.8%) + Hrushikesh Salunke 10 (0.8%) + Sparsh Kumar 10 (0.8%) + Luca Weiss 9 (0.7%) + Vincent Stehlé 9 (0.7%) + Johan Jonker 9 (0.7%) + Pranav Tilak 9 (0.7%) + Angelo Dureghello 9 (0.7%) + Alexey Charkov 8 (0.6%) + Aswin Murugan 8 (0.6%) + Torsten Duwe 8 (0.6%) + Patrice Chotard 8 (0.6%) + Mathew McBride 8 (0.6%) + Varadarajan Narayanan 8 (0.6%) + Max Merchel 8 (0.6%) + Christian Marangi 8 (0.6%) + Alexander Feilke 7 (0.5%) + Chris-QJ Chen 7 (0.5%) + Hal Feng 7 (0.5%) + Javier Martinez Canillas 7 (0.5%) + Heiko Schocher 6 (0.5%) + Markus Schneider-Pargmann (TI) 6 (0.5%) + Noah.Shen 6 (0.5%) + Pranav Sanwal 6 (0.5%) + Padmarao Begari 6 (0.5%) + Dan Carpenter 6 (0.5%) + Wojciech Dubowik 6 (0.5%) + RafaÅ‚ MiÅ‚ecki 6 (0.5%) + Brian Ruley 6 (0.5%) + Tanmay Kathpalia 5 (0.4%) + Wadim Egorov 5 (0.4%) + Franz Schnyder 5 (0.4%) + Jamie Gibbons 5 (0.4%) + Prashant Kamble 5 (0.4%) + Anshul Dalal 5 (0.4%) + Ludwig Nussel 5 (0.4%) + E Shattow 5 (0.4%) + Adrian Freihofer 5 (0.4%) + Aristo Chen 4 (0.3%) + Shiji Yang 4 (0.3%) + Christian DREHER 4 (0.3%) + Randolph Sapp 4 (0.3%) + Andre Przywara 4 (0.3%) + Ferass El Hafidi 4 (0.3%) + Daniel Palmer 4 (0.3%) + Chunguang Li 4 (0.3%) + Paresh Bhagat 4 (0.3%) + Ion Agorria 4 (0.3%) + Niko Mauno 4 (0.3%) + Vignesh Raghavendra 4 (0.3%) + Neil Armstrong 3 (0.2%) + Sam Day 3 (0.2%) + Denis Mukhin 3 (0.2%) + Sumit Garg 3 (0.2%) + Christian Pötzsch 3 (0.2%) + Lucien.Jheng 3 (0.2%) + Siddharth Vadapalli 3 (0.2%) + Paul HENRYS 3 (0.2%) + Vitor Soares 3 (0.2%) + Michele Bisogno 3 (0.2%) + Primoz Fiser 3 (0.2%) + Sam Shih 3 (0.2%) + Ssunk 3 (0.2%) + Ngo Luong Thanh Tra 3 (0.2%) + Ioana Ciornei 3 (0.2%) + Markus Niebel 3 (0.2%) + Jonas Schwöbel 3 (0.2%) + Lukas Stockmann 3 (0.2%) + Brian Sune 3 (0.2%) + Alif Zakuan Yuslaimi 3 (0.2%) + Ilias Apalodimas 2 (0.2%) + Peter Robinson 2 (0.2%) + João Marcos Costa 2 (0.2%) + Mateusz Furdyna 2 (0.2%) + Zixun LI 2 (0.2%) + Gurumoorthy Santhakumar 2 (0.2%) + Francesco Valla 2 (0.2%) + Yann Gautier 2 (0.2%) + Peter Collingbourne 2 (0.2%) + Vincent Jardin 2 (0.2%) + Ernest Van Hoecke 2 (0.2%) + Weijie Gao 2 (0.2%) + Shiva Tripathi 2 (0.2%) + Paul Kocialkowski 2 (0.2%) + Macpaul Lin 2 (0.2%) + Gregor Herburger 2 (0.2%) + Philip Molloy 2 (0.2%) + Simona Toaca 2 (0.2%) + Flaviu Nistor 2 (0.2%) + Chen Huei Lok 2 (0.2%) + Jeffrey Yu 2 (0.2%) + Sean Anderson 2 (0.2%) + Paul Gerber 2 (0.2%) + Boon Khai Ng 2 (0.2%) + Kavin Gunasekara 2 (0.2%) + Fabio Estevam 2 (0.2%) + Shantur Rathore 2 (0.2%) + Dominik Haller 2 (0.2%) + Bo-Chen Chen 2 (0.2%) + Finley Xiao 2 (0.2%) + Walter Schweizer 2 (0.2%) + Julien Masson 2 (0.2%) + Dinesh Maniyam 2 (0.2%) + Vagrant Cascadian 2 (0.2%) + Mattijs Korpershoek 1 (0.1%) + Andrew Goodbody 1 (0.1%) + Quentin Strydom 1 (0.1%) + Piyush Paliwal 1 (0.1%) + Heiko Stuebner 1 (0.1%) + Colin Pinnell McAllister 1 (0.1%) + Petr Hodina 1 (0.1%) + Udit Kumar 1 (0.1%) + Federico Amedeo Izzo 1 (0.1%) + Frank Böwingloh 1 (0.1%) + Frieder Schrempf 1 (0.1%) + Andrea della Porta 1 (0.1%) + Giovanni Santini 1 (0.1%) + Tony Dinh 1 (0.1%) + Nguyen Tran 1 (0.1%) + Jan ÄŒermák 1 (0.1%) + Lionel Debieve 1 (0.1%) + Liel Harel 1 (0.1%) + Suhaas Joshi 1 (0.1%) + Moteen Shah 1 (0.1%) + Harsimran Singh Tungal 1 (0.1%) + Mark Kettenis 1 (0.1%) + Tze Yee Ng 1 (0.1%) + Raphaël Gallais-Pou 1 (0.1%) + Austin Shirley 1 (0.1%) + Alexander Sverdlin 1 (0.1%) + Brad Klingerman 1 (0.1%) + Charles Perry 1 (0.1%) + Sebastian Josue Alba Vives 1 (0.1%) + Julian Braha 1 (0.1%) + yan wang 1 (0.1%) + Johannes Krottmayer 1 (0.1%) + Yixun Lan 1 (0.1%) + Jernej Skrabec 1 (0.1%) + Lukas Schmid 1 (0.1%) + Chanhong Jung 1 (0.1%) + Christoph Niedermaier 1 (0.1%) + Meiker Gao 1 (0.1%) + ht.lin 1 (0.1%) + Maximilian Brune 1 (0.1%) + Ajit Singh 1 (0.1%) + Antony Kurniawan Soemardi 1 (0.1%) + Eugen Hristev 1 (0.1%) + Levi Shafter 1 (0.1%) + Michael Zimmermann 1 (0.1%) + RafaÅ‚ Hibner 1 (0.1%) + Kuan-Wei Chiu 1 (0.1%) + Nora Schiffer 1 (0.1%) + Philippe Reynes 1 (0.1%) + Michael Opdenacker 1 (0.1%) + Matwey V. Kornilov 1 (0.1%) + Hugo Villeneuve 1 (0.1%) + Javier Viguera 1 (0.1%) + Kamlesh Gurudasani 1 (0.1%) + Cathy Xu 1 (0.1%) + Neil Berkman 1 (0.1%) + Tomas Alvarez Vanoli 1 (0.1%) + Krzysztof Kozlowski 1 (0.1%) + Javen Xu 1 (0.1%) + Miquel Raynal 1 (0.1%) + Manorit Chawdhry 1 (0.1%) + Ozan Durgut 1 (0.1%) + Abbarapu Venkatesh Yadav 1 (0.1%) + Han Xu 1 (0.1%) + Irving-CH Lin 1 (0.1%) + Caleb Ethridge 1 (0.1%) + Anton Moryakov 1 (0.1%) + Nikita Shubin 1 (0.1%) + Anurag Dutta 1 (0.1%) + Dimitrios Siganos 1 (0.1%) + Tommy Shih 1 (0.1%) + Nick Hu 1 (0.1%) + Andreas Schwab 1 (0.1%) + Ye Zhang 1 (0.1%) + Xuhui Lin 1 (0.1%) + Martin Schwan 1 (0.1%) + Sébastien Szymanski 1 (0.1%) + Ronald Wahl 1 (0.1%) + Christoph Reiter 1 (0.1%) + Jean-Marie Verdun 1 (0.1%) + Tien Fong Chee 1 (0.1%) + Naresh Kumar Ravulapalli 1 (0.1%) + ==================================== ===== + + +.. table:: Developers with the most changed lines + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Tom Rini 147099 (48.3%) + Marek Vasut 20546 (6.8%) + Simon Glass 18934 (6.2%) + Neha Malcom Francis 18915 (6.2%) + David Lechner 10414 (3.4%) + Johan Jonker 7693 (2.5%) + Peng Fan 7101 (2.3%) + Chris-QJ Chen 5103 (1.7%) + Christian Marangi 3770 (1.2%) + Michael Walle 3248 (1.1%) + Brian Sune 3146 (1.0%) + Janne Grunau 2820 (0.9%) + Primoz Fiser 2644 (0.9%) + Ernest Van Hoecke 2485 (0.8%) + Emanuele Ghidoli 2468 (0.8%) + Bo-Chen Chen 2457 (0.8%) + Finley Xiao 2132 (0.7%) + Raymond Mao 2119 (0.7%) + Alice Guo 2052 (0.7%) + Paresh Bhagat 2012 (0.7%) + Sparsh Kumar 1680 (0.6%) + Julien Masson 1589 (0.5%) + Ye Li 1554 (0.5%) + Kory Maincent 1483 (0.5%) + Dan Carpenter 1470 (0.5%) + Franz Schnyder 1460 (0.5%) + Alexander Feilke 1412 (0.5%) + Quentin Schulz 1278 (0.4%) + Balaji Selvanathan 1217 (0.4%) + Cathy Xu 1125 (0.4%) + Dario Binacchi 1094 (0.4%) + Julien Stephan 1066 (0.4%) + Jonas Karlman 1025 (0.3%) + Nguyen Tran 1012 (0.3%) + Andreas Schwab 997 (0.3%) + Brian Ruley 984 (0.3%) + Lucien.Jheng 790 (0.3%) + Heinrich Schuchardt 739 (0.2%) + Tommy Shih 647 (0.2%) + Svyatoslav Ryhel 641 (0.2%) + Torsten Duwe 591 (0.2%) + Irving-CH Lin 580 (0.2%) + Aswin Murugan 578 (0.2%) + Hrushikesh Salunke 562 (0.2%) + Richard Genoud 547 (0.2%) + Casey Connolly 538 (0.2%) + Luca Weiss 518 (0.2%) + Michal Simek 499 (0.2%) + Mathew McBride 474 (0.2%) + Ye Zhang 473 (0.2%) + Pranav Sanwal 439 (0.1%) + Markus Niebel 384 (0.1%) + Jamie Gibbons 347 (0.1%) + Rasmus Villemoes 343 (0.1%) + Max Merchel 332 (0.1%) + Varadarajan Narayanan 303 (0.1%) + Alexey Charkov 268 (0.1%) + Padmarao Begari 255 (0.1%) + Wojciech Dubowik 249 (0.1%) + Tanmay Kathpalia 216 (0.1%) + Tien Fong Chee 216 (0.1%) + Shantur Rathore 208 (0.1%) + Paul Gerber 206 (0.1%) + Mikhail Kshevetskiy 186 (0.1%) + Markus Schneider-Pargmann (TI) 177 (0.1%) + Francesco Dolcini 171 (0.1%) + Vincent Stehlé 165 (0.1%) + Tze Yee Ng 156 (0.1%) + Anshul Dalal 136 (0.0%) + Javier Martinez Canillas 129 (0.0%) + Noah.Shen 128 (0.0%) + Adrian Freihofer 121 (0.0%) + Sean Anderson 120 (0.0%) + Martin Schwan 114 (0.0%) + Heiko Schocher 112 (0.0%) + Pranav Tilak 111 (0.0%) + Christian Pötzsch 105 (0.0%) + Miquel Raynal 101 (0.0%) + Paul HENRYS 96 (0.0%) + Mateusz Furdyna 92 (0.0%) + Shiva Tripathi 88 (0.0%) + Andre Przywara 85 (0.0%) + Johannes Krottmayer 84 (0.0%) + Angelo Dureghello 78 (0.0%) + Niko Mauno 78 (0.0%) + Christian DREHER 74 (0.0%) + Hal Feng 73 (0.0%) + Daniel Palmer 72 (0.0%) + Randolph Sapp 69 (0.0%) + Francois Berder 68 (0.0%) + Ion Agorria 67 (0.0%) + Lukas Stockmann 59 (0.0%) + Paul Kocialkowski 59 (0.0%) + Michele Bisogno 58 (0.0%) + Federico Amedeo Izzo 56 (0.0%) + Philip Molloy 54 (0.0%) + Sumit Garg 53 (0.0%) + Manorit Chawdhry 50 (0.0%) + E Shattow 49 (0.0%) + Chunguang Li 48 (0.0%) + Peter Collingbourne 48 (0.0%) + Alif Zakuan Yuslaimi 47 (0.0%) + Ngo Luong Thanh Tra 45 (0.0%) + Prashant Kamble 41 (0.0%) + Dinesh Maniyam 40 (0.0%) + Gregor Herburger 38 (0.0%) + Jonas Schwöbel 36 (0.0%) + Ioana Ciornei 34 (0.0%) + RafaÅ‚ MiÅ‚ecki 33 (0.0%) + Ssunk 29 (0.0%) + Jeffrey Yu 26 (0.0%) + Vitor Soares 25 (0.0%) + Vincent Jardin 25 (0.0%) + Patrice Chotard 23 (0.0%) + Aristo Chen 23 (0.0%) + Wadim Egorov 22 (0.0%) + Siddharth Vadapalli 22 (0.0%) + Sam Shih 22 (0.0%) + Weijie Gao 22 (0.0%) + Neil Armstrong 21 (0.0%) + Suhaas Joshi 21 (0.0%) + Eugen Hristev 21 (0.0%) + Ozan Durgut 21 (0.0%) + Nora Schiffer 20 (0.0%) + Shiji Yang 19 (0.0%) + Zixun LI 19 (0.0%) + Krzysztof Kozlowski 19 (0.0%) + Christoph Reiter 19 (0.0%) + João Marcos Costa 18 (0.0%) + Boon Khai Ng 17 (0.0%) + Ludwig Nussel 15 (0.0%) + Vignesh Raghavendra 15 (0.0%) + Macpaul Lin 15 (0.0%) + Meiker Gao 14 (0.0%) + Kavin Gunasekara 13 (0.0%) + Dominik Haller 12 (0.0%) + Austin Shirley 12 (0.0%) + Ferass El Hafidi 11 (0.0%) + Charles Perry 11 (0.0%) + Chanhong Jung 11 (0.0%) + Sam Day 10 (0.0%) + Yann Gautier 10 (0.0%) + Udit Kumar 10 (0.0%) + yan wang 10 (0.0%) + Dimitrios Siganos 10 (0.0%) + Nick Hu 10 (0.0%) + Denis Mukhin 9 (0.0%) + Walter Schweizer 9 (0.0%) + Christoph Niedermaier 8 (0.0%) + Javier Viguera 8 (0.0%) + Neil Berkman 8 (0.0%) + Piyush Paliwal 7 (0.0%) + Abbarapu Venkatesh Yadav 7 (0.0%) + Peter Robinson 6 (0.0%) + Gurumoorthy Santhakumar 6 (0.0%) + Flaviu Nistor 6 (0.0%) + Yixun Lan 6 (0.0%) + Hugo Villeneuve 6 (0.0%) + Kamlesh Gurudasani 6 (0.0%) + Fabio Estevam 5 (0.0%) + Mattijs Korpershoek 5 (0.0%) + Colin Pinnell McAllister 5 (0.0%) + Raphaël Gallais-Pou 5 (0.0%) + Alexander Sverdlin 5 (0.0%) + Antony Kurniawan Soemardi 5 (0.0%) + Anurag Dutta 5 (0.0%) + Ilias Apalodimas 4 (0.0%) + Andrew Goodbody 4 (0.0%) + Liel Harel 4 (0.0%) + Sebastian Josue Alba Vives 4 (0.0%) + Jean-Marie Verdun 4 (0.0%) + Simona Toaca 3 (0.0%) + Chen Huei Lok 3 (0.0%) + Jan ÄŒermák 3 (0.0%) + Harsimran Singh Tungal 3 (0.0%) + Kuan-Wei Chiu 3 (0.0%) + Han Xu 3 (0.0%) + Caleb Ethridge 3 (0.0%) + Anton Moryakov 3 (0.0%) + Francesco Valla 2 (0.0%) + Vagrant Cascadian 2 (0.0%) + Ajit Singh 2 (0.0%) + Levi Shafter 2 (0.0%) + Michael Zimmermann 2 (0.0%) + Matwey V. Kornilov 2 (0.0%) + Nikita Shubin 2 (0.0%) + Quentin Strydom 1 (0.0%) + Heiko Stuebner 1 (0.0%) + Petr Hodina 1 (0.0%) + Frank Böwingloh 1 (0.0%) + Frieder Schrempf 1 (0.0%) + Andrea della Porta 1 (0.0%) + Giovanni Santini 1 (0.0%) + Tony Dinh 1 (0.0%) + Lionel Debieve 1 (0.0%) + Moteen Shah 1 (0.0%) + Mark Kettenis 1 (0.0%) + Brad Klingerman 1 (0.0%) + Julian Braha 1 (0.0%) + Jernej Skrabec 1 (0.0%) + Lukas Schmid 1 (0.0%) + ht.lin 1 (0.0%) + Maximilian Brune 1 (0.0%) + RafaÅ‚ Hibner 1 (0.0%) + Philippe Reynes 1 (0.0%) + Michael Opdenacker 1 (0.0%) + Tomas Alvarez Vanoli 1 (0.0%) + Javen Xu 1 (0.0%) + Xuhui Lin 1 (0.0%) + Sébastien Szymanski 1 (0.0%) + Ronald Wahl 1 (0.0%) + Naresh Kumar Ravulapalli 1 (0.0%) + ==================================== ===== + + +.. table:: Developers with the most lines removed + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Simon Glass 16011 (17.5%) + Johan Jonker 7611 (8.3%) + Michael Walle 2998 (3.3%) + Janne Grunau 2599 (2.8%) + Ernest Van Hoecke 2348 (2.6%) + Franz Schnyder 1428 (1.6%) + Andreas Schwab 981 (1.1%) + Quentin Schulz 936 (1.0%) + Mathew McBride 319 (0.3%) + Francesco Dolcini 141 (0.2%) + Max Merchel 135 (0.1%) + Svyatoslav Ryhel 115 (0.1%) + Tanmay Kathpalia 101 (0.1%) + Zixun LI 18 (0.0%) + Aristo Chen 16 (0.0%) + Lukas Stockmann 15 (0.0%) + Weijie Gao 14 (0.0%) + Meiker Gao 14 (0.0%) + Wadim Egorov 12 (0.0%) + RafaÅ‚ MiÅ‚ecki 11 (0.0%) + João Marcos Costa 11 (0.0%) + Nick Hu 10 (0.0%) + Javier Viguera 7 (0.0%) + Siddharth Vadapalli 6 (0.0%) + Chanhong Jung 5 (0.0%) + Alexander Sverdlin 1 (0.0%) + ==================================== ===== + + +.. table:: Developers with the most signoffs (total 321) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Peng Fan 59 (18.4%) + David Lechner 45 (14.0%) + Casey Connolly 40 (12.5%) + Michal Simek 26 (8.1%) + Neil Armstrong 20 (6.2%) + Siddharth Vadapalli 10 (3.1%) + Mattijs Korpershoek 10 (3.1%) + Ilias Apalodimas 9 (2.8%) + Alice Guo 8 (2.5%) + Max Merchel 7 (2.2%) + Svyatoslav Ryhel 7 (2.2%) + Heiko Schocher 7 (2.2%) + Heiko Stuebner 4 (1.2%) + Macpaul Lin 4 (1.2%) + Anshul Dalal 4 (1.2%) + Jonas Karlman 4 (1.2%) + Ye Li 4 (1.2%) + Tom Rini 4 (1.2%) + Weijie Gao 3 (0.9%) + Walter Schweizer 3 (0.9%) + Adam Lackorzynski 2 (0.6%) + Meet Patel 2 (0.6%) + Shawn Guo 2 (0.6%) + Udit Kumar 2 (0.6%) + Julien Stephan 2 (0.6%) + Marek Vasut 2 (0.6%) + Simon Glass 1 (0.3%) + Michael Walle 1 (0.3%) + Ernest Van Hoecke 1 (0.3%) + Francesco Dolcini 1 (0.3%) + ht.lin 1 (0.3%) + AngeloGioacchino Del Regno 1 (0.3%) + Jerome Forissier 1 (0.3%) + Huy Bui 1 (0.3%) + Patrick Delaunay 1 (0.3%) + Keerthy 1 (0.3%) + Takuma Fujiwara 1 (0.3%) + Steffen Doster 1 (0.3%) + John Toomey 1 (0.3%) + Harini Katakam 1 (0.3%) + Venkatesh Yadav Abbarapu 1 (0.3%) + Mahammed Sadik Shaik 1 (0.3%) + Jimmy Ho 1 (0.3%) + Elaine Zhang 1 (0.3%) + Chen Huei Lok 1 (0.3%) + Yann Gautier 1 (0.3%) + Sumit Garg 1 (0.3%) + Andre Przywara 1 (0.3%) + Alexey Charkov 1 (0.3%) + Aswin Murugan 1 (0.3%) + Torsten Duwe 1 (0.3%) + Heinrich Schuchardt 1 (0.3%) + Balaji Selvanathan 1 (0.3%) + Alexander Feilke 1 (0.3%) + Paresh Bhagat 1 (0.3%) + Bo-Chen Chen 1 (0.3%) + Brian Sune 1 (0.3%) + ==================================== ===== + + +.. table:: Developers with the most reviews (total 791) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Julien Stephan 100 (12.6%) + Simon Glass 90 (11.4%) + Tom Rini 53 (6.7%) + Peng Fan 50 (6.3%) + Ilias Apalodimas 46 (5.8%) + Kever Yang 41 (5.2%) + Macpaul Lin 34 (4.3%) + Neil Armstrong 33 (4.2%) + Quentin Schulz 33 (4.2%) + Marek Vasut 24 (3.0%) + Sumit Garg 23 (2.9%) + Heinrich Schuchardt 22 (2.8%) + Mattijs Korpershoek 17 (2.1%) + Jerome Forissier 17 (2.1%) + Patrice Chotard 16 (2.0%) + Casey Connolly 15 (1.9%) + Peter Robinson 14 (1.8%) + Tien Fong Chee 11 (1.4%) + Heiko Schocher 9 (1.1%) + Leo Yu-Chi Liang 8 (1.0%) + Varadarajan Narayanan 8 (1.0%) + Francesco Dolcini 7 (0.9%) + João Marcos Costa 7 (0.9%) + Miquel Raynal 7 (0.9%) + Udit Kumar 6 (0.8%) + Anshul Dalal 5 (0.6%) + Andre Przywara 5 (0.6%) + Conor Dooley 5 (0.6%) + Paul Kocialkowski 5 (0.6%) + Raymond Mao 4 (0.5%) + Neha Malcom Francis 4 (0.5%) + Jonas Karlman 3 (0.4%) + Alexander Sverdlin 3 (0.4%) + Michael Trimarchi 3 (0.4%) + Greg Malysa 3 (0.4%) + E Shattow 3 (0.4%) + Kory Maincent 3 (0.4%) + Patrick Delaunay 2 (0.3%) + Jernej Skrabec 2 (0.3%) + Matthias Brugger 2 (0.3%) + Stefan Roese 2 (0.3%) + Yannic Moog 2 (0.3%) + Teresa Remmet 2 (0.3%) + Bryan Brattlof 2 (0.3%) + David Zang 2 (0.3%) + Raphaël Gallais-Pou 2 (0.3%) + Hal Feng 2 (0.3%) + Rasmus Villemoes 2 (0.3%) + Svyatoslav Ryhel 1 (0.1%) + Weijie Gao 1 (0.1%) + AngeloGioacchino Del Regno 1 (0.1%) + Manorit Chawdhry 1 (0.1%) + Kuan-Wei Chiu 1 (0.1%) + Thomas Petazzoni 1 (0.1%) + Andy Shevchenko 1 (0.1%) + Romain Naour 1 (0.1%) + Sebastian Reichel 1 (0.1%) + Bin Meng 1 (0.1%) + Ivan T. Ivanov 1 (0.1%) + Manikandan Muralidharan 1 (0.1%) + Javier Tia 1 (0.1%) + Alexander Dahl 1 (0.1%) + Dhruva Gole 1 (0.1%) + Christian Taedcke 1 (0.1%) + Wolfgang Wallner 1 (0.1%) + Linus Walleij 1 (0.1%) + Daniel Schwierzeck 1 (0.1%) + Tianrui Wei 1 (0.1%) + Shawn Lin 1 (0.1%) + Christopher Obbard 1 (0.1%) + Benjamin Hahn 1 (0.1%) + Radhey Shyam Pandey 1 (0.1%) + Tomas Melin 1 (0.1%) + Frieder Schrempf 1 (0.1%) + Tony Dinh 1 (0.1%) + Sam Day 1 (0.1%) + Sean Anderson 1 (0.1%) + Markus Schneider-Pargmann (TI) 1 (0.1%) + Lucien.Jheng 1 (0.1%) + Primoz Fiser 1 (0.1%) + ==================================== ===== + + +.. table:: Developers with the most test credits (total 94) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Julien Stephan 21 (22.3%) + Pedro Falcato 9 (9.6%) + Ilias Apalodimas 7 (7.4%) + Michal Simek 7 (7.4%) + Udit Kumar 6 (6.4%) + Anshul Dalal 6 (6.4%) + Dario Binacchi 6 (6.4%) + Wei Lu 4 (4.3%) + Aaron Griffith 4 (4.3%) + Neil Armstrong 3 (3.2%) + Peter Robinson 2 (2.1%) + Yannic Moog 2 (2.1%) + Quentin Schulz 1 (1.1%) + Marek Vasut 1 (1.1%) + Heinrich Schuchardt 1 (1.1%) + Mattijs Korpershoek 1 (1.1%) + Francesco Dolcini 1 (1.1%) + Andre Przywara 1 (1.1%) + Weijie Gao 1 (1.1%) + Kuan-Wei Chiu 1 (1.1%) + Wolfgang Wallner 1 (1.1%) + Ernest Van Hoecke 1 (1.1%) + Alexey Charkov 1 (1.1%) + Stefan Bosch 1 (1.1%) + Sughosh Ganu 1 (1.1%) + Ferass El Hafidi 1 (1.1%) + Angelo Dureghello 1 (1.1%) + Padmarao Begari 1 (1.1%) + Emanuele Ghidoli 1 (1.1%) + ==================================== ===== + + +.. table:: Developers who gave the most tested-by credits (total 94) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + David Lechner 21 (22.3%) + Raymond Mao 12 (12.8%) + Torsten Duwe 8 (8.5%) + Kory Maincent 7 (7.4%) + Neha Malcom Francis 6 (6.4%) + Ye Li 5 (5.3%) + Peng Fan 4 (4.3%) + Rasmus Villemoes 4 (4.3%) + Jonas Karlman 3 (3.2%) + Michal Simek 2 (2.1%) + Heinrich Schuchardt 2 (2.1%) + Simon Glass 2 (2.1%) + Siddharth Vadapalli 2 (2.1%) + Shantur Rathore 2 (2.1%) + Neil Armstrong 1 (1.1%) + Quentin Schulz 1 (1.1%) + Marek Vasut 1 (1.1%) + Sam Day 1 (1.1%) + ht.lin 1 (1.1%) + Wadim Egorov 1 (1.1%) + Andrea della Porta 1 (1.1%) + Xuhui Lin 1 (1.1%) + Liel Harel 1 (1.1%) + Abbarapu Venkatesh Yadav 1 (1.1%) + Ngo Luong Thanh Tra 1 (1.1%) + Francois Berder 1 (1.1%) + Daniel Palmer 1 (1.1%) + Ye Zhang 1 (1.1%) + ==================================== ===== + + +.. table:: Developers with the most report credits (total 15) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Simon Glass 3 (20.0%) + Julien Stephan 1 (6.7%) + Weijie Gao 1 (6.7%) + Tom Rini 1 (6.7%) + Yann Gautier 1 (6.7%) + Franz Schnyder 1 (6.7%) + Rudy Andram 1 (6.7%) + Mariusz Madej 1 (6.7%) + Anas Cherni 1 (6.7%) + Philippe Simons 1 (6.7%) + Yuya Hamamachi 1 (6.7%) + Christoph Niedermaier 1 (6.7%) + Suhaas Joshi 1 (6.7%) + ==================================== ===== + + +.. table:: Developers who gave the most report credits (total 15) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + David Lechner 3 (20.0%) + Heinrich Schuchardt 3 (20.0%) + Marek Vasut 2 (13.3%) + Rasmus Villemoes 1 (6.7%) + Michal Simek 1 (6.7%) + Quentin Schulz 1 (6.7%) + Anshul Dalal 1 (6.7%) + Patrice Chotard 1 (6.7%) + Jernej Skrabec 1 (6.7%) + Mateusz Furdyna 1 (6.7%) + ==================================== ===== + + +.. table:: Top changeset contributors by employer + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 506 (38.1%) + BayLibre SAS 179 (13.5%) + Canonical 98 (7.4%) + Konsulko Group 96 (7.2%) + NXP 93 (7.0%) + Renesas Electronics 64 (4.8%) + Texas Instruments 60 (4.5%) + AMD 48 (3.6%) + Toradex 32 (2.4%) + Bootlin 27 (2.0%) + Linaro 23 (1.7%) + Amarula Solutions 19 (1.4%) + ARM 16 (1.2%) + Siemens 16 (1.2%) + ST Microelectronics 11 (0.8%) + SUSE 10 (0.8%) + Phytec 8 (0.6%) + Red Hat 7 (0.5%) + Rockchip 4 (0.3%) + Analog Devices 3 (0.2%) + Debian.org 2 (0.2%) + linutronix 2 (0.2%) + Nokia 2 (0.2%) + Digi International 1 (0.1%) + Gentoo 1 (0.1%) + ==================================== ===== + + +.. table:: Top lines changed by employer + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + Konsulko Group 147099 (48.3%) + (Unknown) 52846 (17.4%) + Texas Instruments 23592 (7.8%) + Renesas Electronics 19393 (6.4%) + Canonical 18957 (6.2%) + BayLibre SAS 13246 (4.4%) + NXP 10795 (3.5%) + Toradex 6609 (2.2%) + Rockchip 2606 (0.9%) + Bootlin 2149 (0.7%) + Linaro 2037 (0.7%) + SUSE 1589 (0.5%) + AMD 1304 (0.4%) + Amarula Solutions 1094 (0.4%) + ARM 266 (0.1%) + Siemens 209 (0.1%) + Phytec 148 (0.0%) + Red Hat 129 (0.0%) + Nokia 92 (0.0%) + Analog Devices 57 (0.0%) + linutronix 38 (0.0%) + ST Microelectronics 34 (0.0%) + Digi International 8 (0.0%) + Gentoo 6 (0.0%) + Debian.org 2 (0.0%) + ==================================== ===== + + +.. table:: Employers with the most signoffs (total 321) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + NXP 71 (22.1%) + Linaro 69 (21.5%) + (Unknown) 62 (19.3%) + BayLibre SAS 47 (14.6%) + AMD 29 (9.0%) + Texas Instruments 20 (6.2%) + Konsulko Group 4 (1.2%) + ARM 4 (1.2%) + Renesas Electronics 3 (0.9%) + Siemens 3 (0.9%) + Canonical 2 (0.6%) + Toradex 2 (0.6%) + ST Microelectronics 2 (0.6%) + Rockchip 1 (0.3%) + SUSE 1 (0.3%) + Collabora Ltd. 1 (0.3%) + ==================================== ===== + + +.. table:: Employers with the most hackers (total 213) + :widths: auto + + ==================================== ===== + Name Count + ==================================== ===== + (Unknown) 134 (62.9%) + Texas Instruments 15 (7.0%) + NXP 7 (3.3%) + Linaro 5 (2.3%) + Siemens 5 (2.3%) + Toradex 5 (2.3%) + BayLibre SAS 4 (1.9%) + AMD 4 (1.9%) + ARM 4 (1.9%) + Bootlin 4 (1.9%) + ST Microelectronics 3 (1.4%) + Rockchip 3 (1.4%) + SUSE 3 (1.4%) + Phytec 3 (1.4%) + Renesas Electronics 2 (0.9%) + Canonical 2 (0.9%) + Analog Devices 2 (0.9%) + Konsulko Group 1 (0.5%) + Amarula Solutions 1 (0.5%) + Red Hat 1 (0.5%) + Nokia 1 (0.5%) + linutronix 1 (0.5%) + Digi International 1 (0.5%) + Gentoo 1 (0.5%) + Debian.org 1 (0.5%) + ==================================== ===== diff --git a/doc/develop/testing.rst b/doc/develop/testing.rst index 3a2b496fa00..1d19b49e82c 100644 --- a/doc/develop/testing.rst +++ b/doc/develop/testing.rst @@ -22,7 +22,7 @@ the quick ones, type this:: make qcheck -It is also possible to run just the tests for tools (patman, binman, etc.). +It is also possible to run just the tests for tools (binman, buildman, etc.). Such tests are included with those tools, i.e. no actual U-Boot unit tests are run. Type this:: diff --git a/doc/usage/cmd/reset.rst b/doc/usage/cmd/reset.rst index 79bc8b9deca..78c9c8873bc 100644 --- a/doc/usage/cmd/reset.rst +++ b/doc/usage/cmd/reset.rst @@ -11,9 +11,7 @@ Synopsis :: - reset - reset -w - reset -edl + reset [-w] Description ----------- @@ -24,12 +22,6 @@ DDR and peripherals, on some boards also resets external PMIC. -w Do WARM reset: reset CPU but keep peripheral/DDR/PMIC active. -All other options require CONFIG_SYSRESET_CMD_RESET_ARGS=y. - --edl - Boot to Emergency DownLoad mode on supported Qualcomm platforms. Unsupported - platforms will print an error message but the command will successfully - return (having done nothing). Requires CONFIG_SYSRESET_QCOM_PSCI=y. Return value ------------ diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig index 2b45f9e5eba..d5ef0795401 100644 --- a/drivers/adc/Kconfig +++ b/drivers/adc/Kconfig @@ -5,7 +5,7 @@ config ADC This enables ADC API for drivers, which allows driving ADC features by single and multi-channel methods for: - start/stop/get data for conversion of a single-channel selected by - a number or multi-channels selected by a bitmask + a number or multi-channels selected by a bitmask - get data mask (ADC resolution) ADC reference Voltage supply options: - methods for get Vdd/Vss reference Voltage values with polarity diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index adf338ab00c..d44cf4bcb6b 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -68,10 +68,10 @@ config BLKMAP bool "Composable virtual block devices (blkmap)" depends on BLK help - Create virtual block devices that are backed by various sources, - e.g. RAM, or parts of an existing block device. Though much more - rudimentary, it borrows a lot of ideas from Linux's device mapper - subsystem. + Create virtual block devices that are backed by various sources, + e.g. RAM, or parts of an existing block device. Though much more + rudimentary, it borrows a lot of ideas from Linux's device mapper + subsystem. Example use-cases: - Treat a region of RAM as a block device, i.e. a RAM disk. This let's diff --git a/drivers/block/Makefile b/drivers/block/Makefile index f5a9d8637a3..c827fa81a2d 100644 --- a/drivers/block/Makefile +++ b/drivers/block/Makefile @@ -13,7 +13,7 @@ ifndef CONFIG_XPL_BUILD obj-$(CONFIG_IDE) += ide.o obj-$(CONFIG_RKMTD) += rkmtd.o endif -obj-$(CONFIG_SANDBOX) += sandbox.o host-uclass.o host_dev.o +obj-$(CONFIG_SANDBOX) += sandbox.o sandbox-bootdev.o host-uclass.o host_dev.o obj-$(CONFIG_$(PHASE_)BLOCK_CACHE) += blkcache.o obj-$(CONFIG_$(PHASE_)BLKMAP) += blkmap.o obj-$(CONFIG_$(PHASE_)BLKMAP) += blkmap_helper.o diff --git a/drivers/block/host-uclass.c b/drivers/block/host-uclass.c index cf42bd1e07a..95b0b0b2ffe 100644 --- a/drivers/block/host-uclass.c +++ b/drivers/block/host-uclass.c @@ -150,6 +150,21 @@ struct udevice *host_find_by_label(const char *label) return NULL; } +int host_set_flags_by_label(const char *label, unsigned int flags) +{ + struct udevice *dev; + struct host_sb_plat *plat; + + dev = host_find_by_label(label); + if (!dev) + return -ENODEV; + + plat = dev_get_plat(dev); + plat->flags = flags; + + return 0; +} + struct udevice *host_get_cur_dev(void) { struct uclass *uc = uclass_find(UCLASS_HOST); diff --git a/drivers/block/sandbox-bootdev.c b/drivers/block/sandbox-bootdev.c new file mode 100644 index 00000000000..15af0c17d1f --- /dev/null +++ b/drivers/block/sandbox-bootdev.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0+ + +#define LOG_CATEGORY UCLASS_HOST + +#include <bootdev.h> +#include <dm.h> +#include <log.h> +#include <sandbox_host.h> + +static int sandbox_bootdev_bind(struct udevice *dev) +{ + struct bootdev_uc_plat *ucp = dev_get_uclass_plat(dev); + + ucp->prio = BOOTDEVP_4_SCAN_FAST; + + return 0; +} + +/** + * sandbox_bootdev_hunt() - Hunt host bootdev. + * + * Note, this hunter exists for bootdev testing to simulate a failure + * mode. Do not use as an example of a real hunter. + * + * @info: Hunter details. + * @show: Enable extra printouts. + * + * Returns: 0 if OK, -ve on error (expected by the test) + */ +static int sandbox_bootdev_hunt(struct bootdev_hunter *info, bool show) +{ + struct udevice *dev; + struct uclass *uc; + int ret; + + uclass_id_foreach_dev(UCLASS_HOST, dev, uc) { + struct host_sb_plat *plat = dev_get_plat(dev); + + log_debug("hunting %s\n", plat->label); + + if (plat->flags & HOST_FLAG_BROKEN) { + ret = -ETIME; + log_debug("cannot hunt sandbox device '%s': %d\n", + plat->label, ret); + return ret; + } + } + + return 0; +} + +static const struct bootdev_ops sandbox_bootdev_ops = { +}; + +static const struct udevice_id sandbox_bootdev_ids[] = { + { .compatible = "u-boot,bootdev-sandbox" }, + { } +}; + +U_BOOT_DRIVER(sandbox_bootdev) = { + .name = "sandbox_bootdev", + .id = UCLASS_BOOTDEV, + .ops = &sandbox_bootdev_ops, + .bind = sandbox_bootdev_bind, + .of_match = sandbox_bootdev_ids, +}; + +BOOTDEV_HUNTER(sandbox_bootdev_hunter) = { + .prio = BOOTDEVP_4_SCAN_FAST, + .uclass = UCLASS_HOST, + .hunt = sandbox_bootdev_hunt, + .drv = DM_DRIVER_REF(sandbox_bootdev), +}; diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig index 4c0c8d89bb4..af6bd2f1a7d 100644 --- a/drivers/bootcount/Kconfig +++ b/drivers/bootcount/Kconfig @@ -68,7 +68,7 @@ config BOOTCOUNT_ENV saveenv on all reboots, the environment variable "upgrade_available" is used. If "upgrade_available" is 0, "bootcount" is always 0. If "upgrade_available" is 1, - "bootcount" is incremented in the environment. + "bootcount" is incremented in the environment. So the Userspace Application must set the "upgrade_available" and "bootcount" variables to 0, if the system booted successfully. @@ -83,7 +83,7 @@ config BOOTCOUNT_AT91 depends on AT91SAM9XE config DM_BOOTCOUNT - bool "Boot counter in a device-model device" + bool "Boot counter in a device-model device" help Enables reading/writing the bootcount in a device-model based backing store. If an entry in /chosen/u-boot,bootcount-device diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig index 3bf5c7f5dbf..5ebc8842acd 100644 --- a/drivers/cache/Kconfig +++ b/drivers/cache/Kconfig @@ -14,7 +14,7 @@ config CACHE configuring settings that be found from a device tree file. config L2X0_CACHE - tristate "PL310 cache driver" + bool "PL310 cache driver" select CACHE depends on ARM help diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index c2da7b3938b..e69b0543817 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -134,8 +134,8 @@ config CLK_CDCE9XX bool "Enable CDCD9XX clock driver" depends on CLK && ARCH_OMAP2PLUS help - Enable the clock synthesizer driver for CDCE913/925/937/949 - series of chips. + Enable the clock synthesizer driver for CDCE913/925/937/949 + series of chips. config CLK_ICS8N3QV01 bool "Enable ICS8N3QV01 VCXO driver" @@ -216,7 +216,7 @@ config CLK_HSDK Synopsys ARC HSDK-4xD boards config CLK_VERSACLOCK - tristate "Enable VersaClock 5/6 devices" + bool "Enable VersaClock 5/6 devices" depends on CLK depends on CLK_CCF depends on OF_CONTROL diff --git a/drivers/clk/aspeed/Makefile b/drivers/clk/aspeed/Makefile index 84776e5265e..285180b67cf 100644 --- a/drivers/clk/aspeed/Makefile +++ b/drivers/clk/aspeed/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_ASPEED_AST2500) += clk_ast2500.o obj-$(CONFIG_ASPEED_AST2600) += clk_ast2600.o +obj-$(CONFIG_ASPEED_AST2700) += clk_ast2700.o diff --git a/drivers/clk/aspeed/clk_ast2700.c b/drivers/clk/aspeed/clk_ast2700.c new file mode 100644 index 00000000000..ca76abef48f --- /dev/null +++ b/drivers/clk/aspeed/clk_ast2700.c @@ -0,0 +1,952 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <asm/io.h> +#include <asm/arch/scu_ast2700.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <syscon.h> +#include <linux/bitfield.h> + +#include <dt-bindings/clock/aspeed,ast2700-scu.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * RGMII clock source tree + * HPLL -->|\ + * | |---->| divider |---->RGMII 125M for MAC#0 & MAC#1 + * APLL -->|/ + */ +#define RGMII_DEFAULT_CLK_SRC SCU1_CLK_HPLL + +struct mac_delay_config { + u32 tx_delay_1000; + u32 rx_delay_1000; + u32 tx_delay_100; + u32 rx_delay_100; + u32 tx_delay_10; + u32 rx_delay_10; +}; + +typedef int (*ast2700_clk_init_fn)(struct udevice *dev); + +struct ast2700_clk_priv { + void __iomem *reg; + ast2700_clk_init_fn init; +}; + +static u32 ast2700_soc1_get_pll_rate(struct ast2700_scu1 *scu, int pll_idx) +{ + union ast2700_pll_reg pll_reg; + u32 mul = 1, div = 1; + + switch (pll_idx) { + case SCU1_CLK_HPLL: + pll_reg.w = readl(&scu->hpll); + break; + case SCU1_CLK_APLL: + pll_reg.w = readl(&scu->apll); + break; + case SCU1_CLK_DPLL: + pll_reg.w = readl(&scu->dpll); + break; + } + + if (!pll_reg.b.bypass) { + mul = (pll_reg.b.m + 1) / (pll_reg.b.n + 1); + div = (pll_reg.b.p + 1); + } + + return ((CLKIN_25M * mul) / div); +} + +#define SCU_CLKSEL2_HCLK_DIV_MASK GENMASK(22, 20) +#define SCU_CLKSEL2_HCLK_DIV_SHIFT 20 + +static u32 ast2700_soc1_get_hclk_rate(struct ast2700_scu1 *scu) +{ + u32 rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 clk_sel2 = readl(&scu->clk_sel2); + u32 hclk_div = (clk_sel2 & SCU_CLKSEL2_HCLK_DIV_MASK) >> + SCU_CLKSEL2_HCLK_DIV_SHIFT; + + if (!hclk_div) + hclk_div = 2; + else + hclk_div++; + + return (rate / hclk_div); +} + +#define SCU1_CLKSEL1_PCLK_DIV_MASK GENMASK(20, 18) +#define SCU1_CLKSEL1_PCLK_DIV_SHIFT 18 + +static u32 ast2700_soc1_get_pclk_rate(struct ast2700_scu1 *scu) +{ + u32 rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + + u32 clk_sel1 = readl(&scu->clk_sel1); + u32 pclk_div = (clk_sel1 & SCU1_CLKSEL1_PCLK_DIV_MASK) >> + SCU1_CLKSEL1_PCLK_DIV_SHIFT; + + return (rate / ((pclk_div + 1) * 2)); +} + +#define SCU_UART_CLKGEN_N_MASK GENMASK(17, 8) +#define SCU_UART_CLKGEN_N_SHIFT 8 +#define SCU_UART_CLKGEN_R_MASK GENMASK(7, 0) +#define SCU_UART_CLKGEN_R_SHIFT 0 + +static u32 ast2700_soc1_get_uart_uxclk_rate(struct ast2700_scu1 *scu) +{ + u32 uxclk_sel = readl(&scu->clk_sel2) & GENMASK(1, 0); + u32 uxclk_ctrl = readl(&scu->uxclk_ctrl); + u32 rate; + + switch (uxclk_sel) { + case 0: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 4; + break; + case 1: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 2; + break; + case 2: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL); + break; + case 3: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + break; + } + + u32 n = (uxclk_ctrl & SCU_UART_CLKGEN_N_MASK) >> + SCU_UART_CLKGEN_N_SHIFT; + u32 r = (uxclk_ctrl & SCU_UART_CLKGEN_R_MASK) >> + SCU_UART_CLKGEN_R_SHIFT; + + return ((rate * r) / (n * 2)); +} + +#define SCU_HUART_CLKGEN_N_MASK GENMASK(17, 8) +#define SCU_HUART_CLKGEN_N_SHIFT 8 +#define SCU_HUART_CLKGEN_R_MASK GENMASK(7, 0) +#define SCU_HUART_CLKGEN_R_SHIFT 0 + +static u32 ast2700_soc1_get_uart_huxclk_rate(struct ast2700_scu1 *scu) +{ + u32 huxclk_sel = (readl(&scu->clk_sel2) & GENMASK(4, 3)) >> 3; + u32 huxclk_ctrl = readl(&scu->huxclk_ctrl); + u32 n = (huxclk_ctrl & SCU_HUART_CLKGEN_N_MASK) >> + SCU_HUART_CLKGEN_N_SHIFT; + u32 r = (huxclk_ctrl & SCU_HUART_CLKGEN_R_MASK) >> + SCU_HUART_CLKGEN_R_SHIFT; + u32 rate; + + switch (huxclk_sel) { + case 0: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 4; + break; + case 1: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL) / 2; + break; + case 2: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL); + break; + case 3: + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + break; + } + + return ((rate * r) / (n * 2)); +} + +#define SCU_CLKSRC1_SDIO_DIV_MASK GENMASK(16, 14) +#define SCU_CLKSRC1_SDIO_DIV_SHIFT 14 +#define SCU_CLKSRC1_SDIO_SEL BIT(13) +const int ast2700_sd_div_tbl[] = { + 2, 2, 3, 4, 5, 6, 7, 8 +}; + +static u32 ast2700_soc1_get_sdio_clk_rate(struct ast2700_scu1 *scu) +{ + u32 rate = 0; + u32 clk_sel1 = readl(&scu->clk_sel1); + u32 div = (clk_sel1 & SCU_CLKSRC1_SDIO_DIV_MASK) >> + SCU_CLKSRC1_SDIO_DIV_SHIFT; + + if (clk_sel1 & SCU_CLKSRC1_SDIO_SEL) + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_APLL); + else + rate = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + + if (!div) + div = 1; + + div++; + + return (rate / div); +} + +static void ast2700_init_sdclk(struct ast2700_scu1 *scu) +{ + u32 src_clk = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 reg_280; + int i; + + for (i = 0; i < 8; i++) { + if (src_clk / ast2700_sd_div_tbl[i] <= 125000000) + break; + } + + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~(SCU_CLKSRC1_SDIO_DIV_MASK | SCU_CLKSRC1_SDIO_SEL); + reg_280 |= i << SCU_CLKSRC1_SDIO_DIV_SHIFT; + writel(reg_280, &scu->clk_sel1); +} + +static u32 +ast2700_soc1_get_uart_clk_rate(struct ast2700_scu1 *scu, int uart_idx) +{ + u32 rate = 0; + + if (readl(&scu->clk_sel1) & BIT(uart_idx)) + rate = ast2700_soc1_get_uart_huxclk_rate(scu); + else + rate = ast2700_soc1_get_uart_uxclk_rate(scu); + + return rate; +} + +static ulong ast2700_soc1_clk_get_rate(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + struct ast2700_scu1 *scu = (struct ast2700_scu1 *)priv->reg; + ulong rate = 0; + + switch (clk->id) { + case SCU1_CLK_HPLL: + case SCU1_CLK_APLL: + case SCU1_CLK_DPLL: + rate = ast2700_soc1_get_pll_rate(scu, clk->id); + break; + case SCU1_CLK_AHB: + rate = ast2700_soc1_get_hclk_rate(scu); + break; + case SCU1_CLK_APB: + rate = ast2700_soc1_get_pclk_rate(scu); + break; + case SCU1_CLK_GATE_UART0CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 0); + break; + case SCU1_CLK_GATE_UART1CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 1); + break; + case SCU1_CLK_GATE_UART2CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 2); + break; + case SCU1_CLK_GATE_UART3CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 3); + break; + case SCU1_CLK_GATE_UART5CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 5); + break; + case SCU1_CLK_GATE_UART6CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 6); + break; + case SCU1_CLK_GATE_UART7CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 7); + break; + case SCU1_CLK_GATE_UART8CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 8); + break; + case SCU1_CLK_GATE_UART9CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 9); + break; + case SCU1_CLK_GATE_UART10CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 10); + break; + case SCU1_CLK_GATE_UART11CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 11); + break; + case SCU1_CLK_GATE_UART12CLK: + rate = ast2700_soc1_get_uart_clk_rate(scu, 12); + break; + case SCU1_CLK_GATE_SDCLK: + rate = ast2700_soc1_get_sdio_clk_rate(scu); + break; + case SCU1_CLK_UXCLK: + rate = ast2700_soc1_get_uart_uxclk_rate(scu); + break; + case SCU1_CLK_HUXCLK: + rate = ast2700_soc1_get_uart_huxclk_rate(scu); + break; + default: + debug("%s: unknown clk %ld\n", __func__, clk->id); + return -ENOENT; + } + + return rate; +} + +static int ast2700_soc1_clk_enable(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + struct ast2700_scu1 *scu = (struct ast2700_scu1 *)priv->reg; + u32 clkgate_bit; + + if (clk->id >= 32) + clkgate_bit = BIT(clk->id - 32); + else + clkgate_bit = BIT(clk->id); + + writel(clkgate_bit, &scu->clkgate_clr1); + + return 0; +} + +static const struct clk_ops ast2700_soc1_clk_ops = { + .get_rate = ast2700_soc1_clk_get_rate, + .enable = ast2700_soc1_clk_enable, +}; + +#define SCU_HW_REVISION_ID GENMASK(23, 16) +#define SCU_CPUCLK_MASK GENMASK(4, 2) +#define SCU_CPUCLK_SHIFT 2 +static u32 ast2700_soc0_get_hpll_rate(struct ast2700_scu0 *scu) +{ + u32 chip_id1 = readl(&scu->chip_id1); + u32 hwstrap1 = readl(&scu->hwstrap1); + union ast2700_pll_reg pll_reg; + u32 mul = 1, div = 1; + u32 rate; + + pll_reg.w = readl(&scu->hpll); + + if ((chip_id1 & SCU_HW_REVISION_ID) && (hwstrap1 & BIT(3))) { + switch ((hwstrap1 & GENMASK(4, 2)) >> 2) { + case 2: + rate = 1800000000; + break; + case 3: + rate = 1700000000; + break; + case 6: + rate = 1200000000; + break; + case 7: + rate = 800000000; + break; + default: + rate = 1600000000; + } + } else if (hwstrap1 & GENMASK(3, 2)) { + switch ((hwstrap1 & GENMASK(3, 2)) >> 2) { + case 1U: + rate = 1900000000; + break; + case 2U: + rate = 1800000000; + break; + case 3U: + rate = 1700000000; + break; + default: + rate = 1600000000; + break; + } + } else { + if (pll_reg.b.bypass == 0U) { + /* F = 25Mhz * [(M + 2) / 2 * (n + 1)] / (p + 1) */ + mul = (pll_reg.b.m + 1) / ((pll_reg.b.n + 1) * 2); + div = (pll_reg.b.p + 1); + } + rate = ((CLKIN_25M * mul) / div); + } + + return rate; +} + +static u32 ast2700_soc0_get_pll_rate(struct ast2700_scu0 *scu, int pll_idx) +{ + union ast2700_pll_reg pll_reg; + u32 mul = 1, div = 1; + u32 rate; + + switch (pll_idx) { + case SCU0_CLK_DPLL: + pll_reg.w = readl(&scu->dpll); + break; + case SCU0_CLK_MPLL: + pll_reg.w = readl(&scu->mpll); + break; + default: + pr_err("%s: invalid PSP clock source (%d)\n", __func__, pll_idx); + return 0; + } + + if (pll_reg.b.bypass == 0U) { + if (pll_idx == SCU0_CLK_MPLL) { + /* F = 25Mhz * [M / (n + 1)] / (p + 1) */ + mul = (pll_reg.b.m) / ((pll_reg.b.n + 1)); + div = (pll_reg.b.p + 1); + } else { + /* F = 25Mhz * [(M + 2) / 2 * (n + 1)] / (p + 1) */ + mul = (pll_reg.b.m + 1) / ((pll_reg.b.n + 1) * 2); + div = (pll_reg.b.p + 1); + } + } + + rate = ((CLKIN_25M * mul) / div); + + return rate; +} + +/* + * AST2700A1 + * SCU010[4:2]: + * 000: CPUCLK=MPLL=1.6GHz (MPLL default setting with SCU310, SCU314) + * 001: CPUCLK=HPLL=2.0GHz (HPLL default setting with SCU300, SCU304) + * 010: CPUCLK=HPLL=1.8GHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + * 011: CPUCLK=HPLL=1.7GHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + * 100: CPUCLK=MPLL/2=800MHz (MPLL default setting with SCU310, SCU314) + * 101: CPUCLK=HPLL/2=1.0GHz (HPLL default setting with SCU300, SCU304) + * 110: CPUCLK=HPLL=1.2GHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + * 111: CPUCLK=HPLL=800MHz (HPLL frequency is constance and is not controlled by SCU300, SCU304) + */ + +static u32 ast2700_soc0_get_pspclk_rate(struct ast2700_scu0 *scu) +{ + u32 chip_id1 = readl(&scu->chip_id1); + u32 hwstrap1 = readl(&scu->hwstrap1); + u32 rate; + int cpuclk_set; + + if (chip_id1 & SCU_HW_REVISION_ID) { + cpuclk_set = (hwstrap1 & SCU_CPUCLK_MASK) >> SCU_CPUCLK_SHIFT; + switch (cpuclk_set) { + case 0: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + break; + case 1: + case 2: + case 3: + case 6: + case 7: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + case 4: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 2; + break; + case 5: + rate = ast2700_soc0_get_hpll_rate(scu) / 2; + break; + default: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + } + } else { + if (hwstrap1 & BIT(4)) + rate = ast2700_soc0_get_hpll_rate(scu); + else + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + } + return rate; +} + +static u32 ast2700_soc0_get_axi0clk_rate(struct ast2700_scu0 *scu) +{ + return ast2700_soc0_get_pspclk_rate(scu) / 2; +} + +#define SCU_AHB_DIV_MASK GENMASK(6, 5) +#define SCU_AHB_DIV_SHIFT 5 +static u32 hclk_ast2700a1_div_table[] = { + 6, 5, 4, 7, +}; + +static u32 ast2700_soc0_get_hclk_rate(struct ast2700_scu0 *scu) +{ + u32 hwstrap1 = readl(&scu->hwstrap1); + u32 chip_id1 = readl(&scu->chip_id1); + u32 src_clk; + int div; + + if (chip_id1 & SCU_HW_REVISION_ID) { + if (hwstrap1 & BIT(7)) + src_clk = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + else + src_clk = ast2700_soc0_get_hpll_rate(scu); + + div = (hwstrap1 & SCU_AHB_DIV_MASK) >> SCU_AHB_DIV_SHIFT; + div = hclk_ast2700a1_div_table[div]; + } else { + if (hwstrap1 & BIT(7)) + src_clk = ast2700_soc0_get_hpll_rate(scu); + else + src_clk = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + + div = (hwstrap1 & SCU_AHB_DIV_MASK) >> SCU_AHB_DIV_SHIFT; + + if (!div) + div = 4; + else + div = (div + 1) * 2; + } + return (src_clk / div); +} + +static u32 ast2700_soc0_get_axi1clk_rate(struct ast2700_scu0 *scu) +{ + if (readl(&scu->chip_id1) & SCU_HW_REVISION_ID) + return ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 4; + else + return ast2700_soc0_get_hclk_rate(scu); +} + +#define SCU0_CLKSEL1_PCLK_DIV_MASK GENMASK(25, 23) +#define SCU0_CLKSEL1_PCLK_DIV_SHIFT 23 + +static u32 ast2700_soc0_get_pclk_rate(struct ast2700_scu0 *scu) +{ + u32 rate = ast2700_soc0_get_axi0clk_rate(scu); + u32 clksel1 = readl(&scu->clk_sel1); + int div; + + div = (clksel1 & SCU0_CLKSEL1_PCLK_DIV_MASK) >> + SCU0_CLKSEL1_PCLK_DIV_SHIFT; + + return (rate / ((div + 1) * 2)); +} + +#define SCU_CLKSEL1_MPHYCLK_SEL_MASK GENMASK(19, 18) +#define SCU_CLKSEL1_MPHYCLK_SEL_SHIFT 18 +#define SCU_CLKSEL1_MPHYCLK_DIV_MASK GENMASK(7, 0) +static u32 ast2700_soc0_get_mphyclk_rate(struct ast2700_scu0 *scu) +{ + int div = readl(&scu->mphyclk_para) & SCU_CLKSEL1_MPHYCLK_DIV_MASK; + u32 chip_id1 = readl(&scu->chip_id1); + u32 clk_sel2; + int clk_sel; + u32 rate = 0; + + if (chip_id1 & SCU_HW_REVISION_ID) { + clk_sel2 = readl(&scu->clk_sel2); + clk_sel = (clk_sel2 & SCU_CLKSEL1_MPHYCLK_SEL_MASK) + >> SCU_CLKSEL1_MPHYCLK_SEL_SHIFT; + switch (clk_sel) { + case 0: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + break; + case 1: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + case 2: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_DPLL); + break; + case 3: + rate = 26000000; + break; + } + } else { + rate = ast2700_soc0_get_hpll_rate(scu); + } + + return (rate / (div + 1)); +} + +static void ast2700_mphy_clk_init(struct ast2700_scu0 *scu) +{ + u32 clksrc1, rate = 0; + int i; + + /* set mphy clk */ + if (readl(&scu->chip_id1) & SCU_HW_REVISION_ID) { + clksrc1 = (readl(&scu->clk_sel2) & SCU_CLKSEL1_MPHYCLK_SEL_MASK) + >> SCU_CLKSEL1_MPHYCLK_SEL_SHIFT; + switch (clksrc1) { + case 0: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL); + break; + case 1: + rate = ast2700_soc0_get_hpll_rate(scu); + break; + case 2: + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_DPLL); + break; + case 3: + rate = 26000000; + break; + } + } else { + rate = ast2700_soc0_get_hpll_rate(scu); + } + + for (i = 1; i < 256; i++) { + if ((rate / i) <= 26000000) + break; + } + + /* register defined the value plus 1 is divider*/ + i--; + writel(i, &scu->mphyclk_para); +} + +#define SCU_CLKSRC1_EMMC_DIV_MASK GENMASK(14, 12) +#define SCU_CLKSRC1_EMMC_DIV_SHIFT 12 +#define SCU_CLKSRC1_EMMC_SEL BIT(11) +static u32 ast2700_soc0_get_emmcclk_rate(struct ast2700_scu0 *scu) +{ + u32 clksel1 = readl(&scu->clk_sel1); + u32 rate; + int div; + + div = (clksel1 & SCU_CLKSRC1_EMMC_DIV_MASK) >> SCU_CLKSRC1_EMMC_DIV_SHIFT; + + if (clksel1 & SCU_CLKSRC1_EMMC_SEL) + rate = ast2700_soc0_get_hpll_rate(scu) / 4; + else + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 4; + + return (rate / ((div + 1) * 2)); +} + +static void ast2700_emmc_init(struct ast2700_scu0 *scu) +{ + u32 clksrc1, rate, div; + int i; + + /* set clk/cmd driving */ + writel(2, &scu->gpio18d0_ioctrl); /* clk driving */ + writel(1, &scu->gpio18d1_ioctrl); /* cmd driving */ + writel(1, &scu->gpio18d2_ioctrl); /* data0 driving */ + writel(1, &scu->gpio18d3_ioctrl); /* data1 driving */ + writel(1, &scu->gpio18d4_ioctrl); /* data2 driving */ + writel(1, &scu->gpio18d5_ioctrl); /* data2 driving */ + + /* emmc clk: set clk src mpll/4:400Mhz */ + clksrc1 = readl(&scu->clk_sel1); + rate = ast2700_soc0_get_pll_rate(scu, SCU0_CLK_MPLL) / 4; + for (i = 0; i < 8; i++) { + div = (i + 1) * 2; + if ((rate / div) <= 200000000) + break; + } + + clksrc1 &= ~(SCU_CLKSRC1_EMMC_DIV_MASK | SCU_CLKSRC1_EMMC_SEL); + clksrc1 |= (i << SCU_CLKSRC1_EMMC_DIV_SHIFT); + writel(clksrc1, &scu->clk_sel1); +} + +static void ast2700_vga_clk_init(struct ast2700_scu0 *scu) +{ + if ((readl(&scu->chip_id1) & SCU_HW_REVISION_ID) == 0) + return; + + // Use d0clk/d1clk which generated from hpll for vga0/1 after A0 + // Use CRT1clk as soc display source + setbits_le32(&scu->clk_sel3, BIT(14) | BIT(13) | BIT(12)); +} + +static u32 ast2700_soc0_get_uartclk_rate(struct ast2700_scu0 *scu) +{ + u32 clksel2 = readl(&scu->clk_sel2); + u32 div = 1; + u32 rate; + + if (clksel2 & BIT(15)) + rate = 192000000; + else + rate = 24000000; + + if (clksel2 & BIT(30)) + div = 13; + return (rate / div); +} + +static ulong ast2700_soc0_clk_get_rate(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + switch (clk->id) { + case SCU0_CLK_PSP: + rate = ast2700_soc0_get_pspclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_HPLL: + rate = ast2700_soc0_get_hpll_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_DPLL: + case SCU0_CLK_MPLL: + rate = ast2700_soc0_get_pll_rate((struct ast2700_scu0 *)priv->reg, clk->id); + break; + case SCU0_CLK_AXI0: + rate = ast2700_soc0_get_axi0clk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_AXI1: + rate = ast2700_soc0_get_axi1clk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_AHB: + rate = ast2700_soc0_get_hclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_APB: + rate = ast2700_soc0_get_pclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_GATE_EMMCCLK: + rate = ast2700_soc0_get_emmcclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_GATE_UART4CLK: + rate = ast2700_soc0_get_uartclk_rate((struct ast2700_scu0 *)priv->reg); + break; + case SCU0_CLK_MPHY: + rate = ast2700_soc0_get_mphyclk_rate((struct ast2700_scu0 *)priv->reg); + break; + default: + debug("%s: unknown clk %ld\n", __func__, clk->id); + return -ENOENT; + } + + return rate; +} + +static int ast2700_soc0_clk_enable(struct clk *clk) +{ + struct ast2700_clk_priv *priv = dev_get_priv(clk->dev); + struct ast2700_scu0 *scu = (struct ast2700_scu0 *)priv->reg; + u32 clkgate_bit = BIT(clk->id); + + writel(clkgate_bit, &scu->clkgate_clr); + + return 0; +} + +static const struct clk_ops ast2700_soc0_clk_ops = { + .get_rate = ast2700_soc0_clk_get_rate, + .enable = ast2700_soc0_clk_enable, +}; + +static void ast2700_init_mac_clk(struct ast2700_scu1 *scu) +{ + u32 src_clk = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 reg_280; + u8 div_idx; + + /* The MAC source clock selects HPLL only, and the default clock + * setting is 200 Mhz. + * Calculate the corresponding divider: + * 1: div 2 + * 2: div 3 + * ... + * 7: div 8 + */ + for (div_idx = 1; div_idx <= 7; div_idx++) + if (DIV_ROUND_UP(src_clk, div_idx + 1) == 200000000) + break; + + if (div_idx == 8) { + pr_err("MAC clock cannot divide to 200 MHz\n"); + return; + } + + /* set HPLL clock divider */ + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~GENMASK(31, 29); + reg_280 |= div_idx << 29; + writel(reg_280, &scu->clk_sel1); +} + +static void ast2700_init_rgmii_clk(struct ast2700_scu1 *scu) +{ + u32 reg_284 = readl(&scu->clk_sel2); + u32 src_clk = ast2700_soc1_get_pll_rate(scu, RGMII_DEFAULT_CLK_SRC); + + if (RGMII_DEFAULT_CLK_SRC == SCU1_CLK_HPLL) { + u32 reg_280; + u8 div_idx; + + /* Calculate the corresponding divider: + * 1: div 4 + * 2: div 6 + * ... + * 7: div 16 + */ + for (div_idx = 1; div_idx <= 7; div_idx++) { + u8 div = 4 + 2 * (div_idx - 1); + + if (DIV_ROUND_UP(src_clk, div) == 125000000) + break; + } + if (div_idx == 8) { + pr_err("RGMII using HPLL cannot divide to 125 MHz\n"); + return; + } + + /* set HPLL clock divider */ + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~GENMASK(27, 25); + reg_280 |= div_idx << 25; + writel(reg_280, &scu->clk_sel1); + + /* select HPLL clock source */ + reg_284 &= ~BIT(18); + } else { + /* APLL clock divider is fixed to 8 */ + if (DIV_ROUND_UP(src_clk, 8) != 125000000) { + pr_err("RGMII using APLL cannot divide to 125 MHz\n"); + return; + } + + /* select APLL clock source */ + reg_284 |= BIT(18); + } + + writel(reg_284, &scu->clk_sel2); +} + +static void ast2700_init_rmii_clk(struct ast2700_scu1 *scu) +{ + u32 src_clk = ast2700_soc1_get_pll_rate(scu, SCU1_CLK_HPLL); + u32 reg_280; + u8 div_idx; + + /* The RMII source clock selects HPLL only. + * Calculate the corresponding divider: + * 1: div 8 + * 2: div 12 + * ... + * 7: div 32 + */ + for (div_idx = 1; div_idx <= 7; div_idx++) { + u8 div = 8 + 4 * (div_idx - 1); + + if (DIV_ROUND_UP(src_clk, div) == 50000000) + break; + } + if (div_idx == 8) { + pr_err("RMII using HPLL cannot divide to 50 MHz\n"); + return; + } + + /* set RMII clock divider */ + reg_280 = readl(&scu->clk_sel1); + reg_280 &= ~GENMASK(23, 21); + reg_280 |= div_idx << 21; + writel(reg_280, &scu->clk_sel1); +} + +static void ast2700_init_spi(struct ast2700_scu1 *scu) +{ + writel(readl(&scu->io_driving8) | 0x0000aaaa, &scu->io_driving8); /* fwspi driving */ + writel(readl(&scu->io_driving3) | 0x00000aaa, &scu->io_driving3); /* spi0 driving */ + writel(readl(&scu->io_driving3) | 0x0aaa0000, &scu->io_driving3); /* spi1 driving */ + writel(readl(&scu->io_driving4) | 0x00002aaa, &scu->io_driving4); /* spi2 driving */ +} + +#define SCU1_CLK_I3C_DIV_MASK GENMASK(25, 23) +#define SCU1_CLK_I3C_DIV(n) ((n) - 1) +static void ast2700_init_i3c_clk(struct ast2700_scu1 *scu) +{ + u32 reg_284; + + /* I3C 250MHz = HPLL/4 */ + reg_284 = readl(&scu->clk_sel2); + reg_284 &= ~SCU1_CLK_I3C_DIV_MASK; + reg_284 |= FIELD_PREP(SCU1_CLK_I3C_DIV_MASK, SCU1_CLK_I3C_DIV(4)); + writel(reg_284, &scu->clk_sel2); +} + +static int ast2700_clk1_init(struct udevice *dev) +{ + struct ast2700_clk_priv *priv = dev_get_priv(dev); + struct ast2700_scu1 *scu = (struct ast2700_scu1 *)priv->reg; + + ast2700_init_spi(scu); + ast2700_init_mac_clk(scu); + ast2700_init_rgmii_clk(scu); + ast2700_init_rmii_clk(scu); + ast2700_init_sdclk(scu); + ast2700_init_i3c_clk(scu); + + return 0; +} + +static int ast2700_clk0_init(struct udevice *dev) +{ + struct ast2700_clk_priv *priv = dev_get_priv(dev); + struct ast2700_scu0 *scu = (struct ast2700_scu0 *)priv->reg; + + ast2700_emmc_init(scu); + ast2700_mphy_clk_init(scu); + ast2700_vga_clk_init(scu); + + return 0; +} + +static int ast2700_clk_probe(struct udevice *dev) +{ + struct ast2700_clk_priv *priv = dev_get_priv(dev); + + priv->init = (ast2700_clk_init_fn)dev_get_driver_data(dev); + priv->reg = (void __iomem *)dev_read_addr_ptr(dev); + + if (priv->init) + return priv->init(dev); + + return 0; +} + +static int ast2700_clk_bind(struct udevice *dev) +{ + struct udevice *sysreset_dev, *rst_dev; + int ret; + + /* The system reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "ast_sysreset", "reset", &sysreset_dev); + if (ret) + debug("Warning: No sysreset driver: ret = %d\n", ret); + + /* Bind the per-SCU reset controller to the same ofnode so that + * <&syscon0/1 RESET_X> phandle references resolve to a UCLASS_RESET + * device. This pairs with the airoha-style binding pattern. + */ + if (CONFIG_IS_ENABLED(RESET_AST2700)) { + ret = device_bind_driver_to_node(dev, "ast2700_reset", "reset", + dev_ofnode(dev), &rst_dev); + if (ret) + debug("Warning: failed to bind reset controller: ret = %d\n", ret); + } + + return 0; +} + +static const struct udevice_id ast2700_soc1_clk_ids[] = { + { .compatible = "aspeed,ast2700-scu1", .data = (ulong)&ast2700_clk1_init }, + { }, +}; + +U_BOOT_DRIVER(aspeed_ast2700_soc1_clk) = { + .name = "aspeed_ast2700_scu1", + .id = UCLASS_CLK, + .of_match = ast2700_soc1_clk_ids, + .priv_auto = sizeof(struct ast2700_clk_priv), + .ops = &ast2700_soc1_clk_ops, + .probe = ast2700_clk_probe, + .bind = ast2700_clk_bind, +}; + +static const struct udevice_id ast2700_soc0_clk_ids[] = { + { .compatible = "aspeed,ast2700-scu0", .data = (ulong)&ast2700_clk0_init }, + { }, +}; + +U_BOOT_DRIVER(aspeed_ast2700_soc0_clk) = { + .name = "aspeed_ast2700_scu0", + .id = UCLASS_CLK, + .of_match = ast2700_soc0_clk_ids, + .priv_auto = sizeof(struct ast2700_clk_priv), + .ops = &ast2700_soc0_clk_ops, + .probe = ast2700_clk_probe, + .bind = ast2700_clk_bind, +}; diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index e692b9c2167..d30786a9e6c 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -228,20 +228,30 @@ static struct clk *_register_divider(struct udevice *dev, const char *name, return clk; } -struct clk *clk_register_divider(struct udevice *dev, const char *name, +struct clk *clk_register_divider_table(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, - u8 clk_divider_flags) + u8 clk_divider_flags, const struct clk_div_table *table) { struct clk *clk; clk = _register_divider(dev, name, parent_name, flags, reg, shift, - width, clk_divider_flags, NULL); + width, clk_divider_flags, table); if (IS_ERR(clk)) return ERR_CAST(clk); return clk; } +struct clk *clk_register_divider(struct udevice *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags) +{ + return clk_register_divider_table(dev, name, parent_name, flags, reg, + shift, width, clk_divider_flags, + NULL); +} + U_BOOT_DRIVER(ccf_clk_divider) = { .name = UBOOT_DM_CLK_CCF_DIVIDER, .id = UCLASS_CLK, diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile index f2fd6ff8ca0..a825ed9988f 100644 --- a/drivers/clk/imx/Makefile +++ b/drivers/clk/imx/Makefile @@ -17,7 +17,7 @@ obj-$(CONFIG_$(PHASE_)CLK_IMX8MN) += clk-imx8mn.o clk-pll14xx.o \ clk-composite-8m.o obj-$(CONFIG_$(PHASE_)CLK_IMX8MP) += clk-imx8mp.o clk-pll14xx.o \ clk-composite-8m.o -obj-$(CONFIG_$(PHASE_)CLK_IMX8MQ) += clk-imx8mq.o clk-pll14xx.o \ +obj-$(CONFIG_$(PHASE_)CLK_IMX8MQ) += clk-imx8mq.o clk-frac-pll.o \ clk-composite-8m.o obj-$(CONFIG_$(PHASE_)CLK_IMX93) += clk-imx93.o clk-fracn-gppll.o \ clk-gate-93.o clk-composite-93.o diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c new file mode 100644 index 00000000000..057389d3069 --- /dev/null +++ b/drivers/clk/imx/clk-frac-pll.c @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2026 NXP + * + */ + +#include <asm/io.h> +#include <malloc.h> +#include <clk-uclass.h> +#include <dm/device.h> +#include <dm/devres.h> +#include <linux/bitops.h> +#include <linux/clk-provider.h> +#include <linux/delay.h> +#include <linux/err.h> +#include <linux/iopoll.h> +#include <clk.h> +#include <div64.h> +#include <linux/printk.h> +#include <linux/bitfield.h> + +#include "clk.h" + +#define PLL_CFG0 0x0 +#define PLL_CFG1 0x4 + +#define PLL_LOCK_STATUS BIT(31) +#define PLL_PD_MASK BIT(19) +#define PLL_BYPASS_MASK BIT(14) +#define PLL_NEWDIV_VAL BIT(12) +#define PLL_NEWDIV_ACK BIT(11) +#define PLL_FRAC_DIV_MASK GENMASK(30, 7) +#define PLL_INT_DIV_MASK GENMASK(6, 0) +#define PLL_OUTPUT_DIV_MASK GENMASK(4, 0) +#define PLL_FRAC_DENOM 0x1000000 + +#define PLL_FRAC_LOCK_TIMEOUT 10000 +#define PLL_FRAC_ACK_TIMEOUT 500000 + +struct clk_frac_pll { + struct clk clk; + void __iomem *base; +}; + +#define to_clk_frac_pll(_clk) container_of(_clk, struct clk_frac_pll, clk) + +static int clk_wait_lock(struct clk_frac_pll *pll) +{ + u32 val; + + return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, + PLL_FRAC_LOCK_TIMEOUT); +} + +static int clk_wait_ack(struct clk_frac_pll *pll) +{ + u32 val; + + /* return directly if the pll is in powerdown or in bypass */ + if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK)) + return 0; + + /* Wait for the pll's divfi and divff to be reloaded */ + return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, + PLL_FRAC_ACK_TIMEOUT); +} + +static int clk_pll_prepare(struct clk *clk) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(clk); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + val &= ~PLL_PD_MASK; + writel_relaxed(val, pll->base + PLL_CFG0); + + return clk_wait_lock(pll); +} + +static int clk_pll_unprepare(struct clk *clk) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(clk); + u32 val; + + val = readl_relaxed(pll->base + PLL_CFG0); + val |= PLL_PD_MASK; + writel_relaxed(val, pll->base + PLL_CFG0); + + return 0; +} + +static unsigned long clk_pll_recalc_rate(struct clk *clk) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(clk); + u32 val, divff, divfi, divq; + ulong parent_rate = clk_get_parent_rate(clk); + u64 temp64 = parent_rate; + u64 rate; + + val = readl_relaxed(pll->base + PLL_CFG0); + divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2; + val = readl_relaxed(pll->base + PLL_CFG1); + divff = FIELD_GET(PLL_FRAC_DIV_MASK, val); + divfi = FIELD_GET(PLL_INT_DIV_MASK, val); + + temp64 *= 8; + temp64 *= divff; + do_div(temp64, PLL_FRAC_DENOM); + do_div(temp64, divq); + + rate = parent_rate * 8 * (divfi + 1); + do_div(rate, divq); + rate += temp64; + + return rate; +} + +static ulong clk_pll_set_rate(struct clk *clk, unsigned long rate) +{ + struct clk_frac_pll *pll = to_clk_frac_pll(clk); + ulong parent_rate = clk_get_parent_rate(clk); + u32 val, divfi, divff; + u64 temp64; + int ret; + + parent_rate *= 8; + rate *= 2; + divfi = rate / parent_rate; + temp64 = parent_rate * divfi; + temp64 = rate - temp64; + temp64 *= PLL_FRAC_DENOM; + do_div(temp64, parent_rate); + divff = temp64; + + val = readl_relaxed(pll->base + PLL_CFG1); + val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK); + val |= (divff << 7) | (divfi - 1); + writel_relaxed(val, pll->base + PLL_CFG1); + + val = readl_relaxed(pll->base + PLL_CFG0); + val &= ~0x1f; + writel_relaxed(val, pll->base + PLL_CFG0); + + /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */ + val = readl_relaxed(pll->base + PLL_CFG0); + val |= PLL_NEWDIV_VAL; + writel_relaxed(val, pll->base + PLL_CFG0); + + ret = clk_wait_ack(pll); + + /* clear the NEV_DIV_VAL */ + val = readl_relaxed(pll->base + PLL_CFG0); + val &= ~PLL_NEWDIV_VAL; + writel_relaxed(val, pll->base + PLL_CFG0); + + if (ret) + return ret; + + return clk_pll_recalc_rate(clk); +} + +static const struct clk_ops clk_frac_pll_ops = { + .enable = clk_pll_prepare, + .disable = clk_pll_unprepare, + .set_rate = clk_pll_set_rate, + .get_rate = clk_pll_recalc_rate, +}; + +struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, + void __iomem *base) +{ + struct clk_frac_pll *pll; + struct clk *clk; + int ret; + + pll = kzalloc(sizeof(*pll), GFP_KERNEL); + if (!pll) + return ERR_PTR(-ENOMEM); + + pll->base = base; + clk = &pll->clk; + + ret = clk_register(clk, "imx_clk_frac_pll", name, parent_name); + if (ret) { + pr_err("%s: failed to register pll %s %d\n", + __func__, name, ret); + kfree(pll); + return ERR_PTR(ret); + } + + return clk; +} + +U_BOOT_DRIVER(clk_frac_pll) = { + .name = "imx_clk_frac_pll", + .id = UCLASS_CLK, + .ops = &clk_frac_pll_ops, + .flags = DM_FLAG_PRE_RELOC, +}; diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index f57ac79f8ca..846b8011f5c 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -9,6 +9,7 @@ #include <log.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> +#include <dm/of_access.h> #include <dt-bindings/clock/imx6qdl-clock.h> #include "clk.h" @@ -46,6 +47,33 @@ static struct clk_ops imx6q_clk_ops = { .disable = ccf_clk_disable, }; +static const char *const pll_bypass_src_sels[] = { + "osc", + "lvds1_in", + "lvds2_in", + "dummy", +}; + +static const char *const pll2_bypass_sels[] = { + "pll2", + "pll2_bypass_src", +}; + +static const char *const pll3_bypass_sels[] = { + "pll3", + "pll3_bypass_src", +}; + +static const char *const pll5_bypass_sels[] = { + "pll5", + "pll5_bypass_src", +}; + +static const char *const pll6_bypass_sels[] = { + "pll6", + "pll6_bypass_src", +}; + static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", @@ -72,6 +100,23 @@ static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; + +static const struct clk_div_table post_div_table[] = { + { .val = 2, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 0, .div = 4, }, + { /* sentinel */ } +}; + +static const struct clk_div_table video_div_table[] = { + { .val = 0, .div = 1, }, + { .val = 1, .div = 2, }, + { .val = 2, .div = 1, }, + { .val = 3, .div = 4, }, + { /* sentinel */ } +}; + +#if CONFIG_IS_ENABLED(VIDEO) static const char *const ipu_sels[] = { "mmdc_ch0_axi", "pll2_pfd2_396m", @@ -113,6 +158,122 @@ static const char *ipu2_di1_sels_2[] = { static unsigned int share_count_mipi_core_cfg; +static void of_assigned_ldb_sels(struct udevice *dev, int *ldb_di0_sel, + int *ldb_di1_sel) +{ + struct ofnode_phandle_args clk_args, parent_args; + ofnode node = dev_ofnode(dev); + int count, err; + + count = dev_count_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0); + if (count <= 0) { + if (count == 0) + debug("%s: no assigned_clocks found\n", dev->name); + else + pr_err("%s: failed to get phandle count (%d)\n", + dev->name, count); + return; + } + + for (int i = 0; i < count; i++) { + err = dev_read_phandle_with_args(dev, "assigned-clocks", + "#clock-cells", 0, i, + &clk_args); + if (err == -ENOENT) + /* Skip empty handles */ + continue; + else if (err < 0) + return; + + if (!ofnode_equal(clk_args.node, node) || + clk_args.args[0] >= IMX6QDL_CLK_END) { + pr_err("%s: clock %d not in ccm\n", dev->name, i); + return; + } + + err = dev_read_phandle_with_args(dev, "assigned-clock-parents", + "#clock-cells", 0, i, + &parent_args); + if (err < 0) + return; + + if (!ofnode_equal(parent_args.node, node) || + parent_args.args[0] >= IMX6QDL_CLK_END) { + pr_err("%s: parent clock %d not in ccm\n", dev->name, + i); + return; + } + + if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI0_SEL) + *ldb_di0_sel = parent_args.args[0]; + else if (clk_args.args[0] == IMX6QDL_CLK_LDB_DI1_SEL) + *ldb_di1_sel = parent_args.args[0]; + } +} + +static void imx6q_init_ldb_clks(struct udevice *dev) +{ + int ldb_di_sel[] = { IMX6QDL_CLK_END, IMX6QDL_CLK_END }; + enum ldb_di_clock ldb_di_clk[] = { MXC_MMDC_CH1_CLK, MXC_MMDC_CH1_CLK }; + + of_assigned_ldb_sels(dev, &ldb_di_sel[0], &ldb_di_sel[1]); + for (int i = 0; i < 2; i++) { + switch (ldb_di_sel[i]) { + case IMX6QDL_CLK_PLL5_VIDEO_DIV: + ldb_di_clk[i] = MXC_PLL5_CLK; + break; + case IMX6QDL_CLK_PLL2_PFD0_352M: + ldb_di_clk[i] = MXC_PLL2_PFD0_CLK; + break; + case IMX6QDL_CLK_PLL2_PFD2_396M: { + struct clk *clk, *parent; + + int err = clk_get_by_id(IMX6QDL_CLK_PERIPH_PRE, &clk); + + if (err) { + pr_err("%s: failed to get periph_pre clock " + "(%d)\n", + dev->name, err); + return; + } + + err = clk_get_by_id(IMX6QDL_CLK_PLL2_PFD2_396M, + &parent); + if (err) { + pr_err("%s: failed to get pll2_pfd2_396m clock" + " (%d)\n", + dev->name, err); + return; + } + + if (parent == clk) { + pr_err("%s: ldb_di%d_sel: couldn't disable " + "pll2_pfd2_396m clock\n", + dev->name, i); + return; + } + + ldb_di_clk[i] = MXC_PLL2_PFD2_CLK; + break; + } + case IMX6QDL_CLK_MMDC_CH1_AXI: + case IMX6QDL_CLK_END: + /* use the default clock */ + break; + case IMX6QDL_CLK_PLL3_USB_OTG: + ldb_di_clk[i] = MXC_PLL3_SW_CLK; + break; + default: + pr_err("%s: invalid LDB clock parent\n", dev->name); + return; + } + } + + select_ldb_di_clock_source(ldb_di_clk[0], ldb_di_clk[1]); +} +#endif /* CONFIG_IS_ENABLED(VIDEO) */ + static int imx6q_clk_probe(struct udevice *dev) { void *base; @@ -120,26 +281,70 @@ static int imx6q_clk_probe(struct udevice *dev) /* Anatop clocks */ base = (void *)ANATOP_BASE_ADDR; - clk_dm(IMX6QDL_CLK_PLL2, - imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2_bus", "osc", - base + 0x30, 0x1)); + clk_dm(IMX6QDL_PLL2_BYPASS_SRC, + imx_clk_mux(dev, "pll2_bypass_src", base + 0x30, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL3_BYPASS_SRC, + imx_clk_mux(dev, "pll3_bypass_src", base + 0x10, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL5_BYPASS_SRC, + imx_clk_mux(dev, "pll5_bypass_src", base + 0xa0, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + clk_dm(IMX6QDL_PLL6_BYPASS_SRC, + imx_clk_mux(dev, "pll6_bypass_src", base + 0xe0, 14, 2, + pll_bypass_src_sels, + ARRAY_SIZE(pll_bypass_src_sels))); + + clk_dm(IMX6QDL_CLK_PLL2, imx_clk_pllv3(dev, IMX_PLLV3_GENERIC, "pll2", + "osc", base + 0x30, 0x1)); + clk_dm(IMX6QDL_CLK_PLL3, imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3", + "osc", base + 0x10, 0x3)); + clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", + base + 0xa0, 0x7f)); + clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", + "osc", base + 0xe0, 0x3)); + + clk_dm(IMX6QDL_PLL2_BYPASS, + imx_clk_mux_flags(dev, "pll2_bypass", base + 0x30, 16, 1, + pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL3_BYPASS, + imx_clk_mux_flags(dev, "pll3_bypass", base + 0x10, 16, 1, + pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL5_BYPASS, + imx_clk_mux_flags(dev, "pll5_bypass", base + 0xa0, 16, 1, + pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), + CLK_SET_RATE_PARENT)); + clk_dm(IMX6QDL_PLL6_BYPASS, + imx_clk_mux_flags(dev, "pll6_bypass", base + 0xe0, 16, 1, + pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), + CLK_SET_RATE_PARENT)); + + SET_CLK_PARENT(IMX6QDL_PLL2_BYPASS, IMX6QDL_CLK_PLL2); + SET_CLK_PARENT(IMX6QDL_PLL3_BYPASS, IMX6QDL_CLK_PLL3); + SET_CLK_PARENT(IMX6QDL_PLL5_BYPASS, IMX6QDL_CLK_PLL5); + SET_CLK_PARENT(IMX6QDL_PLL6_BYPASS, IMX6QDL_CLK_PLL6); + + clk_dm(IMX6QDL_CLK_PLL2_BUS, + imx_clk_gate(dev, "pll2_bus", "pll2_bypass", base + 0x30, 13)); clk_dm(IMX6QDL_CLK_PLL3_USB_OTG, - imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", - base + 0x10, 0x3)); + imx_clk_gate(dev, "pll3_usb_otg", "pll3_bypass", base + 0x10, + 13)); + clk_dm(IMX6QDL_CLK_PLL5_VIDEO, + imx_clk_gate(dev, "pll5_video", "pll5_bypass", base + 0xa0, 13)); + clk_dm(IMX6QDL_CLK_PLL6_ENET, + imx_clk_gate(dev, "pll6_enet", "pll6_bypass", base + 0xe0, 13)); + clk_dm(IMX6QDL_CLK_PLL3_60M, imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); clk_dm(IMX6QDL_CLK_PLL3_80M, imx_clk_fixed_factor(dev, "pll3_80m", "pll3_usb_otg", 1, 6)); clk_dm(IMX6QDL_CLK_PLL3_120M, imx_clk_fixed_factor(dev, "pll3_120m", "pll3_usb_otg", 1, 4)); - clk_dm(IMX6QDL_CLK_PLL5, imx_clk_pllv3(dev, IMX_PLLV3_AV, "pll5", "osc", - base + 0xa0, 0x7f)); - clk_dm(IMX6QDL_CLK_PLL5_VIDEO, - imx_clk_gate(dev, "pll5_video", "pll5", base + 0xa0, 13)); - clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", - "osc", base + 0xe0, 0x3)); - clk_dm(IMX6QDL_CLK_PLL6_ENET, - imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); @@ -151,10 +356,14 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_PLL2_198M, imx_clk_fixed_factor(dev, "pll2_198m", "pll2_pfd2_396m", 1, 2)); clk_dm(IMX6QDL_CLK_PLL5_POST_DIV, - imx_clk_fixed_factor(dev, "pll5_post_div", "pll5_video", 1, 1)); + clk_register_divider_table(dev, "pll5_post_div", "pll5_video", + CLK_SET_RATE_PARENT, base + 0xa0, 19, + 2, 0, post_div_table)); clk_dm(IMX6QDL_CLK_PLL5_VIDEO_DIV, - imx_clk_fixed_factor(dev, "pll5_video_div", "pll5_post_div", 1, - 1)); + clk_register_divider_table(dev, "pll5_video_div", + "pll5_post_div", CLK_SET_RATE_PARENT, + base + 0x170, 30, 2, 0, + video_div_table)); clk_dm(IMX6QDL_CLK_VIDEO_27M, imx_clk_fixed_factor(dev, "video_27m", "pll3_pfd1_540m", 1, 20)); @@ -263,6 +472,7 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22)); +#if CONFIG_IS_ENABLED(VIDEO) clk_dm(IMX6QDL_CLK_IPU1_SEL, imx_clk_mux(dev, "ipu1_sel", base + 0x3c, 9, 2, ipu_sels, ARRAY_SIZE(ipu_sels))); @@ -279,9 +489,12 @@ static int imx6q_clk_probe(struct udevice *dev) ldb_di_sels, ARRAY_SIZE(ldb_di_sels))); } else { /* - * Need to set these as read-only due to a hardware bug. - * Keeping default mux values. Fixed on the i.MX6 QuadPlus - */ + * Need to set these as read-only due to a hardware bug. + * Keeping default mux values. Fixed on the i.MX6 QuadPlus + * Need to set the clocks now and make them read-only due to a + * hardware bug. Fixed on the i.MX6 QuadPlus + */ + imx6q_init_ldb_clks(dev); clk_dm(IMX6QDL_CLK_LDB_DI0_SEL, imx_clk_mux_flags(dev, "ldb_di0_sel", base + 0x2c, 9, 3, ldb_di_sels, ARRAY_SIZE(ldb_di_sels), @@ -413,6 +626,7 @@ static int imx6q_clk_probe(struct udevice *dev) ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT)); } +#endif /* CONFIG_IS_ENABLED(VIDEO) */ clk_dm(IMX6QDL_CLK_ECSPI1, imx_clk_gate2(dev, "ecspi1", "ecspi_root", base + 0x6c, 0)); @@ -453,6 +667,8 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1)); + +#if CONFIG_IS_ENABLED(VIDEO) clk_dm(IMX6QDL_CLK_MIPI_CORE_CFG, imx_clk_gate2_shared(dev, "mipi_core_cfg", "video_27m", base + 0x74, 16, @@ -480,6 +696,7 @@ static int imx6q_clk_probe(struct udevice *dev) SET_CLK_PARENT(IMX6QDL_CLK_IPU1_SEL, IMX6QDL_CLK_PLL3_PFD1_540M); } +#endif /* CONFIG_IS_ENABLED(VIDEO) */ return 0; } diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c index fe6cba19758..78156003ad9 100644 --- a/drivers/clk/imx/clk-imx8mq.c +++ b/drivers/clk/imx/clk-imx8mq.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright 2019 NXP + * Copyright 2019, 2026 NXP * Copyright 2022 Purism * Peng Fan <[email protected]> */ @@ -155,39 +155,52 @@ static int imx8mq_clk_probe(struct udevice *dev) imx_clk_mux(dev, "dram_pll_ref_sel", base + 0x60, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_ARM_PLL_REF_SEL, - imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x28, 0, 2, + imx_clk_mux(dev, "arm_pll_ref_sel", base + 0x28, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_GPU_PLL_REF_SEL, - imx_clk_mux(dev, "gpu_pll_ref_sel", base + 0x18, 0, 2, + imx_clk_mux(dev, "gpu_pll_ref_sel", base + 0x18, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_VPU_PLL_REF_SEL, - imx_clk_mux(dev, "vpu_pll_ref_sel", base + 0x20, 0, 2, + imx_clk_mux(dev, "vpu_pll_ref_sel", base + 0x20, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_SYS3_PLL1_REF_SEL, imx_clk_mux(dev, "sys3_pll_ref_sel", base + 0x48, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_AUDIO_PLL1_REF_SEL, - imx_clk_mux(dev, "audio_pll1_ref_sel", base + 0x0, 0, 2, + imx_clk_mux(dev, "audio_pll1_ref_sel", base + 0x0, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_AUDIO_PLL2_REF_SEL, - imx_clk_mux(dev, "audio_pll2_ref_sel", base + 0x8, 0, 2, + imx_clk_mux(dev, "audio_pll2_ref_sel", base + 0x8, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_VIDEO_PLL1_REF_SEL, - imx_clk_mux(dev, "video_pll1_ref_sel", base + 0x10, 0, 2, + imx_clk_mux(dev, "video_pll1_ref_sel", base + 0x10, 16, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); clk_dm(IMX8MQ_VIDEO2_PLL1_REF_SEL, imx_clk_mux(dev, "video_pll2_ref_sel", base + 0x54, 0, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels))); + clk_dm(IMX8MQ_ARM_PLL_REF_DIV, + imx_clk_divider(dev, "arm_pll_ref_div", "arm_pll_ref_sel", base + 0x28, 5, 6)); + clk_dm(IMX8MQ_GPU_PLL_REF_DIV, + imx_clk_divider(dev, "gpu_pll_ref_div", "gpu_pll_ref_sel", base + 0x18, 5, 6)); + clk_dm(IMX8MQ_VPU_PLL_REF_DIV, + imx_clk_divider(dev, "vpu_pll_ref_div", "vpu_pll_ref_sel", base + 0x20, 5, 6)); + clk_dm(IMX8MQ_AUDIO_PLL1_REF_DIV, + imx_clk_divider(dev, "audio_pll1_ref_div", "audio_pll1_ref_sel", base + 0x0, 5, 6)); + clk_dm(IMX8MQ_AUDIO_PLL2_REF_DIV, + imx_clk_divider(dev, "audio_pll2_ref_div", "audio_pll2_ref_sel", base + 0x8, 5, 6)); + clk_dm(IMX8MQ_VIDEO_PLL1_REF_DIV, + imx_clk_divider(dev, "video_pll1_ref_div", "video_pll1_ref_sel", base + 0x10, 5, 6)); + clk_dm(IMX8MQ_ARM_PLL, - imx_clk_pll14xx("arm_pll", "arm_pll_ref_sel", - base + 0x28, &imx_1416x_pll)); + imx_clk_frac_pll("arm_pll", "arm_pll_ref_div", + base + 0x28)); clk_dm(IMX8MQ_GPU_PLL, - imx_clk_pll14xx("gpu_pll", "gpu_pll_ref_sel", - base + 0x18, &imx_1416x_pll)); + imx_clk_frac_pll("gpu_pll", "gpu_pll_ref_div", + base + 0x18)); clk_dm(IMX8MQ_VPU_PLL, - imx_clk_pll14xx("vpu_pll", "vpu_pll_ref_sel", - base + 0x20, &imx_1416x_pll)); + imx_clk_frac_pll("vpu_pll", "vpu_pll_ref_div", + base + 0x20)); clk_dm(IMX8MQ_SYS1_PLL1, clk_register_fixed_rate(NULL, "sys1_pll", 800000000)); @@ -196,14 +209,14 @@ static int imx8mq_clk_probe(struct udevice *dev) clk_dm(IMX8MQ_SYS2_PLL1, clk_register_fixed_rate(NULL, "sys3_pll", 1000000000)); clk_dm(IMX8MQ_AUDIO_PLL1, - imx_clk_pll14xx("audio_pll1", "audio_pll1_ref_sel", - base + 0x0, &imx_1443x_pll)); + imx_clk_frac_pll("audio_pll1", "audio_pll1_ref_div", + base + 0x0)); clk_dm(IMX8MQ_AUDIO_PLL2, - imx_clk_pll14xx("audio_pll2", "audio_pll2_ref_sel", - base + 0x8, &imx_1443x_pll)); + imx_clk_frac_pll("audio_pll2", "audio_pll2_ref_div", + base + 0x8)); clk_dm(IMX8MQ_VIDEO_PLL1, - imx_clk_pll14xx("video_pll1", "video_pll1_ref_sel", - base + 0x10, &imx_1443x_pll)); + imx_clk_frac_pll("video_pll1", "video_pll1_ref_div", + base + 0x10)); /* PLL bypass out */ clk_dm(IMX8MQ_ARM_PLL_BYPASS, @@ -356,8 +369,8 @@ static int imx8mq_clk_probe(struct udevice *dev) clk_dm(IMX8MQ_CLK_A53_DIV, imx_clk_divider2(dev, "arm_a53_div", "arm_a53_cg", base + 0x8000, 0, 3)); - clk_dm(IMX8MQ_CLK_A53_CORE, - imx_clk_mux2(dev, "arm_a53_src", base + 0x9880, 24, 1, + clk_dm(IMX8MQ_CLK_ARM, + imx_clk_mux2(dev, "arm_a53_core", base + 0x9880, 24, 1, imx8mq_a53_core_sels, ARRAY_SIZE(imx8mq_a53_core_sels))); clk_dm(IMX8MQ_CLK_AHB, diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index b53f35df84f..6aef72c0212 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -78,6 +78,9 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, void __iomem *base, const struct imx_pll14xx_clk *pll_clk); +struct clk *imx_clk_frac_pll(const char *name, const char *parent_name, + void __iomem *base); + struct clk *clk_register_gate2(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 bit_idx, u8 cgr_val, diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig index c6afef90034..5f3b8fe8ab4 100644 --- a/drivers/clk/owl/Kconfig +++ b/drivers/clk/owl/Kconfig @@ -1,8 +1,8 @@ config CLK_OWL - bool "Actions Semi OWL clock drivers" - depends on CLK && ARCH_OWL - help - Enable support for clock managemet unit present in Actions Semi + bool "Actions Semi OWL clock drivers" + depends on CLK && ARCH_OWL + help + Enable support for clock managemet unit present in Actions Semi Owl series S900/S700 SoCs. diff --git a/drivers/clk/qcom/clock-milos.c b/drivers/clk/qcom/clock-milos.c index afe59108559..54103adc114 100644 --- a/drivers/clk/qcom/clock-milos.c +++ b/drivers/clk/qcom/clock-milos.c @@ -15,6 +15,7 @@ #include <linux/bitops.h> #include <dt-bindings/clock/qcom,milos-gcc.h> #include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8650-tcsr.h> #include "clock-qcom.h" @@ -98,6 +99,13 @@ static const struct gate_clk milos_clks[] = { GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x39028, BIT(0)), GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x39024, BIT(0)), GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x3908c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AXI_CLK, 0x77018, BIT(0)), + GATE_CLK(GCC_AGGRE_UFS_PHY_AXI_CLK, 0x770e4, BIT(0)), + GATE_CLK(GCC_UFS_PHY_AHB_CLK, 0x77024, BIT(0)), + GATE_CLK(GCC_UFS_PHY_UNIPRO_CORE_CLK, 0x77068, BIT(0)), + GATE_CLK(GCC_UFS_PHY_TX_SYMBOL_0_CLK, 0x77028, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_0_CLK, 0x7702c, BIT(0)), + GATE_CLK(GCC_UFS_PHY_RX_SYMBOL_1_CLK, 0x770cc, BIT(0)), }; static int milos_enable(struct clk *clk) @@ -194,3 +202,68 @@ U_BOOT_DRIVER(milos_rpmh_clk) = { .ops = &milos_rpmh_clk_ops, .flags = DM_FLAG_DEFAULT_PD_CTRL_OFF, }; + +/* TCSRCC */ + +static const struct gate_clk milos_tcsr_clks[] = { + GATE_CLK(TCSR_PCIE_0_CLKREF_EN, 0x31100, BIT(0)), + GATE_CLK(TCSR_PCIE_1_CLKREF_EN, 0x31114, BIT(0)), + GATE_CLK(TCSR_UFS_CLKREF_EN, 0x31118, BIT(0)), + GATE_CLK(TCSR_UFS_PAD_CLKREF_EN, 0x31104, BIT(0)), +}; + +static struct msm_clk_data milos_tcsrcc_data = { + .clks = milos_tcsr_clks, + .num_clks = ARRAY_SIZE(milos_tcsr_clks), +}; + +static int tcsrcc_milos_clk_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + +static ulong tcsrcc_milos_clk_get_rate(struct clk *clk) +{ + return TCXO_RATE; +} + +static int tcsrcc_milos_clk_probe(struct udevice *dev) +{ + struct msm_clk_data *data = (struct msm_clk_data *)dev_get_driver_data(dev); + struct msm_clk_priv *priv = dev_get_priv(dev); + + priv->base = dev_read_addr(dev); + if (priv->base == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->data = data; + + return 0; +} + +static struct clk_ops tcsrcc_milos_clk_ops = { + .enable = tcsrcc_milos_clk_enable, + .get_rate = tcsrcc_milos_clk_get_rate, +}; + +static const struct udevice_id tcsrcc_milos_of_match[] = { + { + .compatible = "qcom,milos-tcsr", + .data = (ulong)&milos_tcsrcc_data, + }, + { } +}; + +U_BOOT_DRIVER(tcsrcc_milos) = { + .name = "tcsrcc_milos", + .id = UCLASS_CLK, + .of_match = tcsrcc_milos_of_match, + .ops = &tcsrcc_milos_clk_ops, + .priv_auto = sizeof(struct msm_clk_priv), + .probe = tcsrcc_milos_clk_probe, + .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF, +}; diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 72f99e9fa1b..1893b6c4181 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -61,11 +61,11 @@ config CLK_RCAR_GEN3 Enable this to support the clocks on Renesas R-Car Gen3 and Gen4 SoCs. config CLK_R8A774A1 - bool "Renesas R8A774A1 clock driver" + bool "Renesas R8A774A1 clock driver" def_bool y if R8A774A1 - depends on CLK_RCAR_GEN3 - help - Enable this to support the clocks on Renesas R8A774A1 SoC. + depends on CLK_RCAR_GEN3 + help + Enable this to support the clocks on Renesas R8A774A1 SoC. config CLK_R8A774B1 bool "Renesas R8A774B1 clock driver" diff --git a/drivers/clk/renesas/rcar-cpg-lib.c b/drivers/clk/renesas/rcar-cpg-lib.c index 60ab2cb379e..8e992d2c2da 100644 --- a/drivers/clk/renesas/rcar-cpg-lib.c +++ b/drivers/clk/renesas/rcar-cpg-lib.c @@ -30,10 +30,6 @@ #define SDnSRCFC_SHIFT 2 #define STPnHCK_TABLE (CPG_SDCKCR_STPnHCK >> SDnSRCFC_SHIFT) -/* Non-constant mask variant of FIELD_GET/FIELD_PREP */ -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - static const struct clk_div_table cpg_sdh_div_table[] = { { 0, 1 }, { 1, 2 }, { STPnHCK_TABLE | 2, 4 }, { STPnHCK_TABLE | 3, 8 }, { STPnHCK_TABLE | 4, 16 }, { 0, 0 }, diff --git a/drivers/core/acpi.c b/drivers/core/acpi.c index 6a431171c8d..284fb70b036 100644 --- a/drivers/core/acpi.c +++ b/drivers/core/acpi.c @@ -87,7 +87,7 @@ int acpi_copy_name(char *out_name, const char *name) int acpi_get_name(const struct udevice *dev, char *out_name) { - struct acpi_ops *aops; + const struct acpi_ops *aops; const char *name; int ret; @@ -275,7 +275,7 @@ static int sort_acpi_item_type(struct acpi_ctx *ctx, void *start, acpi_method acpi_get_method(struct udevice *dev, enum method_t method) { - struct acpi_ops *aops; + const struct acpi_ops *aops; aops = device_get_acpi_ops(dev); if (aops) { diff --git a/drivers/core/root.c b/drivers/core/root.c index 1f32f33b295..2aa16d59b69 100644 --- a/drivers/core/root.c +++ b/drivers/core/root.c @@ -459,7 +459,7 @@ static int root_acpi_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "\\_SB"); } -struct acpi_ops root_acpi_ops = { +static const struct acpi_ops root_acpi_ops = { .get_name = root_acpi_get_name, }; #endif diff --git a/drivers/cpu/armv8_cpu.c b/drivers/cpu/armv8_cpu.c index ed87841b723..337661c23a8 100644 --- a/drivers/cpu/armv8_cpu.c +++ b/drivers/cpu/armv8_cpu.c @@ -124,7 +124,7 @@ int armv8_cpu_fill_madt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -static struct acpi_ops armv8_cpu_acpi_ops = { +static const struct acpi_ops armv8_cpu_acpi_ops = { .fill_ssdt = armv8_cpu_fill_ssdt, .fill_madt = armv8_cpu_fill_madt, }; diff --git a/drivers/cpu/bcm283x_cpu.c b/drivers/cpu/bcm283x_cpu.c index ad638cd8fff..43e74d1811b 100644 --- a/drivers/cpu/bcm283x_cpu.c +++ b/drivers/cpu/bcm283x_cpu.c @@ -193,7 +193,7 @@ static int bcm_cpu_probe(struct udevice *dev) return ret; } -struct acpi_ops bcm283x_cpu_acpi_ops = { +static const struct acpi_ops __maybe_unused bcm283x_cpu_acpi_ops = { .fill_ssdt = armv8_cpu_fill_ssdt, .fill_madt = armv8_cpu_fill_madt, }; diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfig index 401225b8528..a4710257f62 100644 --- a/drivers/crypto/aspeed/Kconfig +++ b/drivers/crypto/aspeed/Kconfig @@ -15,11 +15,11 @@ config ASPEED_ACRY bool "ASPEED RSA and ECC Engine" depends on ASPEED_AST2600 help - Select this option to enable a driver for using the RSA/ECC engine in - the ASPEED BMC SoCs. + Select this option to enable a driver for using the RSA/ECC engine in + the ASPEED BMC SoCs. - Enabling this allows the use of RSA/ECC operations in hardware without requiring the - software implementations. It also improves performance and saves code size. + Enabling this allows the use of RSA/ECC operations in hardware without requiring the + software implementations. It also improves performance and saves code size. config ASPEED_CPTRA_SHA bool "Caliptra SHA ACC for Aspeed AST27xx SoCs" diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig index eb01c6cf700..244a9bd905d 100644 --- a/drivers/crypto/fsl/Kconfig +++ b/drivers/crypto/fsl/Kconfig @@ -20,6 +20,7 @@ config SYS_FSL_MAX_NUM_OF_SEC config CAAM_64BIT bool + depends on FSL_CAAM default y if PHYS_64BIT && !ARCH_IMX8M && !ARCH_IMX8 help Select Crypto driver for 64 bits CAAM version @@ -27,27 +28,27 @@ config CAAM_64BIT config SYS_FSL_HAS_SEC bool help - Enable Freescale Secure Boot and Trusted Architecture + Enable Freescale Secure Boot and Trusted Architecture config SYS_FSL_SEC_COMPAT_2 bool help - Secure boot and trust architecture compatible version 2 + Secure boot and trust architecture compatible version 2 config SYS_FSL_SEC_COMPAT_4 bool help - Secure boot and trust architecture compatible version 4 + Secure boot and trust architecture compatible version 4 config SYS_FSL_SEC_COMPAT_5 bool help - Secure boot and trust architecture compatible version 5 + Secure boot and trust architecture compatible version 5 config SYS_FSL_SEC_COMPAT_6 bool help - Secure boot and trust architecture compatible version 6 + Secure boot and trust architecture compatible version 6 config SYS_FSL_SEC_BE bool "Big-endian access to Freescale Secure Boot" diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig index 7f8f3570dd8..b11fa79ca59 100644 --- a/drivers/ddr/fsl/Kconfig +++ b/drivers/ddr/fsl/Kconfig @@ -21,12 +21,12 @@ if SYS_FSL_DDR || SYS_FSL_MMDC config SYS_FSL_DDR_BE bool help - Access DDR registers in big-endian + Access DDR registers in big-endian config SYS_FSL_DDR_LE bool help - Access DDR registers in little-endian + Access DDR registers in little-endian config FSL_DDR_BIST bool diff --git a/drivers/dma/ti/Kconfig b/drivers/dma/ti/Kconfig index d904982c800..8c9b377e8a3 100644 --- a/drivers/dma/ti/Kconfig +++ b/drivers/dma/ti/Kconfig @@ -3,14 +3,14 @@ if ARCH_K3 config TI_K3_NAVSS_UDMA - bool "Texas Instruments UDMA" - depends on ARCH_K3 - select DEVRES - select DMA - select TI_K3_NAVSS_RINGACC - select TI_K3_PSIL - help - Support for UDMA used in K3 devices. + bool "Texas Instruments UDMA" + depends on ARCH_K3 + select DEVRES + select DMA + select TI_K3_NAVSS_RINGACC + select TI_K3_PSIL + help + Support for UDMA used in K3 devices. endif config TI_K3_PSIL diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig index 220de731950..f524f741e54 100644 --- a/drivers/firmware/Kconfig +++ b/drivers/firmware/Kconfig @@ -14,7 +14,7 @@ config ARM_PSCI_FW select FIRMWARE config TI_SCI_PROTOCOL - tristate "TI System Control Interface (TISCI) Message Protocol" + bool "TI System Control Interface (TISCI) Message Protocol" depends on K3_SEC_PROXY select DEVRES select FIRMWARE diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index ea14ed4ef95..6052a31b5b4 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -7,6 +7,7 @@ */ #include <asm/arch/hardware.h> +#include <asm/arch/sys_proto.h> #include <asm/io.h> #include <cpu_func.h> #include <dm.h> @@ -16,6 +17,7 @@ #include <zynqmp_firmware.h> #include <asm/cache.h> #include <asm/ptrace.h> +#include <asm/system.h> #include <linux/bitfield.h> #if defined(CONFIG_ZYNQMP_IPI) @@ -326,6 +328,93 @@ u32 zynqmp_pm_get_pmc_multi_boot_reg(void) } #endif +#if defined(CONFIG_ARCH_VERSAL) +u32 versal_pmc_multi_boot(void) +{ + /* At EL3 the SMC path to firmware is unavailable, read directly */ + if (current_el() == 3) + return versal_multi_boot_reg(); + + return zynqmp_pm_get_pmc_multi_boot_reg() & PMC_MULTI_BOOT_MASK; +} + +u8 versal_get_bootmode(void) +{ + u32 reg; + + /* At EL3 the SMC path to firmware is unavailable, read directly */ + if (current_el() == 3) + reg = versal_bootmode_reg(); + else + reg = zynqmp_pm_get_bootmode_reg(); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + return reg & BOOT_MODES_MASK; +} +#endif + +#if defined(CONFIG_ARCH_VERSAL_NET) +u8 versal_net_get_bootmode(void) +{ + u32 reg; + + /* At EL3 the SMC path to firmware is unavailable, read directly */ + if (current_el() == 3) + reg = versal_net_bootmode_reg(); + else + reg = zynqmp_pm_get_bootmode_reg(); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + return reg & BOOT_MODES_MASK; +} +#endif + +#if defined(CONFIG_ARCH_ZYNQMP) +int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value) +{ + /* At EL3 or in SPL the firmware (SMC) path is unavailable */ + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) + return zynqmp_mmio_rawwrite(address, mask, value); + + return xilinx_pm_request(PM_MMIO_WRITE, address, mask, value, + 0, 0, 0, NULL); +} + +int zynqmp_mmio_read(const u32 address, u32 *value) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!value) + return -EINVAL; + + /* At EL3 or in SPL the firmware (SMC) path is unavailable */ + if (IS_ENABLED(CONFIG_XPL_BUILD) || current_el() == 3) + return zynqmp_mmio_rawread(address, value); + + ret = xilinx_pm_request(PM_MMIO_READ, address, 0, 0, 0, 0, 0, + ret_payload); + *value = ret_payload[1]; + + return ret; +} +#endif + +#if defined(CONFIG_ARCH_VERSAL2) +u32 versal2_pmc_multi_boot(void) +{ + /* At EL3 the SMC path to firmware is unavailable, read directly */ + if (current_el() == 3) + return versal2_multi_boot_reg(); + + return zynqmp_pm_get_pmc_multi_boot_reg() & PMC_MULTI_BOOT_MASK; +} +#endif + int zynqmp_pm_feature(const u32 api_id) { int ret; diff --git a/drivers/firmware/psci.c b/drivers/firmware/psci.c index b6838a244d2..2e3223e1c32 100644 --- a/drivers/firmware/psci.c +++ b/drivers/firmware/psci.c @@ -186,10 +186,6 @@ static int psci_bind(struct udevice *dev) NULL); if (ret) pr_debug("PSCI System Reset was not bound.\n"); - if (IS_ENABLED(CONFIG_SYSRESET_QCOM_PSCI) && - device_bind_driver(dev, "qcom_psci-sysreset", - "qcom_psci-sysreset", NULL)) - pr_debug("QCOM PSCI System Reset was not bound.\n"); } /* From PSCI v1.0 onward we can discover services through ARM_SMCCC_FEATURE */ diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 822183c5785..69d7111a5f1 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -12,8 +12,7 @@ /* * Altera FPGA support */ -#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_FPGA_INTEL_SDM_MAILBOX) #include <asm/arch/misc.h> #endif #include <errno.h> @@ -48,8 +47,7 @@ static const struct altera_fpga { #endif }; -#if IS_ENABLED(CONFIG_ARCH_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_ARCH_SOCFPGA_STRATIX10) +#if IS_ENABLED(CONFIG_FPGA_INTEL_SDM_MAILBOX) int fpga_is_partial_data(int devnum, size_t img_len) { /* diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 5084af23269..75b35fbc5be 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -294,9 +294,9 @@ config MAX7320_GPIO bool "MAX7320 I2C GPIO Expander driver" depends on DM_GPIO && DM_I2C help - Support for MAX7320 I2C 8/16-bit GPIO expander. - original maxim device has 8 push/pull outputs, - some clones offers 16bit. + Support for MAX7320 I2C 8/16-bit GPIO expander. + original maxim device has 8 push/pull outputs, + some clones offers 16bit. config MAX77663_GPIO bool "MAX77663 GPIO cell of PMIC driver" @@ -313,23 +313,23 @@ config MCP230XX_GPIO help Support for Microchip's MCP230XX I2C and SPI connected GPIO devices. The following chips are supported: - - MCP23008 - - MCP23017 - - MCP23018 - - MCP23S08 - - MCP23S17 - - MCP23S18 + - MCP23008 + - MCP23017 + - MCP23018 + - MCP23S08 + - MCP23S17 + - MCP23S18 config MSCC_SGPIO bool "Microsemi Serial GPIO driver" depends on DM_GPIO && SOC_VCOREIII help Support for the VCoreIII SoC serial GPIO device. By using a - serial interface, the SIO controller significantly extends - the number of available GPIOs with a minimum number of - additional pins on the device. The primary purpose of the - SIO controller is to connect control signals from SFP - modules and to act as an LED controller. + serial interface, the SIO controller significantly extends + the number of available GPIOs with a minimum number of + additional pins on the device. The primary purpose of the + SIO controller is to connect control signals from SFP + modules and to act as an LED controller. config MSM_GPIO bool "Qualcomm GPIO driver" @@ -404,8 +404,8 @@ config PCF8575_GPIO bool "PCF8575 I2C GPIO Expander driver" depends on DM_GPIO && DM_I2C help - Support for PCF8575 I2C 16-bit GPIO expander. Most of these - chips are from NXP and TI. + Support for PCF8575 I2C 16-bit GPIO expander. Most of these + chips are from NXP and TI. config RCAR_GPIO bool "Renesas R-Car GPIO driver" @@ -459,9 +459,9 @@ config SUNXI_GPIO config SUNXI_NEW_PINCTRL bool depends on SUNXI_GPIO - ---help--- - The Allwinner D1 and other new SoCs use a different register map - for the GPIO block, which we need to know about in the SPL. + help + The Allwinner D1 and other new SoCs use a different register map + for the GPIO block, which we need to know about in the SPL. config XILINX_GPIO bool "Xilinx GPIO driver" @@ -728,15 +728,15 @@ config SLG7XL45106_I2C_GPO bool "slg7xl45106 i2c gpo expander" depends on DM_GPIO && ARCH_ZYNQMP help - Support for slg7xl45106 i2c gpo expander. It is an i2c based - 8-bit gpo expander, all gpo lines are controlled by writing - value into data register. + Support for slg7xl45106 i2c gpo expander. It is an i2c based + 8-bit gpo expander, all gpo lines are controlled by writing + value into data register. config GPIO_SCMI bool "SCMI GPIO pinctrl driver" depends on DM_GPIO && PINCTRL_SCMI help - Support pinctrl GPIO over the SCMI interface. + Support pinctrl GPIO over the SCMI interface. config ADP5585_GPIO bool "ADP5585 GPIO driver" @@ -756,10 +756,11 @@ config SPL_ADP5585_GPIO depends on SPL_DM_GPIO && SPL_I2C help Support ADP5585 GPIO expander in SPL. + config MPFS_GPIO bool "Enable Polarfire SoC GPIO driver" depends on DM_GPIO help - Enable to support the GPIO driver on Polarfire SoC + Enable to support the GPIO driver on Polarfire SoC endif diff --git a/drivers/gpio/imx_rgpio2p.c b/drivers/gpio/imx_rgpio2p.c index 7cf178f8a48..ba3c5fcf25b 100644 --- a/drivers/gpio/imx_rgpio2p.c +++ b/drivers/gpio/imx_rgpio2p.c @@ -194,11 +194,11 @@ static int imx_rgpio2p_bind(struct udevice *dev) dual_base = true; if (dual_base) { - addr = devfdt_get_addr_index(dev, 1); + addr = dev_read_addr_index(dev, 1); if (addr == FDT_ADDR_T_NONE) return -EINVAL; } else { - addr = devfdt_get_addr_index(dev, 0); + addr = dev_read_addr_index(dev, 0); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c index 709d04017d1..40646407369 100644 --- a/drivers/gpio/mpc8xxx_gpio.c +++ b/drivers/gpio/mpc8xxx_gpio.c @@ -171,6 +171,58 @@ static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio) return dir ? GPIOF_OUTPUT : GPIOF_INPUT; } +static int mpc8xxx_gpio_set_flags(struct udevice *dev, uint gpio, + ulong flags) +{ + u32 mask = gpio_mask(gpio); + int ret; + + /* The QorIQ GPIO pad supports open-drain only; open-source has + * no silicon counterpart, so reject it rather than silently + * pretending. + */ + if (flags & GPIOD_OPEN_SOURCE) + return -EOPNOTSUPP; + + /* GPODR is per-pin and meaningful in both directions (it stays + * latched when the pin is re-purposed), so apply it before the + * direction change. + */ + if (flags & GPIOD_OPEN_DRAIN) + mpc8xxx_gpio_open_drain_on(dev, mask); + else + mpc8xxx_gpio_open_drain_off(dev, mask); + + if (flags & GPIOD_IS_OUT) { + ret = mpc8xxx_gpio_direction_output(dev, gpio, + !!(flags & GPIOD_IS_OUT_ACTIVE)); + } else if (flags & GPIOD_IS_IN) { + ret = mpc8xxx_gpio_direction_input(dev, gpio); + } else { + ret = 0; + } + + return ret; +} + +static int mpc8xxx_gpio_get_flags(struct udevice *dev, uint gpio, + ulong *flagsp) +{ + u32 mask = gpio_mask(gpio); + ulong flags = 0; + + if (mpc8xxx_gpio_get_dir(dev, mask)) + flags |= GPIOD_IS_OUT; + else + flags |= GPIOD_IS_IN; + + if (mpc8xxx_gpio_open_drain_val(dev, mask)) + flags |= GPIOD_OPEN_DRAIN; + + *flagsp = flags; + return 0; +} + #if CONFIG_IS_ENABLED(OF_CONTROL) static int mpc8xxx_gpio_of_to_plat(struct udevice *dev) { @@ -255,6 +307,8 @@ static const struct dm_gpio_ops gpio_mpc8xxx_ops = { .get_value = mpc8xxx_gpio_get_value, .set_value = mpc8xxx_gpio_set_value, .get_function = mpc8xxx_gpio_get_function, + .set_flags = mpc8xxx_gpio_set_flags, + .get_flags = mpc8xxx_gpio_get_flags, }; static const struct udevice_id mpc8xxx_gpio_ids[] = { diff --git a/drivers/gpio/sandbox.c b/drivers/gpio/sandbox.c index e8f50d815d7..76aff0ed5aa 100644 --- a/drivers/gpio/sandbox.c +++ b/drivers/gpio/sandbox.c @@ -306,7 +306,7 @@ static int sb_gpio_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "GPIO"); } -struct acpi_ops gpio_sandbox_acpi_ops = { +static const struct acpi_ops gpio_sandbox_acpi_ops = { .get_name = sb_gpio_get_name, }; #endif /* ACPIGEN */ @@ -568,7 +568,7 @@ static struct pinctrl_ops sandbox_pinctrl_gpio_ops = { }; #if CONFIG_IS_ENABLED(ACPIGEN) -struct acpi_ops pinctrl_sandbox_acpi_ops = { +static const struct acpi_ops pinctrl_sandbox_acpi_ops = { .get_name = sb_pinctrl_get_name, }; #endif diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 8c2f71b9fe2..5f6586c78ba 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -98,7 +98,7 @@ config SYS_I2C_EARLY_INIT board_early_init_f. config I2C_CROS_EC_TUNNEL - tristate "Chrome OS EC tunnel I2C bus" + bool "Chrome OS EC tunnel I2C bus" depends on CROS_EC help This provides an I2C bus that will tunnel i2c commands through to @@ -110,16 +110,16 @@ config I2C_CROS_EC_TUNNEL config I2C_CROS_EC_LDO bool "Provide access to LDOs on the Chrome OS EC" depends on CROS_EC - ---help--- - On many Chromebooks the main PMIC is inaccessible to the AP. This is - often dealt with by using an I2C pass-through interface provided by - the EC. On some unfortunate models (e.g. Spring) the pass-through - is not available, and an LDO message is available instead. This - option enables a driver which provides very basic access to those - regulators, via the EC. We implement this as an I2C bus which - emulates just the TPS65090 messages we know about. This is done to - avoid duplicating the logic in the TPS65090 regulator driver for - enabling/disabling an LDO. + help + On many Chromebooks the main PMIC is inaccessible to the AP. This is + often dealt with by using an I2C pass-through interface provided by + the EC. On some unfortunate models (e.g. Spring) the pass-through + is not available, and an LDO message is available instead. This + option enables a driver which provides very basic access to those + regulators, via the EC. We implement this as an I2C bus which + emulates just the TPS65090 messages we know about. This is done to + avoid duplicating the logic in the TPS65090 regulator driver for + enabling/disabling an LDO. config I2C_SET_DEFAULT_BUS_NUM bool "Set default I2C bus number" @@ -180,9 +180,9 @@ config SYS_I2C_IPROC Say yes here to to enable the Broadco I2C driver. config SYS_I2C_FSL - bool "Freescale I2C bus driver" - depends on M68K || PPC - help + bool "Freescale I2C bus driver" + depends on M68K || PPC + help Add support for Freescale I2C busses as used on MPC8240, MPC8245, and MPC85xx processors. @@ -213,14 +213,14 @@ config SYS_FSL_I2C4_OFFSET endif config SYS_I2C_CADENCE - tristate "Cadence I2C Controller" + bool "Cadence I2C Controller" depends on DM_I2C help Say yes here to select Cadence I2C Host Controller. This controller is e.g. used by Xilinx Zynq. config SYS_I2C_CA - tristate "Cortina-Access I2C Controller" + bool "Cortina-Access I2C Controller" depends on DM_I2C && CORTINA_PLATFORM help Add support for the Cortina Access I2C host controller. @@ -249,14 +249,14 @@ config SYS_I2C_DW_PCI controller. config SYS_I2C_AST2600 - bool "AST2600 I2C Controller" - depends on DM_I2C && ARCH_ASPEED - help - Say yes here to select AST2600 I2C Host Controller. The driver - support AST2600 I2C new mode register. This I2C controller supports: - _Standard-mode (up to 100 kHz) - _Fast-mode (up to 400 kHz) - _Fast-mode Plus (up to 1 MHz) + bool "AST2600 I2C Controller" + depends on DM_I2C && ARCH_ASPEED + help + Say yes here to select AST2600 I2C Host Controller. The driver + support AST2600 I2C new mode register. This I2C controller supports: + _Standard-mode (up to 100 kHz) + _Fast-mode (up to 400 kHz) + _Fast-mode Plus (up to 1 MHz) config SYS_I2C_ASPEED bool "Aspeed I2C Controller" @@ -333,50 +333,50 @@ if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY) config SYS_I2C_MXC_I2C1 bool "NXP MXC I2C1" help - Add support for NXP MXC I2C Controller 1. - Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 1. + Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C2 bool "NXP MXC I2C2" help - Add support for NXP MXC I2C Controller 2. - Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 2. + Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C3 bool "NXP MXC I2C3" help - Add support for NXP MXC I2C Controller 3. - Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 3. + Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C4 bool "NXP MXC I2C4" help - Add support for NXP MXC I2C Controller 4. - Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A + Add support for NXP MXC I2C Controller 4. + Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A config SYS_I2C_MXC_I2C5 bool "NXP MXC I2C5" help - Add support for NXP MXC I2C Controller 5. - Required for SoCs which have I2C MXC controller 5 eg LX2160A + Add support for NXP MXC I2C Controller 5. + Required for SoCs which have I2C MXC controller 5 eg LX2160A config SYS_I2C_MXC_I2C6 bool "NXP MXC I2C6" help - Add support for NXP MXC I2C Controller 6. - Required for SoCs which have I2C MXC controller 6 eg LX2160A + Add support for NXP MXC I2C Controller 6. + Required for SoCs which have I2C MXC controller 6 eg LX2160A config SYS_I2C_MXC_I2C7 bool "NXP MXC I2C7" help - Add support for NXP MXC I2C Controller 7. - Required for SoCs which have I2C MXC controller 7 eg LX2160A + Add support for NXP MXC I2C Controller 7. + Required for SoCs which have I2C MXC controller 7 eg LX2160A config SYS_I2C_MXC_I2C8 bool "NXP MXC I2C8" help - Add support for NXP MXC I2C Controller 8. - Required for SoCs which have I2C MXC controller 8 eg LX2160A + Add support for NXP MXC I2C Controller 8. + Required for SoCs which have I2C MXC controller 8 eg LX2160A endif if SYS_I2C_MXC_I2C1 @@ -385,13 +385,13 @@ config SYS_MXC_I2C1_SPEED default 40000000 if TARGET_LS2080A_EMU default 100000 help - MXC I2C Channel 1 speed + MXC I2C Channel 1 speed config SYS_MXC_I2C1_SLAVE hex "I2C1 Slave" default 0x0 help - MXC I2C1 Slave + MXC I2C1 Slave endif if SYS_I2C_MXC_I2C2 @@ -400,13 +400,13 @@ config SYS_MXC_I2C2_SPEED default 40000000 if TARGET_LS2080A_EMU default 100000 help - MXC I2C Channel 2 speed + MXC I2C Channel 2 speed config SYS_MXC_I2C2_SLAVE hex "I2C2 Slave" default 0x0 help - MXC I2C2 Slave + MXC I2C2 Slave endif if SYS_I2C_MXC_I2C3 @@ -414,13 +414,13 @@ config SYS_MXC_I2C3_SPEED int "I2C Channel 3 speed" default 100000 help - MXC I2C Channel 3 speed + MXC I2C Channel 3 speed config SYS_MXC_I2C3_SLAVE hex "I2C3 Slave" default 0x0 help - MXC I2C3 Slave + MXC I2C3 Slave endif if SYS_I2C_MXC_I2C4 @@ -428,13 +428,13 @@ config SYS_MXC_I2C4_SPEED int "I2C Channel 4 speed" default 100000 help - MXC I2C Channel 4 speed + MXC I2C Channel 4 speed config SYS_MXC_I2C4_SLAVE hex "I2C4 Slave" default 0x0 help - MXC I2C4 Slave + MXC I2C4 Slave endif if SYS_I2C_MXC_I2C5 @@ -442,13 +442,13 @@ config SYS_MXC_I2C5_SPEED int "I2C Channel 5 speed" default 100000 help - MXC I2C Channel 5 speed + MXC I2C Channel 5 speed config SYS_MXC_I2C5_SLAVE hex "I2C5 Slave" default 0x0 help - MXC I2C5 Slave + MXC I2C5 Slave endif if SYS_I2C_MXC_I2C6 @@ -456,13 +456,13 @@ config SYS_MXC_I2C6_SPEED int "I2C Channel 6 speed" default 100000 help - MXC I2C Channel 6 speed + MXC I2C Channel 6 speed config SYS_MXC_I2C6_SLAVE hex "I2C6 Slave" default 0x0 help - MXC I2C6 Slave + MXC I2C6 Slave endif if SYS_I2C_MXC_I2C7 @@ -470,13 +470,13 @@ config SYS_MXC_I2C7_SPEED int "I2C Channel 7 speed" default 100000 help - MXC I2C Channel 7 speed + MXC I2C Channel 7 speed config SYS_MXC_I2C7_SLAVE hex "I2C7 Slave" default 0x0 help - MXC I2C7 Slave + MXC I2C7 Slave endif if SYS_I2C_MXC_I2C8 @@ -484,13 +484,13 @@ config SYS_MXC_I2C8_SPEED int "I2C Channel 8 speed" default 100000 help - MXC I2C Channel 8 speed + MXC I2C Channel 8 speed config SYS_MXC_I2C8_SLAVE hex "I2C8 Slave" default 0x0 help - MXC I2C8 Slave + MXC I2C8 Slave endif config SYS_I2C_NEXELL @@ -668,19 +668,19 @@ config SYS_I2C_STM32F7 help Enable this option to add support for STM32 I2C controller introduced with STM32F7/H7 SoCs. This I2C controller supports : - _ Slave and master modes - _ Multimaster capability - _ Standard-mode (up to 100 kHz) - _ Fast-mode (up to 400 kHz) - _ Fast-mode Plus (up to 1 MHz) - _ 7-bit and 10-bit addressing mode - _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) - _ All 7-bit addresses acknowledge mode - _ General call - _ Programmable setup and hold times - _ Easy to use event management - _ Optional clock stretching - _ Software reset + _ Slave and master modes + _ Multimaster capability + _ Standard-mode (up to 100 kHz) + _ Fast-mode (up to 400 kHz) + _ Fast-mode Plus (up to 1 MHz) + _ 7-bit and 10-bit addressing mode + _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask) + _ All 7-bit addresses acknowledge mode + _ General call + _ Programmable setup and hold times + _ Easy to use event management + _ Optional clock stretching + _ Software reset config SYS_I2C_SUN6I_P2WI bool "Allwinner sun6i P2WI controller" @@ -792,10 +792,10 @@ config SYS_I2C_XILINX_XIIC Support for Xilinx AXI I2C controller. config SYS_I2C_IHS - bool "gdsys IHS I2C driver" - depends on DM_I2C - help - Support for gdsys IHS I2C driver on FPGA bus. + bool "gdsys IHS I2C driver" + depends on DM_I2C + help + Support for gdsys IHS I2C driver on FPGA bus. source "drivers/i2c/muxes/Kconfig" diff --git a/drivers/i2c/designware_i2c.c b/drivers/i2c/designware_i2c.c index 8ad716f410e..8d290acefda 100644 --- a/drivers/i2c/designware_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -740,13 +740,47 @@ static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr, { struct dw_i2c *i2c = dev_get_priv(bus); struct i2c_regs *i2c_base = i2c->regs; - u32 tmp; - int ret; + u32 start_time, ic_status; + int ret = 0; - /* Try to read the first location of the chip */ - ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1); + ret = i2c_wait_for_bb(i2c_base); if (ret) - __dw_i2c_init(i2c_base, 0, 0); + return ret; + + dw_i2c_enable(i2c_base, false); + writel(chip_addr, &i2c_base->ic_tar); + dw_i2c_enable(i2c_base, true); + + writel(IC_STOP, &i2c_base->ic_cmd_data); + + start_time = get_timer(0); + while (1) { + ic_status = readl(&i2c_base->ic_status); + + if ((ic_status & IC_STATUS_TFE) && !(ic_status & IC_STATUS_MA)) + break; + + if (readl(&i2c_base->ic_raw_intr_stat) & IC_TX_ABRT) { + readl(&i2c_base->ic_clr_tx_abrt); + ret = -EREMOTEIO; + break; + } + + if (get_timer(start_time) > I2C_BYTE_TO) { + ret = -ETIMEDOUT; + break; + } + } + + start_time = get_timer(0); + while (1) { + if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) { + readl(&i2c_base->ic_clr_stop_det); + break; + } else if (get_timer(start_time) > I2C_STOPDET_TO) { + break; + } + } return ret; } diff --git a/drivers/i2c/designware_i2c_pci.c b/drivers/i2c/designware_i2c_pci.c index ad4122c2abd..db2706fdb6e 100644 --- a/drivers/i2c/designware_i2c_pci.c +++ b/drivers/i2c/designware_i2c_pci.c @@ -168,7 +168,7 @@ static int dw_i2c_acpi_fill_ssdt(const struct udevice *dev, return 0; } -static struct acpi_ops dw_i2c_acpi_ops = { +static const struct acpi_ops dw_i2c_acpi_ops = { .fill_ssdt = dw_i2c_acpi_fill_ssdt, }; diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig index 3b1220b2105..89a4b82458a 100644 --- a/drivers/i2c/muxes/Kconfig +++ b/drivers/i2c/muxes/Kconfig @@ -26,14 +26,14 @@ config I2C_ARB_GPIO_CHALLENGE a GPIO. config I2C_MUX_PCA9541 - tristate "NXP PCA9541 I2C Master Selector" + bool "NXP PCA9541 I2C Master Selector" depends on I2C_MUX help If you say yes here you get support for the NXP PCA9541 I2C Master Selector. config I2C_MUX_PCA954x - tristate "TI PCA954x I2C Mux/switches" + bool "TI PCA954x I2C Mux/switches" depends on I2C_MUX help If you say yes here you get support for the TI PCA954x I2C mux/switch @@ -49,7 +49,7 @@ config I2C_MUX_PCA954x MAX7356, MAX7357, MAX7358, MAX7367, MAX7368 and MAX7369 config I2C_MUX_GPIO - tristate "GPIO-based I2C multiplexer" + bool "GPIO-based I2C multiplexer" depends on I2C_MUX && DM_GPIO select DEVRES help diff --git a/drivers/i2c/nx_i2c.c b/drivers/i2c/nx_i2c.c index 706b7adefe8..5800e79ab70 100644 --- a/drivers/i2c/nx_i2c.c +++ b/drivers/i2c/nx_i2c.c @@ -1,3 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ + #include <errno.h> #include <dm.h> #include <i2c.h> @@ -230,12 +232,13 @@ static void i2c_process_node(struct udevice *dev) static int nx_i2c_probe(struct udevice *dev) { struct nx_i2c_bus *bus = dev_get_priv(dev); - fdt_addr_t addr; + void __iomem *addr; /* get regs = i2c base address */ - addr = devfdt_get_addr(dev); - if (addr == FDT_ADDR_T_NONE) + addr = dev_read_addr_ptr(dev); + if (!addr) return -EINVAL; + bus->regs = (struct nx_i2c_regs *)addr; bus->bus_num = dev_seq(dev); diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig index 48341f9b873..41a4177b3ae 100644 --- a/drivers/i3c/Kconfig +++ b/drivers/i3c/Kconfig @@ -1,5 +1,5 @@ menuconfig I3C - tristate "I3C support" + bool "I3C support" select I2C select DEVRES help diff --git a/drivers/i3c/master/Kconfig b/drivers/i3c/master/Kconfig index 79776f60ae4..63467ef9cc2 100644 --- a/drivers/i3c/master/Kconfig +++ b/drivers/i3c/master/Kconfig @@ -1,5 +1,5 @@ config DW_I3C_MASTER - tristate "Synopsys DesignWare I3C master driver" + bool "Synopsys DesignWare I3C master driver" depends on I3C help Support for Synopsys DesignWare MIPI I3C Controller. diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig index de95a1debdc..04ebc24e8cf 100644 --- a/drivers/led/Kconfig +++ b/drivers/led/Kconfig @@ -133,7 +133,7 @@ config LED_GPIO config SPL_LED_GPIO bool "LED support for GPIO-connected LEDs in SPL" - depends on SPL_LED && SPL_DM_GPIO + depends on SPL_LED && SPL_DM_GPIO help This option is an SPL-variant of the LED_GPIO option. See the help of LED_GPIO for details. diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 591d9d9c656..5f029fd3e70 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -44,18 +44,18 @@ config STM32_OMM This driver manages the muxing between the 2 OSPI busses and the 2 output ports. There are 4 possible muxing configurations: - direct mode (no multiplexing): OSPI1 output is on port 1 and OSPI2 - output is on port 2 + output is on port 2 - OSPI1 and OSPI2 are multiplexed over the same output port 1 - swapped mode (no multiplexing), OSPI1 output is on port 2, - OSPI2 output is on port 1 + OSPI2 output is on port 1 - OSPI1 and OSPI2 are multiplexed over the same output port 2 It also manages : - - the split of the memory area shared between the 2 OSPI instances. - - chip select selection override. - - the time between 2 transactions in multiplexed mode. + - the split of the memory area shared between the 2 OSPI instances. + - chip select selection override. + - the time between 2 transactions in multiplexed mode. config TI_AEMIF - tristate "Texas Instruments AEMIF driver" + bool "Texas Instruments AEMIF driver" depends on ARCH_KEYSTONE || ARCH_DAVINCI help This driver is for the AEMIF module available in Texas Instruments @@ -71,9 +71,9 @@ config TI_GPMC depends on MEMORY && CLK && OF_CONTROL help This driver is for the General Purpose Memory Controller (GPMC) - present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows - interfacing to a variety of asynchronous as well as synchronous - memory drives like NOR, NAND, OneNAND, SRAM. + present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows + interfacing to a variety of asynchronous as well as synchronous + memory drives like NOR, NAND, OneNAND, SRAM. if TI_GPMC config TI_GPMC_DEBUG diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index ae53b02f27c..79f4db9849c 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1,4 +1,4 @@ config MFD_ATMEL_SMC - bool "Atmel Static Memory Controller driver" - help - Say yes here to support Atmel Static Memory Controller driver. + bool "Atmel Static Memory Controller driver" + help + Say yes here to support Atmel Static Memory Controller driver. diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index ea785793d18..44415f24ae1 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -71,9 +71,9 @@ config ATSHA204A select BITREVERSE depends on MISC help - Enable support for I2C connected Atmel's ATSHA204A - CryptoAuthentication module found for example on the Turris Omnia - board. + Enable support for I2C connected Atmel's ATSHA204A + CryptoAuthentication module found for example on the Turris Omnia + board. config GATEWORKS_SC bool "Gateworks System Controller Support" @@ -94,7 +94,7 @@ config QCOM_GENI etc. config ROCKCHIP_EFUSE - bool "Rockchip e-fuse support" + bool "Rockchip e-fuse support" depends on MISC help Enable (read-only) access for the e-fuse block found in Rockchip @@ -505,7 +505,7 @@ config TURRIS_OMNIA_MCU board power off. config USB_HUB_USB251XB - tristate "USB251XB Hub Controller Configuration Driver" + bool "USB251XB Hub Controller Configuration Driver" depends on I2C help This option enables support for configuration via SMBus of the @@ -647,6 +647,7 @@ config IHS_FPGA gdsys devices, which supply the majority of the functionality offered by the devices. This driver supports both CON and CPU variants of the devices, depending on the device tree entry. + config ESM_K3 bool "Enable K3 ESM driver" depends on ARCH_K3 diff --git a/drivers/misc/cros_ec.c b/drivers/misc/cros_ec.c index c3e647edfac..e163224b8e3 100644 --- a/drivers/misc/cros_ec.c +++ b/drivers/misc/cros_ec.c @@ -258,7 +258,7 @@ static int send_command_proto3(struct cros_ec_dev *cdev, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int out_bytes, in_bytes; int rv; @@ -287,7 +287,7 @@ static int send_command(struct cros_ec_dev *dev, uint cmd, int cmd_version, const void *dout, int dout_len, uint8_t **dinp, int din_len) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int ret = -1; /* Handle protocol version 3 support */ @@ -756,9 +756,8 @@ int cros_ec_flash_protect(struct udevice *dev, uint32_t set_mask, static int cros_ec_check_version(struct udevice *dev) { struct cros_ec_dev *cdev = dev_get_uclass_priv(dev); + const struct dm_cros_ec_ops *ops; struct ec_params_hello req; - - struct dm_cros_ec_ops *ops; int ret; ops = dm_cros_ec_get_ops(dev); @@ -1638,7 +1637,7 @@ int cros_ec_vstore_write(struct udevice *dev, int slot, const uint8_t *data, int cros_ec_get_switches(struct udevice *dev) { - struct dm_cros_ec_ops *ops; + const struct dm_cros_ec_ops *ops; int ret; ops = dm_cros_ec_get_ops(dev); diff --git a/drivers/misc/imx_ele/ele_api.c b/drivers/misc/imx_ele/ele_api.c index 8ee0a7733ca..355fd86ed8c 100644 --- a/drivers/misc/imx_ele/ele_api.c +++ b/drivers/misc/imx_ele/ele_api.c @@ -795,6 +795,38 @@ int ele_generate_dek_blob(u32 key_id, u32 src_paddr, u32 dst_paddr, u32 max_outp return ret; } +int ele_v2x_get_state(struct v2x_get_state *state, u32 *response) +{ + struct udevice *dev = gd->arch.ele_dev; + int size = sizeof(struct ele_msg); + struct ele_msg msg = {}; + int ret; + + if (!dev) { + printf("ele dev is not initialized\n"); + return -ENODEV; + } + + msg.version = ELE_VERSION; + msg.tag = ELE_CMD_TAG; + msg.size = 1; + msg.command = ELE_V2X_GET_STATE_REQ; + + ret = misc_call(dev, false, &msg, size, &msg, size); + if (ret) + printf("Error: %s: ret %d, response 0x%x\n", + __func__, ret, msg.data[0]); + + if (response) + *response = msg.data[0]; + + state->v2x_state = msg.data[1] & 0xFF; + state->v2x_power_state = (msg.data[1] & 0xFF00) >> 8; + state->v2x_err_code = msg.data[2]; + + return ret; +} + int ele_volt_change_start_req(void) { struct udevice *dev = gd->arch.ele_dev; diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c index cdb85b999db..65a4779c041 100644 --- a/drivers/misc/imx_ele/ele_mu.c +++ b/drivers/misc/imx_ele/ele_mu.c @@ -209,7 +209,7 @@ static int imx8ulp_mu_probe(struct udevice *dev) debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); - addr = devfdt_get_addr(dev); + addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 0996d9fc30d..f9f7aa5cf97 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -332,7 +332,7 @@ config MMC_MESON_GX bool "Meson GX EMMC controller support" depends on ARCH_MESON help - Support for EMMC host controller on Meson GX ARM SoCs platform (S905) + Support for EMMC host controller on Meson GX ARM SoCs platform (S905) config MMC_OWL bool "Actions OWL Multimedia Card Interface support" @@ -576,7 +576,7 @@ config MMC_SDHCI_ATMEL specification. config MMC_SDHCI_BCM2835 - tristate "SDHCI support for the BCM2835 SD/MMC Controller" + bool "SDHCI support for the BCM2835 SD/MMC Controller" depends on ARCH_BCM283X depends on MMC_SDHCI select MMC_SDHCI_IO_ACCESSORS @@ -589,7 +589,7 @@ config MMC_SDHCI_BCM2835 If unsure, say N. config MMC_SDHCI_BCMSTB - tristate "SDHCI support for the BCMSTB SD/MMC Controller" + bool "SDHCI support for the BCMSTB SD/MMC Controller" depends on MMC_SDHCI && (ARCH_BCMSTB || ARCH_BCM283X) help This selects the Broadcom set-top box SD/MMC controller. @@ -659,8 +659,8 @@ config MMC_SDHCI_MSM depends on MMC_SDHCI && ARCH_SNAPDRAGON help Enables support for SDHCI 2.0 controller present on some Qualcomm - Snapdragon devices. This device is compatible with eMMC v4.5 and - SD 3.0 specifications. Both SD and eMMC devices are supported. + Snapdragon devices. This device is compatible with eMMC v4.5 and + SD 3.0 specifications. Both SD and eMMC devices are supported. Card-detect gpios are not supported. config MMC_SDHCI_MV @@ -852,12 +852,13 @@ config FTSDC010_SDIO bool "Support ftsdc010 sdio" depends on FTSDC010 help - This can enable ftsdc010 sdio function. + This can enable ftsdc010 sdio function. config MMC_MTK bool "MediaTek SD/MMC Card Interface support" depends on ARCH_MEDIATEK || ARCH_MTMIPS || ARCH_AIROHA depends on OF_CONTROL + imply LMB_LIMIT_DMA_BELOW_RAM_TOP help This selects the MediaTek(R) Secure digital and Multimedia card Interface. If you have a machine with a integrated SD/MMC card reader, say Y here. diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index f0e38efb262..2e565560656 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2721,10 +2721,11 @@ static int mmc_startup(struct mmc *mmc) #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) /* - * If the card has already switched to 1.8V signaling, then - * set the signal voltage to 1.8V. + * If voltage switch was skipped during ACMD41 but the card is + * already at 1.8V (retained from a previous session, e.g. warm + * reboot), re-configure the host to match. */ - if (mmc_sd_card_using_v18(mmc)) { + if (!(mmc->ocr & OCR_S18R) && mmc_sd_card_using_v18(mmc)) { /* * During a signal voltage level switch, the clock must be gated * for 5 ms according to the SD spec. diff --git a/drivers/mmc/pci_mmc.c b/drivers/mmc/pci_mmc.c index d446c55f72b..82e393fd9d6 100644 --- a/drivers/mmc/pci_mmc.c +++ b/drivers/mmc/pci_mmc.c @@ -137,11 +137,11 @@ static int pci_mmc_acpi_fill_ssdt(const struct udevice *dev, return 0; } -struct acpi_ops pci_mmc_acpi_ops = { #ifdef CONFIG_ACPIGEN +static const struct acpi_ops pci_mmc_acpi_ops = { .fill_ssdt = pci_mmc_acpi_fill_ssdt, -#endif }; +#endif static const struct udevice_id pci_mmc_match[] = { { .compatible = "intel,apl-sd", .data = TYPE_SD }, diff --git a/drivers/mmc/sdhci-cadence.c b/drivers/mmc/sdhci-cadence.c index a76f9e8d6bd..5bbc18dfa51 100644 --- a/drivers/mmc/sdhci-cadence.c +++ b/drivers/mmc/sdhci-cadence.c @@ -39,9 +39,6 @@ static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = { { "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, }, }; -static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev, - unsigned int opcode); - static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_plat *plat, u8 addr, u8 data) { @@ -158,93 +155,8 @@ static void sdhci_cdns_set_control_reg(struct sdhci_host *host) sdhci_cdns6_phy_adj(mmc->dev, plat, mmc->selected_mode); } -static __maybe_unused bool sdhci_cdns_sd_needs_tuning(struct mmc *mmc) -{ - struct sdhci_cdns_plat *plat = dev_get_plat(mmc->dev); - - if (!IS_SD(mmc)) - return false; - - if (!dev_read_bool(mmc->dev, "cdns,sd-hs-tuning")) - return false; - - /* Already tuned for this mode */ - if (plat->tuned_mode == mmc->selected_mode) - return false; - - switch (mmc->selected_mode) { - case SD_HS: - return mmc->bus_width == 4; - /* Add future modes here, e.g.: - * case UHS_SDR50: - * return true; - */ - default: - return false; - } -} - -static int sdhci_cdns_set_ios_post(struct sdhci_host *host) -{ - struct mmc *mmc = host->mmc; - struct sdhci_cdns_plat *plat = dev_get_plat(mmc->dev); - int ret __maybe_unused; - /* - * The SD6HC soft PHY requires runtime DLL delay calibration - * for SD High Speed mode. The default PHY_DLL_SLAVE_CTRL_REG - * values (READ_DQS_CMD_DELAY and READ_DQS_DELAY = 0) do not - * provide sufficient timing margin due to PVT and board trace - * variations. - * - * Tuning is performed once per entry into SD_HS mode - * (tracked by plat->tuned_mode state). The calibrated PHY delay - * values remain valid while the card stays in SD_HS mode, and - * leaving that tuned mode clears the state so re-entering SD_HS - * triggers tuning again. - * - * This must be done in set_ios_post (not set_control_reg) - * because the SDHCI controller must already be operating at - * the target bus width, clock, and speed mode before CMD19 - * tuning commands can succeed. - */ - - if (IS_ENABLED(CONFIG_MMC_SUPPORTS_TUNING)) { - if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_420 && - sdhci_cdns_sd_needs_tuning(mmc)) { - ret = sdhci_cdns_execute_tuning(mmc->dev, - MMC_CMD_SEND_TUNING_BLOCK); - if (ret) { - dev_err(mmc->dev, - "SD_HS tuning failed (ret=%d), using default PHY\n", - ret); - /* Restore default PHY settings and avoid retrying in this mode */ - sdhci_cdns6_phy_adj(mmc->dev, plat, - mmc->selected_mode); - plat->tuned_mode = mmc->selected_mode; - plat->tuned_dll_slave_ctrl = sdhci_cdns6_phy_get_dll_slave(plat); - return 0; - } - /* - * Tuning succeeded. The tuned_mode is already set by - * execute_tuning(), so the tuned value will be preserved - * across subsequent PHY reconfigurations. - */ - dev_dbg(mmc->dev, "SD_HS tuning successful\n"); - } - - /* Reset when mode changes away from a tuned mode */ - if (mmc->selected_mode != plat->tuned_mode) { - plat->tuned_mode = MMC_MODES_END; - plat->tuned_dll_slave_ctrl = 0; - } - } - - return 0; -} - static const struct sdhci_ops sdhci_cdns_ops = { .set_control_reg = sdhci_cdns_set_control_reg, - .set_ios_post = sdhci_cdns_set_ios_post, }; static int sdhci_cdns_set_tune_val(struct sdhci_cdns_plat *plat, @@ -292,7 +204,6 @@ static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev, int cur_streak = 0; int max_streak = 0; int end_of_streak = 0; - int ret; int i; /* @@ -318,24 +229,7 @@ static int __maybe_unused sdhci_cdns_execute_tuning(struct udevice *dev, return -EIO; } - ret = sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2); - if (ret) - return ret; - - /* - * Mark this mode as tuned. This is critical for both driver tuning - * (SD_HS via set_ios_post) and framework tuning (UHS_SDR104, MMC_HS_200, - * MMC_HS_400) so that subsequent PHY reconfigurations restore the - * calibrated DLL value instead of overwriting with DT defaults. - * - * For HS400, tuning is performed while the controller is in HS200 mode - * (mmc->selected_mode == MMC_HS_200 and mmc->hs400_tuning == true). - * Record the tuned mode as MMC_HS_400 so the calibrated DLL value is - * preserved across the HS200→HS400 transition. - */ - plat->tuned_mode = mmc->hs400_tuning ? MMC_HS_400 : mmc->selected_mode; - - return 0; + return sdhci_cdns_set_tune_val(plat, end_of_streak - max_streak / 2); } static struct dm_mmc_ops sdhci_cdns_mmc_ops; diff --git a/drivers/mmc/sdhci-cadence.h b/drivers/mmc/sdhci-cadence.h index ea517491860..7101f00b75b 100644 --- a/drivers/mmc/sdhci-cadence.h +++ b/drivers/mmc/sdhci-cadence.h @@ -7,8 +7,6 @@ #ifndef SDHCI_CADENCE_H_ #define SDHCI_CADENCE_H_ -#include <mmc.h> - /* HRS - Host Register Set (specific to Cadence) */ /* PHY access port */ #define SDHCI_CDNS_HRS04 0x10 @@ -62,13 +60,10 @@ struct sdhci_cdns_plat { struct mmc_config cfg; struct mmc mmc; void __iomem *hrs_addr; - enum bus_mode tuned_mode; - u32 tuned_dll_slave_ctrl; }; int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 mode); int sdhci_cdns6_phy_init(struct udevice *dev, struct sdhci_cdns_plat *plat); int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val); -u32 sdhci_cdns6_phy_get_dll_slave(struct sdhci_cdns_plat *plat); #endif diff --git a/drivers/mmc/sdhci-cadence6.c b/drivers/mmc/sdhci-cadence6.c index c8b42532e17..ca1086e2359 100644 --- a/drivers/mmc/sdhci-cadence6.c +++ b/drivers/mmc/sdhci-cadence6.c @@ -173,30 +173,6 @@ static void sdhci_cdns6_write_phy_reg(struct sdhci_cdns_plat *plat, u32 addr, u3 writel(val, plat->hrs_addr + SDHCI_CDNS_HRS05); } -static bool sdhci_cdns6_mode_is_tuned(struct sdhci_cdns_plat *plat, u32 mode) -{ - /* - * Check if the given mode has a valid tuned DLL value. - * Only modes that support tuning (driver or framework) can have - * valid tuned values. This prevents the initial state (tuned_mode=0) - * from falsely matching MMC_LEGACY. - */ - if (plat->tuned_mode != mode) - return false; - - switch (mode) { - case SD_HS: /* Driver tuning via set_ios_post */ - case UHS_SDR50: /* Future driver tuning support */ - case UHS_SDR104: /* Framework tuning */ - case MMC_HS_200: /* Framework tuning */ - case MMC_HS_400: /* Framework tuning */ - case MMC_HS_400_ES: /* Framework tuning */ - return true; - default: - return false; - } -} - static int sdhci_cdns6_reset_phy_dll(struct sdhci_cdns_plat *plat, bool reset) { void __iomem *reg = plat->hrs_addr + SDHCI_CDNS_HRS09; @@ -283,18 +259,7 @@ int sdhci_cdns6_phy_adj(struct udevice *dev, struct sdhci_cdns_plat *plat, u32 m sdhci_cdns6_write_phy_reg(plat, PHY_DQS_TIMING_REG_ADDR, sdhci_cdns6_phy_cfgs[0].val); sdhci_cdns6_write_phy_reg(plat, PHY_GATE_LPBK_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[1].val); sdhci_cdns6_write_phy_reg(plat, PHY_DLL_MASTER_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[4].val); - if (sdhci_cdns6_mode_is_tuned(plat, mode)) { - /* - * Use previously saved tuned DLL slave control value. - * Note: 0 is a valid tuned value (e.g., optimal tap at position 0), - * so we check both mode match AND that it's a tunable mode. - */ - sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, - plat->tuned_dll_slave_ctrl); - } else { - sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, - sdhci_cdns6_phy_cfgs[2].val); - } + sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, sdhci_cdns6_phy_cfgs[2].val); /* Switch Off the DLL Reset */ ret = sdhci_cdns6_reset_phy_dll(plat, false); @@ -353,9 +318,6 @@ int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val) sdhci_cdns6_write_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR, tmp); - /* Store tuned DLL slave control value which will be reapplied via set_ios(). */ - plat->tuned_dll_slave_ctrl = tmp; - /* Switch Off the DLL Reset */ ret = sdhci_cdns6_reset_phy_dll(plat, false); if (ret) { @@ -365,8 +327,3 @@ int sdhci_cdns6_set_tune_val(struct sdhci_cdns_plat *plat, unsigned int val) return 0; } - -u32 sdhci_cdns6_phy_get_dll_slave(struct sdhci_cdns_plat *plat) -{ - return sdhci_cdns6_read_phy_reg(plat, PHY_DLL_SLAVE_CTRL_REG_ADDR); -} diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig index 21b8b21f6b2..38d6dd142dd 100644 --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig @@ -205,16 +205,16 @@ config HBMC_AM654 bool "HyperBus controller driver for AM65x SoC" depends on MULTIPLEXER && (MUX_MMIO || SPL_MUX_MMIO) help - This is the driver for HyperBus controller on TI's AM65x and - other SoCs + This is the driver for HyperBus controller on TI's AM65x and + other SoCs config STM32_FLASH bool "STM32 MCU Flash driver" depends on ARCH_STM32 select USE_SYS_MAX_FLASH_BANKS help - This is the driver of embedded flash for some STMicroelectronics - STM32 MCU. + This is the driver of embedded flash for some STMicroelectronics + STM32 MCU. config SYS_MAX_FLASH_SECT int "Maximum number of sectors on a flash chip" @@ -236,17 +236,17 @@ config SYS_MAX_FLASH_BANKS depends on USE_SYS_MAX_FLASH_BANKS default 1 help - Max number of Flash memory banks using by the MTD framework, in the - flash CFI driver and in some other driver to define the flash_info - struct declaration. + Max number of Flash memory banks using by the MTD framework, in the + flash CFI driver and in some other driver to define the flash_info + struct declaration. config SYS_MAX_FLASH_BANKS_DETECT bool "Detection of flash banks number in CFI driver" depends on CFI_FLASH && FLASH_CFI_DRIVER help - This enables detection of number of flash banks in CFI driver, - to reduce the effective number of flash bank, between 0 and - CONFIG_SYS_MAX_FLASH_BANKS + This enables detection of number of flash banks in CFI driver, + to reduce the effective number of flash bank, between 0 and + CONFIG_SYS_MAX_FLASH_BANKS source "drivers/mtd/nand/Kconfig" diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 78ae04bdcba..5ffec9502b6 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -1,5 +1,5 @@ config MTD_NAND_CORE - tristate + bool source "drivers/mtd/nand/raw/Kconfig" diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 2999e6b1710..b5dfad7380f 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -310,47 +310,47 @@ choice prompt "ECC scheme" default NAND_OMAP_ECCSCHEME_BCH8_CODE_HW help - On OMAP platforms, this CONFIG specifies NAND ECC scheme. - It can take following values: - OMAP_ECC_HAM1_CODE_SW + On OMAP platforms, this CONFIG specifies NAND ECC scheme. + It can take following values: + OMAP_ECC_HAM1_CODE_SW 1-bit Hamming code using software lib. (for legacy devices only) - OMAP_ECC_HAM1_CODE_HW + OMAP_ECC_HAM1_CODE_HW 1-bit Hamming code using GPMC hardware. (for legacy devices only) - OMAP_ECC_BCH4_CODE_HW_DETECTION_SW + OMAP_ECC_BCH4_CODE_HW_DETECTION_SW 4-bit BCH code (unsupported) - OMAP_ECC_BCH4_CODE_HW + OMAP_ECC_BCH4_CODE_HW 4-bit BCH code (unsupported) - OMAP_ECC_BCH8_CODE_HW_DETECTION_SW + OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 8-bit BCH code with - ecc calculation using GPMC hardware engine, - error detection using software library. - requires CONFIG_BCH to enable software BCH library (For legacy device which do not have ELM h/w engine) - OMAP_ECC_BCH8_CODE_HW + OMAP_ECC_BCH8_CODE_HW 8-bit BCH code with - ecc calculation using GPMC hardware engine, - error detection using ELM hardware engine. - OMAP_ECC_BCH16_CODE_HW + OMAP_ECC_BCH16_CODE_HW 16-bit BCH code with - ecc calculation using GPMC hardware engine, - error detection using ELM hardware engine. - How to select ECC scheme on OMAP and AMxx platforms ? - ----------------------------------------------------- - Though higher ECC schemes have more capability to detect and correct - bit-flips, but still selection of ECC scheme is dependent on following - - hardware engines present in SoC. + How to select ECC scheme on OMAP and AMxx platforms ? + ----------------------------------------------------- + Though higher ECC schemes have more capability to detect and correct + bit-flips, but still selection of ECC scheme is dependent on following + - hardware engines present in SoC. Some legacy OMAP SoC do not have ELM h/w engine thus such SoC cannot support BCHx_HW ECC schemes. - - size of OOB/Spare region + - size of OOB/Spare region With higher ECC schemes, more OOB/Spare area is required to store ECC. So choice of ECC scheme is limited by NAND oobsize. - In general following expression can help: + In general following expression can help: NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES - where + where NAND_OOBSIZE = number of bytes available in OOB/spare area per NAND page. NAND_PAGESIZE = bytes in main-area of NAND page. diff --git a/drivers/mtd/nand/raw/rockchip_nfc.c b/drivers/mtd/nand/raw/rockchip_nfc.c index f730e15d041..ea8e67d1a23 100644 --- a/drivers/mtd/nand/raw/rockchip_nfc.c +++ b/drivers/mtd/nand/raw/rockchip_nfc.c @@ -861,6 +861,15 @@ static int rk_nfc_ecc_init(struct rk_nfc *nfc, struct nand_chip *chip) ecc->steps = mtd->writesize / ecc->size; ecc->bytes = DIV_ROUND_UP(ecc->strength * fls(8 * chip->ecc.size), 8); + rknand->metadata_size = NFC_SYS_DATA_SIZE * ecc->steps; + + if (rknand->metadata_size < NFC_SYS_DATA_SIZE + 2) { + dev_err(nfc->dev, + "driver needs at least %d bytes of meta data\n", + NFC_SYS_DATA_SIZE + 2); + return -EIO; + } + if (ecc->bytes * ecc->steps > mtd->oobsize - rknand->metadata_size) return -EINVAL; @@ -974,15 +983,6 @@ static int rk_nfc_nand_chip_init(ofnode node, struct rk_nfc *nfc, int devnum) ret = ofnode_read_u32(node, "rockchip,boot-ecc-strength", &tmp); rknand->boot_ecc = ret ? ecc->strength : tmp; - rknand->metadata_size = NFC_SYS_DATA_SIZE * ecc->steps; - - if (rknand->metadata_size < NFC_SYS_DATA_SIZE + 2) { - dev_err(dev, - "driver needs at least %d bytes of meta data\n", - NFC_SYS_DATA_SIZE + 2); - return -EIO; - } - if (!nfc->page_buf) { nfc->page_buf = kzalloc(NFC_MAX_PAGE_SIZE, GFP_KERNEL); if (!nfc->page_buf) { diff --git a/drivers/mtd/nand/raw/sunxi_nand.h b/drivers/mtd/nand/raw/sunxi_nand.h index d7a8b3dd40c..1b2c514852d 100644 --- a/drivers/mtd/nand/raw/sunxi_nand.h +++ b/drivers/mtd/nand/raw/sunxi_nand.h @@ -24,10 +24,7 @@ #define SUNXI_NAND_H #include <linux/bitops.h> - -/* non compile-time field get/prep */ -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) +#include <linux/bitfield.h> #define NFC_REG_CTL 0x0000 #define NFC_REG_ST 0x0004 diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index de78a6cb707..4ff58380b59 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -94,39 +94,39 @@ config SPI_FLASH_SFDP_SUPPORT bool "SFDP table parsing support for SPI NOR flashes" depends on !SPI_FLASH_BAR help - Enable support for parsing and auto discovery of parameters for - SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) - tables as per JESD216 standard. + Enable support for parsing and auto discovery of parameters for + SPI NOR flashes using Serial Flash Discoverable Parameters (SFDP) + tables as per JESD216 standard. config SPI_FLASH_SMART_HWCAPS bool "Smart hardware capability detection based on SPI MEM supports_op() hook" default y help - Enable support for smart hardware capability detection based on SPI - MEM supports_op() hook that lets controllers express whether they - can support a type of operation in a much more refined way compared - to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc. + Enable support for smart hardware capability detection based on SPI + MEM supports_op() hook that lets controllers express whether they + can support a type of operation in a much more refined way compared + to using flags like SPI_RX_DUAL, SPI_TX_QUAD, etc. config SPI_NOR_BOOT_SOFT_RESET_EXT_INVERT bool "Command extension type is INVERT for Software Reset on boot" help - Because of SFDP information can not be get before boot. - So define command extension type is INVERT when Software Reset on boot only. + Because of SFDP information can not be get before boot. + So define command extension type is INVERT when Software Reset on boot only. config SPI_FLASH_SOFT_RESET bool "Software Reset support for SPI NOR flashes" help - Enable support for xSPI Software Reset. It will be used to switch from - Octal DTR mode to legacy mode on shutdown and boot (if enabled). + Enable support for xSPI Software Reset. It will be used to switch from + Octal DTR mode to legacy mode on shutdown and boot (if enabled). config SPI_FLASH_SOFT_RESET_ON_BOOT bool "Perform a Software Reset on boot on flashes that boot in stateful mode" depends on SPI_FLASH_SOFT_RESET help - Perform a Software Reset on boot to allow detecting flashes that are - handed to us in Octal DTR mode. Do not enable this config on flashes - that are not supposed to be handed to U-Boot in Octal DTR mode, even - if they _do_ support the Soft Reset sequence. + Perform a Software Reset on boot to allow detecting flashes that are + handed to us in Octal DTR mode. Do not enable this config on flashes + that are not supposed to be handed to U-Boot in Octal DTR mode, even + if they _do_ support the Soft Reset sequence. config SPI_FLASH_BAR bool "SPI flash Bank/Extended address register support" @@ -139,18 +139,18 @@ config SPI_FLASH_LOCK bool "Enable the Locking feature" default y help - Enable the SPI flash lock support. By default this is set to y. - If you intend not to use the lock support you should say n here. + Enable the SPI flash lock support. By default this is set to y. + If you intend not to use the lock support you should say n here. config SPI_FLASH_UNLOCK_ALL bool "Unlock the entire SPI flash on u-boot startup" default y help - Some flashes tend to power up with the software write protection - bits set. If this option is set, the whole flash will be unlocked. + Some flashes tend to power up with the software write protection + bits set. If this option is set, the whole flash will be unlocked. - For legacy reasons, this option default to y. But if you intend to - actually use the software protection bits you should say n here. + For legacy reasons, this option default to y. But if you intend to + actually use the software protection bits you should say n here. config SPI_FLASH_ATMEL bool "Atmel SPI flash support" @@ -201,9 +201,9 @@ config SPI_FLASH_S28HX_T bool "Cypress SEMPER Octal (S28) chip support" depends on SPI_FLASH_SPANSION help - Add support for the Cypress S28HL-T and S28HS-T chip. This is a separate - config because the fixup hooks for this flash add extra size overhead. - Boards that don't use the flash can disable this to save space. + Add support for the Cypress S28HL-T and S28HS-T chip. This is a separate + config because the fixup hooks for this flash add extra size overhead. + Boards that don't use the flash can disable this to save space. config SPI_FLASH_STMICRO bool "STMicro SPI flash support" @@ -214,9 +214,9 @@ config SPI_FLASH_MT35XU bool "Micron MT35XU chip support" depends on SPI_FLASH_STMICRO help - Add support for the Micron MT35XU chip. This is a separate config - because the fixup hooks for this flash add extra size overhead. Boards - that don't use the flash can disable this to save space. + Add support for the Micron MT35XU chip. This is a separate config + because the fixup hooks for this flash add extra size overhead. Boards + that don't use the flash can disable this to save space. config SPI_FLASH_SST bool "SST SPI flash support" @@ -282,7 +282,7 @@ config SPI_FLASH_MTD bool "SPI Flash MTD support" depends on SPI_FLASH && MTD help - Enable the MTD support for spi flash layer, this adapter is for + Enable the MTD support for spi flash layer, this adapter is for translating mtd_read/mtd_write commands into spi_flash_read/write commands. It is not intended to use it within sf_cmd or the SPI flash subsystem. Such an adapter is needed for subsystems like @@ -294,7 +294,7 @@ config SPL_SPI_FLASH_MTD bool "SPI flash MTD support for SPL" depends on SPI_FLASH && SPL help - Enable the MTD support for the SPI flash layer in SPL. + Enable the MTD support for the SPI flash layer in SPL. If unsure, say N diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index c0fa98424aa..31a2ba49a87 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -231,6 +231,10 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd55lb02gf", 0xc8601c, 0, 64 * 1024, 4096, + SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig index ba77c034736..e523a4c4707 100644 --- a/drivers/mtd/ubi/Kconfig +++ b/drivers/mtd/ubi/Kconfig @@ -82,8 +82,8 @@ config MTD_UBI_BEB_LIMIT config MTD_UBI_FASTMAP bool "UBI Fastmap (Experimental feature)" help - Important: this feature is experimental so far and the on-flash - format for fastmap may change in the next kernel versions + Important: this feature is experimental so far and the on-flash + format for fastmap may change in the next kernel versions Fastmap is a mechanism which allows attaching an UBI device in nearly constant time. Instead of scanning the whole MTD device it diff --git a/drivers/mux/Kconfig b/drivers/mux/Kconfig index de74e5d5e4e..383dac532c1 100644 --- a/drivers/mux/Kconfig +++ b/drivers/mux/Kconfig @@ -5,17 +5,17 @@ config MULTIPLEXER depends on DM select DEVRES help - The mux framework is a minimalistic subsystem that handles multiplexer - controllers. It provides the same API as Linux and mux drivers should - be portable with a minimum effort. + The mux framework is a minimalistic subsystem that handles multiplexer + controllers. It provides the same API as Linux and mux drivers should + be portable with a minimum effort. if MULTIPLEXER config SPL_MUX_MMIO bool "MMIO register bitfield-controlled Multiplexer" - depends on MULTIPLEXER && SYSCON - help - MMIO register bitfield-controlled Multiplexer controller. + depends on MULTIPLEXER && SYSCON + help + MMIO register bitfield-controlled Multiplexer controller. The driver builds multiplexer controllers for bitfields in a syscon register. For N bit wide bitfields, there will be 2^N possible diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 5172b2bae8e..4399c6c7a99 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -184,10 +184,10 @@ config CALXEDA_XGMAC config DWC_ETH_XGMAC bool select PHYLIB - help - This driver supports the Synopsys Designware Ethernet XGMAC (10G - Ethernet MAC) IP block. The IP supports many options for bus type, - clocking/reset structure, and feature list. + help + This driver supports the Synopsys Designware Ethernet XGMAC (10G + Ethernet MAC) IP block. The IP supports many options for bus type, + clocking/reset structure, and feature list. config DWC_ETH_XGMAC_SOCFPGA bool "Synopsys DWC Ethernet XGMAC device support for SOCFPGA" @@ -229,8 +229,8 @@ config DWC_ETH_QOS_ADI bool "Synopsys DWC Ethernet QOS device support for ADI SC59x-64 parts" depends on DWC_ETH_QOS && ARCH_SC5XX help - The Synopsis Designware Ethernet QoS IP block with the specific - configuration used in the ADI ADSP-SC59X 64 bit SoCs + The Synopsis Designware Ethernet QoS IP block with the specific + configuration used in the ADI ADSP-SC59X 64 bit SoCs config DWC_ETH_QOS_IMX bool "Synopsys DWC Ethernet QOS device support for IMX" @@ -467,9 +467,9 @@ config FSL_FM_10GEC_REGULAR_NOTATION help On SoCs T4240, T2080, LS1043A, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 + 10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2 While on SoCs T1024, etc, the notation between 10GEC and MAC as below: - 10GEC1->MAC1, 10GEC2->MAC2 + 10GEC1->MAC1, 10GEC2->MAC2 so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on which 10GEC enumeration is consistent with MAC enumeration. @@ -536,7 +536,7 @@ config KSZ9477 config LITEETH bool "LiteX LiteEth Ethernet MAC" help - Driver for the LiteEth Ethernet MAC from LiteX. + Driver for the LiteEth Ethernet MAC from LiteX. config MV88E6XXX bool "Marvell MV88E6xxx Ethernet switch DSA driver" @@ -708,12 +708,12 @@ config SJA1105 family. These are 5-port devices and are managed over an SPI interface. Probing is handled based on OF bindings. The driver supports the following revisions: - - SJA1105E (Gen. 1, No TT-Ethernet) - - SJA1105T (Gen. 1, TT-Ethernet) - - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet) - - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet) - - SJA1105R (Gen. 2, SGMII, No TT-Ethernet) - - SJA1105S (Gen. 2, SGMII, TT-Ethernet) + - SJA1105E (Gen. 1, No TT-Ethernet) + - SJA1105T (Gen. 1, TT-Ethernet) + - SJA1105P (Gen. 2, No SGMII, No TT-Ethernet) + - SJA1105Q (Gen. 2, No SGMII, TT-Ethernet) + - SJA1105R (Gen. 2, SGMII, No TT-Ethernet) + - SJA1105S (Gen. 2, SGMII, TT-Ethernet) config SMC911X bool "SMSC LAN911x and LAN921x controller driver" @@ -747,11 +747,11 @@ config SUN4I_EMAC This driver supports the Allwinner based SUN4I Ethernet MAC. config SUN8I_EMAC - bool "Allwinner Sun8i Ethernet MAC support" - select PHYLIB + bool "Allwinner Sun8i Ethernet MAC support" + select PHYLIB select PHY_GIGE - help - This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC. + help + This driver supports the Allwinner based SUN8I/SUN50I Ethernet MAC. It can be found in H3/A64/A83T based SoCs and compatible with both External and Internal PHYs. @@ -912,7 +912,7 @@ config FEC1_PHY help Define to the hardcoded PHY address which corresponds to the given FEC; i. e. - #define CONFIG_FEC1_PHY 4 + #define CONFIG_FEC1_PHY 4 means that the PHY with address 4 is connected to FEC1 When set to -1, means to probe for first available. @@ -936,7 +936,7 @@ config FEC2_PHY help Define to the hardcoded PHY address which corresponds to the given FEC; i. e. - #define CONFIG_FEC1_PHY 4 + #define CONFIG_FEC1_PHY 4 means that the PHY with address 4 is connected to FEC1 When set to -1, means to probe for first available. @@ -1041,7 +1041,7 @@ config MDIO_GPIO_BITBANG bool "GPIO bitbanging MDIO driver" depends on DM_MDIO && DM_GPIO help - Driver for bitbanging MDIO + Driver for bitbanging MDIO config MDIO_MUX_I2CREG bool "MDIO MUX accessed as a register over I2C" @@ -1087,8 +1087,8 @@ config MDIO_MSCC_MIIM depends on DM_MDIO select REGMAP help - This driver supports MDIO interface found in Microsemi and Microchip - network switches. + This driver supports MDIO interface found in Microsemi and Microchip + network switches. config MDIO_MUX_MMIOREG bool "MDIO MUX accessed as a MMIO register access" diff --git a/drivers/net/airoha_eth.c b/drivers/net/airoha_eth.c index 84ee9b2ad76..e5d39b95cc5 100644 --- a/drivers/net/airoha_eth.c +++ b/drivers/net/airoha_eth.c @@ -845,11 +845,45 @@ static int airoha_alloc_gdm_port(struct udevice *dev, ofnode node) (ulong)eth, node, &gdm_dev); } +static struct udevice *airoha_switch_mdio_init(struct udevice *dev) +{ + struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev); + ofnode switch_node, mdio_node; + struct udevice *mdio_dev; + int ret; + + if (!CONFIG_IS_ENABLED(MDIO_MT7531_MMIO)) + return NULL; + + switch_node = ofnode_by_compatible(ofnode_null(), + data->switch_compatible); + if (!ofnode_valid(switch_node)) { + debug("Warning: missing airoha switch node\n"); + return ERR_PTR(-EINVAL); + } + + mdio_node = ofnode_find_subnode(switch_node, "mdio"); + if (!ofnode_valid(mdio_node)) { + debug("Warning: missing airoha switch mdio subnode\n"); + return ERR_PTR(-EINVAL); + } + + ret = device_bind_driver_to_node(dev, "mt7531-mdio-mmio", "mt7531-mdio", + mdio_node, &mdio_dev); + if (ret) { + debug("Warning: failed to bind airoha switch mdio\n"); + return ERR_PTR(ret); + } + + return mdio_dev; +} + static int airoha_eth_probe(struct udevice *dev) { struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev); struct airoha_eth *eth = dev_get_priv(dev); struct regmap *scu_regmap; + struct udevice *mdio_dev; ofnode node; int i, ret; @@ -908,10 +942,10 @@ static int airoha_eth_probe(struct udevice *dev) if (ret) return ret; - if (eth->switch_mdio_dev) { - if (!device_probe(eth->switch_mdio_dev)) - debug("Warning: failed to probe airoha switch mdio\n"); - } + /* Airoha switch mdio PHYs maybe used by several GDM devices */ + mdio_dev = airoha_switch_mdio_init(dev); + if (!IS_ERR_OR_NULL(mdio_dev)) + eth->switch_mdio_dev = mdio_dev; ofnode_for_each_subnode(node, dev_ofnode(dev)) { if (!ofnode_device_is_compatible(node, "airoha,eth-mac")) @@ -957,6 +991,16 @@ static int airoha_eth_port_probe(struct udevice *dev) #else return -EINVAL; #endif + } else { + /* + * GDM1 device connected to airoha switch. Probe airoha switch + * mdio to be able set/query states of corresponding LAN ports. + */ + ret = device_probe(eth->switch_mdio_dev); + if (ret) { + debug("Warning: failed to probe airoha switch mdio\n"); + eth->switch_mdio_dev = NULL; + } } return 0; @@ -1202,38 +1246,12 @@ static int arht_eth_write_hwaddr(struct udevice *dev) static int airoha_eth_bind(struct udevice *dev) { - struct airoha_eth_soc_data *data = (void *)dev_get_driver_data(dev); - struct airoha_eth *eth = dev_get_priv(dev); - ofnode switch_node, mdio_node; - int ret; - /* * Force Probe as we set the Main ETH driver as misc * to register multiple eth port for each GDM */ dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); - if (!CONFIG_IS_ENABLED(MDIO_MT7531_MMIO)) - return 0; - - switch_node = ofnode_by_compatible(ofnode_null(), - data->switch_compatible); - if (!ofnode_valid(switch_node)) { - debug("Warning: missing switch node\n"); - return 0; - } - - mdio_node = ofnode_find_subnode(switch_node, "mdio"); - if (!ofnode_valid(mdio_node)) { - debug("Warning: missing mdio node\n"); - return 0; - } - - ret = device_bind_driver_to_node(dev, "mt7531-mdio-mmio", "mt7531-mdio", - mdio_node, ð->switch_mdio_dev); - if (ret) - debug("Warning: failed to bind mdio controller\n"); - return 0; } diff --git a/drivers/net/hifemac.c b/drivers/net/hifemac.c index 62182f922f8..7dda8cb8815 100644 --- a/drivers/net/hifemac.c +++ b/drivers/net/hifemac.c @@ -401,9 +401,6 @@ static void hisi_femac_get_strings(struct udevice *dev, u8 *data) strcpy(data + i * ETH_GSTRING_LEN, hisi_femac_stats_table[i].name); } -/* Non-constant mask variant of FIELD_GET/FIELD_PREP */ -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) - static void hisi_femac_get_stats(struct udevice *dev, u64 *data) { int i; diff --git a/drivers/net/mtk_eth/Kconfig b/drivers/net/mtk_eth/Kconfig index 5d4e54ab90e..7d58f542bde 100644 --- a/drivers/net/mtk_eth/Kconfig +++ b/drivers/net/mtk_eth/Kconfig @@ -5,6 +5,7 @@ config MEDIATEK_ETH select PHYLIB select DM_GPIO select DM_RESET + select LMB_LIMIT_DMA_BELOW_RAM_TOP help This Driver support MediaTek Ethernet GMAC Say Y to enable support for the MediaTek Ethernet GMAC. diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 0025c895f12..ee438524490 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -81,7 +81,7 @@ config PHYLIB_10G config PHY_ADIN bool "Analog Devices Industrial Ethernet PHYs" help - Add support for configuring RGMII on Analog Devices ADIN PHYs. + Add support for configuring RGMII on Analog Devices ADIN PHYs. menuconfig PHY_AQUANTIA bool "Aquantia Ethernet PHYs support" @@ -126,9 +126,9 @@ config SYS_CORTINA_NO_FW_UPLOAD bool "Cortina firmware loading support" depends on PHY_CORTINA help - Cortina phy has provision to store phy firmware in attached dedicated - EEPROM. And boards designed with such EEPROM does not require firmware - upload. + Cortina phy has provision to store phy firmware in attached dedicated + EEPROM. And boards designed with such EEPROM does not require firmware + upload. choice prompt "Location of the Cortina firmware" @@ -167,7 +167,7 @@ config PHY_CORTINA_ACCESS default y depends on CORTINA_NI_ENET help - Cortina Access Ethernet PHYs init process + Cortina Access Ethernet PHYs init process config PHY_DAVICOM bool "Davicom Ethernet PHYs support" @@ -233,7 +233,7 @@ config PHY_MICREL_KSZ8XXX endif # PHY_MICREL config PHY_MOTORCOMM - tristate "Motorcomm PHYs" + bool "Motorcomm PHYs" help Enables support for Motorcomm network PHYs. Currently supports the YT8511 and YT8531 Gigabit Ethernet PHYs. @@ -246,7 +246,7 @@ config PHY_NATSEMI bool "National Semiconductor Ethernet PHYs support" config PHY_NXP_C45_TJA11XX - tristate "NXP C45 TJA11XX PHYs" + bool "NXP C45 TJA11XX PHYs" select DEVRES help Enable support for NXP C45 TJA11XX PHYs. @@ -317,13 +317,13 @@ config PHY_TERANETICS config PHY_TI bool "Texas Instruments Ethernet PHYs support" - ---help--- + help Adds PHY registration support for TI PHYs. config PHY_TI_DP83867 select PHY_TI bool "Texas Instruments Ethernet DP83867 PHY support" - ---help--- + help Adds support for the TI DP83867 1Gbit PHY. config SPL_PHY_TI_DP83867 @@ -333,13 +333,13 @@ config SPL_PHY_TI_DP83867 config PHY_TI_DP83869 select PHY_TI bool "Texas Instruments Ethernet DP83869 PHY support" - ---help--- + help Adds support for the TI DP83869 1Gbit PHY. config PHY_TI_GENERIC select PHY_TI bool "Texas Instruments Generic Ethernet PHYs support" - ---help--- + help Adds support for Generic TI PHYs that don't need special handling but the PHY name is associated with a PHY ID. diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig index 93c3a0c35f2..2d72af8aade 100644 --- a/drivers/net/ti/Kconfig +++ b/drivers/net/ti/Kconfig @@ -14,7 +14,7 @@ config DRIVER_TI_EMAC bool "TI Davinci EMAC" depends on ARCH_DAVINCI || ARCH_OMAP2PLUS help - Support for davinci emac + Support for davinci emac config DRIVER_TI_EMAC_USE_RMII depends on DRIVER_TI_EMAC @@ -26,7 +26,7 @@ config DRIVER_TI_KEYSTONE_NET bool "TI Keystone 2 Ethernet" depends on ARCH_KEYSTONE help - This driver supports the TI Keystone 2 Ethernet subsystem + This driver supports the TI Keystone 2 Ethernet subsystem choice prompt "TI Keystone 2 Ethernet NETCP IP revision" diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 39df0e776df..9ffccc3a80b 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -101,11 +101,11 @@ config PCI_ENHANCED_ALLOCATION devices in place of traditional BARS for allocation of resources. config PCI_ARID - bool "Enable Alternate Routing-ID support for PCI" - help - Say Y here if you want to enable Alternate Routing-ID capability - support on PCI devices. This helps to skip some devices in BDF - scan that are not present. + bool "Enable Alternate Routing-ID support for PCI" + help + Say Y here if you want to enable Alternate Routing-ID capability + support on PCI devices. This helps to skip some devices in BDF + scan that are not present. config PCI_SCAN_SHOW bool "Show PCI devices during startup" @@ -287,7 +287,7 @@ config PCI_IOMMU_EXTRA_MAPPINGS the node describing the PCI controller. The intent is to cover SR-IOV scenarios which need mappings for VFs and PCI hot-plug scenarios. More documentation can be found under: - arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra + arch/arm/cpu/armv8/fsl-layerscape/doc/README.pci_iommu_extra config PCIE_LAYERSCAPE_EP bool "Layerscape PCIe Endpoint mode support" @@ -440,8 +440,8 @@ config PCIE_XILINX_NWL bool "Xilinx NWL PCIe controller" depends on ARCH_ZYNQMP help - Say 'Y' here if you want support for Xilinx / AMD NWL PCIe - controller as Root Port. + Say 'Y' here if you want support for Xilinx / AMD NWL PCIe + controller as Root Port. config PCIE_PLDA_COMMON bool diff --git a/drivers/pci/pci-rcar-gen2.c b/drivers/pci/pci-rcar-gen2.c index 08d5c4fbb8b..53cb0916741 100644 --- a/drivers/pci/pci-rcar-gen2.c +++ b/drivers/pci/pci-rcar-gen2.c @@ -10,6 +10,7 @@ #include <clk.h> #include <dm.h> #include <errno.h> +#include <fdtdec.h> #include <pci.h> #include <linux/bitops.h> @@ -235,9 +236,9 @@ static int rcar_gen2_pci_of_to_plat(struct udevice *dev) { struct rcar_gen2_pci_priv *priv = dev_get_priv(dev); - priv->cfg_base = devfdt_get_addr_index(dev, 0); - priv->mem_base = devfdt_get_addr_index(dev, 1); - if (!priv->cfg_base || !priv->mem_base) + priv->cfg_base = dev_read_addr_index(dev, 0); + priv->mem_base = dev_read_addr_index(dev, 1); + if (priv->cfg_base == FDT_ADDR_T_NONE || priv->mem_base == FDT_ADDR_T_NONE) return -EINVAL; return 0; diff --git a/drivers/pci/pci-rcar-gen3.c b/drivers/pci/pci-rcar-gen3.c index d4b4037ce19..1925d968c16 100644 --- a/drivers/pci/pci-rcar-gen3.c +++ b/drivers/pci/pci-rcar-gen3.c @@ -19,6 +19,7 @@ #include <clk.h> #include <dm.h> #include <errno.h> +#include <fdtdec.h> #include <pci.h> #include <wait_bit.h> #include <linux/bitops.h> @@ -391,8 +392,8 @@ static int rcar_gen3_pcie_of_to_plat(struct udevice *dev) { struct rcar_gen3_pcie_priv *priv = dev_get_plat(dev); - priv->regs = devfdt_get_addr_index(dev, 0); - if (!priv->regs) + priv->regs = dev_read_addr_index(dev, 0); + if (priv->regs == FDT_ADDR_T_NONE) return -EINVAL; return 0; diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c index c07feba7976..96550a9ff8f 100644 --- a/drivers/pci/pci_mpc85xx.c +++ b/drivers/pci/pci_mpc85xx.c @@ -170,13 +170,14 @@ static int mpc85xx_pci_dm_remove(struct udevice *dev) static int mpc85xx_pci_of_to_plat(struct udevice *dev) { struct mpc85xx_pci_priv *priv = dev_get_priv(dev); - fdt_addr_t addr; + void __iomem *addr; - addr = devfdt_get_addr_index(dev, 0); - if (addr == FDT_ADDR_T_NONE) + addr = dev_remap_addr_index(dev, 0); + if (!addr) return -EINVAL; - priv->cfg_addr = (void __iomem *)map_physmem(addr, 0, MAP_NOCACHE); - priv->cfg_data = (void __iomem *)((ulong)priv->cfg_addr + 4); + + priv->cfg_addr = addr; + priv->cfg_data = priv->cfg_addr + 4; return 0; } diff --git a/drivers/pci/pcie_dw_mvebu.c b/drivers/pci/pcie_dw_mvebu.c index 43b919175c9..5a177478afc 100644 --- a/drivers/pci/pcie_dw_mvebu.c +++ b/drivers/pci/pcie_dw_mvebu.c @@ -565,13 +565,12 @@ static int pcie_dw_mvebu_of_to_plat(struct udevice *dev) struct pcie_dw_mvebu *pcie = dev_get_priv(dev); /* Get the controller base address */ - pcie->ctrl_base = devfdt_get_addr_index_ptr(dev, 0); + pcie->ctrl_base = dev_read_addr_index_ptr(dev, 0); if (!pcie->ctrl_base) return -EINVAL; /* Get the config space base address and size */ - pcie->cfg_base = devfdt_get_addr_size_index_ptr(dev, 1, - &pcie->cfg_size); + pcie->cfg_base = dev_read_addr_size_index_ptr(dev, 1, &pcie->cfg_size); if (!pcie->cfg_base) return -EINVAL; diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index 8d853ecf2c2..c8b8e171e39 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -774,8 +774,8 @@ static int imx_pcie_of_to_plat(struct udevice *dev) { struct imx_pcie_priv *priv = dev_get_priv(dev); - priv->dbi_base = devfdt_get_addr_index_ptr(dev, 0); - priv->cfg_base = devfdt_get_addr_index_ptr(dev, 1); + priv->dbi_base = dev_read_addr_index_ptr(dev, 0); + priv->cfg_base = dev_read_addr_index_ptr(dev, 1); if (!priv->dbi_base || !priv->cfg_base) return -EINVAL; diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h index d5f4930e181..e6d47241e71 100644 --- a/drivers/pci/pcie_layerscape.h +++ b/drivers/pci/pcie_layerscape.h @@ -10,6 +10,7 @@ #include <fdtdec.h> #include <pci.h> +#include <linux/ioport.h> #include <linux/sizes.h> #include <linux/types.h> #include <asm/arch-fsl-layerscape/svr.h> @@ -164,7 +165,7 @@ struct ls_pcie_rc { }; struct ls_pcie_ep { - struct fdt_resource addr_res; + struct resource addr_res; struct ls_pcie *pcie; struct udevice *bus; void __iomem *addr; diff --git a/drivers/pci/pcie_layerscape_ep.c b/drivers/pci/pcie_layerscape_ep.c index 3520488b345..b7809857565 100644 --- a/drivers/pci/pcie_layerscape_ep.c +++ b/drivers/pci/pcie_layerscape_ep.c @@ -7,7 +7,6 @@ #include <config.h> #include <asm/arch/fsl_serdes.h> #include <dm.h> -#include <asm/global_data.h> #include <dm/devres.h> #include <errno.h> #include <pci_ep.h> @@ -16,8 +15,6 @@ #include <linux/log2.h> #include "pcie_layerscape.h" -DECLARE_GLOBAL_DATA_PTR; - static void ls_pcie_ep_enable_cfg(struct ls_pcie_ep *pcie_ep) { struct ls_pcie *pcie = pcie_ep->pcie; @@ -250,17 +247,15 @@ static int ls_pcie_ep_probe(struct udevice *dev) pcie_ep->pcie = pcie; - pcie->dbi = devfdt_get_addr_index_ptr(dev, 0); + pcie->dbi = dev_read_addr_index_ptr(dev, 0); if (!pcie->dbi) return -EINVAL; - pcie->ctrl = devfdt_get_addr_index_ptr(dev, 1); + pcie->ctrl = dev_read_addr_index_ptr(dev, 1); if (!pcie->ctrl) return -EINVAL; - ret = fdt_get_named_resource(gd->fdt_blob, dev_of_offset(dev), - "reg", "reg-names", - "addr_space", &pcie_ep->addr_res); + ret = dev_read_resource_byname(dev, "addr_space", &pcie_ep->addr_res); if (ret) { printf("%s: resource \"addr_space\" not found\n", dev->name); return ret; @@ -273,8 +268,7 @@ static int ls_pcie_ep_probe(struct udevice *dev) if (!is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx))) return 0; - pcie->big_endian = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), - "big-endian"); + pcie->big_endian = dev_read_bool(dev, "big-endian"); svr = SVR_SOC_VER(get_svr()); @@ -294,13 +288,9 @@ static int ls_pcie_ep_probe(struct udevice *dev) if (pcie->mode != PCI_HEADER_TYPE_NORMAL) return 0; - pcie_ep->max_functions = fdtdec_get_int(gd->fdt_blob, - dev_of_offset(dev), - "max-functions", 1); - pcie_ep->num_ib_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "num-ib-windows", 8); - pcie_ep->num_ob_wins = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), - "num-ob-windows", 8); + pcie_ep->max_functions = dev_read_s32_default(dev, "max-functions", 1); + pcie_ep->num_ib_wins = dev_read_s32_default(dev, "num-ib-windows", 8); + pcie_ep->num_ob_wins = dev_read_s32_default(dev, "num-ob-windows", 8); printf("PCIe%u: %s %s", PCIE_SRDS_PRTCL(pcie->idx), dev->name, "Endpoint"); diff --git a/drivers/pci_endpoint/Kconfig b/drivers/pci_endpoint/Kconfig index 9900481daa6..d1db4951a0c 100644 --- a/drivers/pci_endpoint/Kconfig +++ b/drivers/pci_endpoint/Kconfig @@ -9,10 +9,10 @@ config PCI_ENDPOINT bool "PCI Endpoint Support" depends on DM help - Enable this configuration option to support configurable PCI - endpoints. This should be enabled if the platform has a PCI - controllers that can operate in endpoint mode (as a device - connected to PCI host or bridge). + Enable this configuration option to support configurable PCI + endpoints. This should be enabled if the platform has a PCI + controllers that can operate in endpoint mode (as a device + connected to PCI host or bridge). config PCIE_CADENCE_EP bool "Cadence PCIe endpoint controller" diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index eafa82fe494..89d84df96ae 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -72,14 +72,14 @@ config AB8500_USB_PHY Support for the USB OTG PHY in ST-Ericsson AB8500. config APPLE_ATCPHY - bool "Apple Type-C PHY Driver" - depends on PHY && ARCH_APPLE - default y - help - Support for the Apple Type-C PHY. + bool "Apple Type-C PHY Driver" + depends on PHY && ARCH_APPLE + default y + help + Support for the Apple Type-C PHY. - This is a dummy driver since the PHY is initialized - sufficiently by previous stage firmware. + This is a dummy driver since the PHY is initialized + sufficiently by previous stage firmware. config BCM6318_USBH_PHY bool "BCM6318 USBH PHY support" @@ -249,14 +249,14 @@ config MT7620_USB_PHY depends on PHY depends on SOC_MT7620 help - Support the intergated USB PHY in MediaTek MT7620 SoC + Support the intergated USB PHY in MediaTek MT7620 SoC config MT76X8_USB_PHY bool "MediaTek MT76x8 (7628/88) USB PHY support" depends on PHY depends on SOC_MT7628 help - Support the USB PHY in MT76x8 SoCs + Support the USB PHY in MT76x8 SoCs This PHY is found on MT76x8 devices supporting USB. diff --git a/drivers/phy/qcom/Kconfig b/drivers/phy/qcom/Kconfig index 7094903d869..1fdadaccb12 100644 --- a/drivers/phy/qcom/Kconfig +++ b/drivers/phy/qcom/Kconfig @@ -2,7 +2,7 @@ config MSM8916_USB_PHY bool select PHY help - Support the Qualcomm MSM8916 USB PHY + Support the Qualcomm MSM8916 USB PHY This PHY is found on qualcomm dragonboard410c development board. diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 578edbf8168..46a95a1ab6b 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -405,6 +405,7 @@ config SPL_PINCTRL_ZYNQMP endif +source "drivers/pinctrl/airoha/Kconfig" source "drivers/pinctrl/broadcom/Kconfig" source "drivers/pinctrl/exynos/Kconfig" source "drivers/pinctrl/intel/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 29fb9b484d0..6c6e8b59122 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -3,39 +3,42 @@ obj-y += pinctrl-uclass.o obj-$(CONFIG_$(PHASE_)PINCTRL_GENERIC) += pinctrl-generic.o +obj-y += broadcom/ +obj-y += nxp/ + +obj-$(CONFIG_ARCH_ASPEED) += aspeed/ +obj-$(CONFIG_ARCH_ATH79) += ath79/ +obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ +obj-$(CONFIG_ARCH_MVEBU) += mvebu/ +obj-$(CONFIG_ARCH_NEXELL) += nexell/ +obj-$(CONFIG_ARCH_NPCM) += nuvoton/ +obj-$(CONFIG_ARCH_RENESAS) += renesas/ + obj-$(CONFIG_PINCTRL_ADI) += pinctrl-adi-adsp.o +obj-$(CONFIG_PINCTRL_AIROHA) += airoha/ obj-$(CONFIG_PINCTRL_APPLE) += pinctrl-apple.o obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o obj-$(CONFIG_PINCTRL_AT91PIO4) += pinctrl-at91-pio4.o -obj-y += nxp/ +obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ +obj-$(CONFIG_PINCTRL_INTEL) += intel/ +obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o +obj-$(CONFIG_PINCTRL_MESON) += meson/ +obj-$(CONFIG_PINCTRL_MSCC) += mscc/ +obj-$(CONFIG_PINCTRL_MTK) += mediatek/ +obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o +obj-$(CONFIG_PINCTRL_QCOM) += qcom/ +obj-$(CONFIG_PINCTRL_QE) += pinctrl-qe-io.o obj-$(CONFIG_$(PHASE_)PINCTRL_ROCKCHIP) += rockchip/ -obj-$(CONFIG_ARCH_ASPEED) += aspeed/ -obj-$(CONFIG_ARCH_ATH79) += ath79/ -obj-$(CONFIG_PINCTRL_INTEL) += intel/ -obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ -obj-$(CONFIG_ARCH_NPCM) += nuvoton/ -obj-$(CONFIG_PINCTRL_QCOM) += qcom/ -obj-$(CONFIG_ARCH_RENESAS) += renesas/ -obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o -obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ -obj-$(CONFIG_$(PHASE_)PINCTRL_TEGRA) += tegra/ -obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ -obj-$(CONFIG_PINCTRL_PIC32) += pinctrl_pic32.o -obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/ -obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o -obj-$(CONFIG_PINCTRL_MESON) += meson/ -obj-$(CONFIG_PINCTRL_MTK) += mediatek/ -obj-$(CONFIG_PINCTRL_MSCC) += mscc/ -obj-$(CONFIG_ARCH_MVEBU) += mvebu/ -obj-$(CONFIG_ARCH_NEXELL) += nexell/ -obj-$(CONFIG_PINCTRL_QE) += pinctrl-qe-io.o -obj-$(CONFIG_PINCTRL_SCMI) += pinctrl-scmi.o -obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o -obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o -obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o -obj-$(CONFIG_$(PHASE_)PINCTRL_SX150X) += pinctrl-sx150x.o +obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o +obj-$(CONFIG_PINCTRL_SCMI) += pinctrl-scmi.o +obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o +obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/ +obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o +obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o obj-$(CONFIG_$(PHASE_)PINCTRL_STMFX) += pinctrl-stmfx.o -obj-$(CONFIG_PINCTRL_TH1520) += pinctrl-th1520.o -obj-y += broadcom/ +obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ +obj-$(CONFIG_$(PHASE_)PINCTRL_SX150X) += pinctrl-sx150x.o +obj-$(CONFIG_$(PHASE_)PINCTRL_TEGRA) += tegra/ +obj-$(CONFIG_PINCTRL_TH1520) += pinctrl-th1520.o +obj-$(CONFIG_PINCTRL_UNIPHIER) += uniphier/ obj-$(CONFIG_$(PHASE_)PINCTRL_ZYNQMP) += pinctrl-zynqmp.o -obj-$(CONFIG_PINCTRL_STARFIVE) += starfive/ diff --git a/drivers/pinctrl/airoha/Kconfig b/drivers/pinctrl/airoha/Kconfig new file mode 100644 index 00000000000..f5d948b27eb --- /dev/null +++ b/drivers/pinctrl/airoha/Kconfig @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config PINCTRL_AIROHA + depends on ARCH_AIROHA + select PINCTRL_FULL + select PINCTRL_GENERIC + select PINMUX + select PINCONF + select REGMAP + select SYSCON + bool + +config PINCTRL_AIROHA_EN7523 + bool "Airoha EN7523 pin controller and gpio driver" + depends on TARGET_EN7523 + select PINCTRL_AIROHA + +config PINCTRL_AIROHA_AN7581 + bool "Airoha AN7581 pin controller and gpio driver" + depends on TARGET_AN7581 + select PINCTRL_AIROHA + +config PINCTRL_AIROHA_AN7583 + bool "Airoha AN7583 pin controller and gpio driver" + depends on TARGET_AN7583 + select PINCTRL_AIROHA diff --git a/drivers/pinctrl/airoha/Makefile b/drivers/pinctrl/airoha/Makefile new file mode 100644 index 00000000000..b90bd180591 --- /dev/null +++ b/drivers/pinctrl/airoha/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_PINCTRL_AIROHA) += pinctrl-airoha.o + +obj-$(CONFIG_PINCTRL_AIROHA_EN7523) += pinctrl-en7523.o +obj-$(CONFIG_PINCTRL_AIROHA_AN7581) += pinctrl-an7581.o +obj-$(CONFIG_PINCTRL_AIROHA_AN7583) += pinctrl-an7583.o diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h new file mode 100644 index 00000000000..4354b0eb6b4 --- /dev/null +++ b/drivers/pinctrl/airoha/airoha-common.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef __AIROHA_COMMON_HEADER__ +#define __AIROHA_COMMON_HEADER__ + +#include <linux/types.h> +#include <linux/bitops.h> +#include <linux/bitfield.h> +#include <linux/pinctrl/pinctrl.h> + +#include <dm/device.h> +#include <dm/pinctrl.h> + +/* GPIOs */ +#define REG_GPIO_CTRL 0x0000 +#define REG_GPIO_DATA 0x0004 +#define REG_GPIO_INT 0x0008 +#define REG_GPIO_INT_EDGE 0x000c +#define REG_GPIO_INT_LEVEL 0x0010 +#define REG_GPIO_OE 0x0014 +#define REG_GPIO_CTRL1 0x0020 +#define REG_GPIO_CTRL2 0x0060 +#define REG_GPIO_CTRL3 0x0064 +#define REG_GPIO_DATA1 0x0070 +#define REG_GPIO_OE1 0x0078 +#define REG_GPIO_INT1 0x007c +#define REG_GPIO_INT_EDGE1 0x0080 +#define REG_GPIO_INT_EDGE2 0x0084 +#define REG_GPIO_INT_EDGE3 0x0088 +#define REG_GPIO_INT_LEVEL1 0x008c +#define REG_GPIO_INT_LEVEL2 0x0090 +#define REG_GPIO_INT_LEVEL3 0x0094 + +#define AIROHA_NUM_PINS 64 +#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) +#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) + +#define PINCTRL_PIN_GROUP(id, table) \ + PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins)) + +#define PINCTRL_FUNC_DESC(id, table) \ + { \ + .desc = PINCTRL_PINFUNCTION(id, table##_groups, \ + ARRAY_SIZE(table##_groups)),\ + .groups = table##_func_group, \ + .group_size = ARRAY_SIZE(table##_func_group), \ + } + +#define PINCTRL_CONF_DESC(p, offset, mask) \ + { \ + .pin = p, \ + .reg = { offset, mask }, \ + } + +struct airoha_pinctrl_reg { + u32 offset; + u32 mask; +}; + +enum airoha_pinctrl_mux_func { + AIROHA_FUNC_MUX, + AIROHA_FUNC_PWM_MUX, + AIROHA_FUNC_PWM_EXT_MUX, +}; + +struct airoha_pinctrl_func_group { + const char *name; + struct { + enum airoha_pinctrl_mux_func mux; + u32 offset; + u32 mask; + u32 val; + } regmap[2]; + int regmap_size; +}; + +struct airoha_pinctrl_func { + const struct pinfunction desc; + const struct airoha_pinctrl_func_group *groups; + u8 group_size; +}; + +struct airoha_pinctrl_conf { + u32 pin; + struct airoha_pinctrl_reg reg; +}; + +struct airoha_pinctrl_gpiochip { + /* gpio */ + const u32 *data; + const u32 *dir; + const u32 *out; + /* irq */ + const u32 *status; + const u32 *level; + const u32 *edge; + + u32 irq_type[AIROHA_NUM_PINS]; +}; + +struct airoha_pinctrl_confs_info { + const struct airoha_pinctrl_conf *confs; + unsigned int num_confs; +}; + +enum airoha_pinctrl_confs_type { + AIROHA_PINCTRL_CONFS_PULLUP, + AIROHA_PINCTRL_CONFS_PULLDOWN, + AIROHA_PINCTRL_CONFS_DRIVE_E2, + AIROHA_PINCTRL_CONFS_DRIVE_E4, + AIROHA_PINCTRL_CONFS_PCIE_RST_OD, + + AIROHA_PINCTRL_CONFS_MAX +}; + +struct airoha_pinctrl { + struct udevice *dev; + + struct regmap *chip_scu; + struct regmap *regmap; + + struct airoha_pinctrl_match_data *data; + + struct airoha_pinctrl_gpiochip gpiochip; +}; + +struct airoha_pinctrl_match_data { + const int gpio_offs; + const int gpio_pin_cnt; + const char *chip_scu_compatible; + const struct pinctrl_pin_desc *pins; + const unsigned int num_pins; + const struct pingroup *grps; + const unsigned int num_grps; + const struct airoha_pinctrl_func *funcs; + const unsigned int num_funcs; + const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX]; +}; + +extern const struct pinctrl_ops airoha_pinctrl_ops; + +int airoha_pinctrl_probe(struct udevice *dev); +int airoha_pinctrl_bind(struct udevice *dev); + +#endif diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c new file mode 100644 index 00000000000..60c48c0960c --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-airoha.c @@ -0,0 +1,958 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi <[email protected]> + * Author: Benjamin Larsson <[email protected]> + * Author: Markus Gothe <[email protected]> + * Author: Mikhail Kshevetskiy <[email protected]> + */ +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/ofnode.h> +#include <asm-generic/gpio.h> +#include <asm/arch/scu-regmap.h> +#include <dt-bindings/pinctrl/mt65xx.h> +#include <regmap.h> +#include <syscon.h> + +#include "airoha-common.h" + +#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ + (pin), (val)) +#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ + (pin), (val)) +#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ + (pin), (val)) +#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ + (pin), (val)) +#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \ + airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ + (pin), (val)) +#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ + (pin), (val)) +#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ + (pin), (val)) +#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ + (pin), (val)) +#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ + (pin), (val)) +#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \ + airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ + (pin), (val)) + +static const u32 gpio_data_regs[] = { + REG_GPIO_DATA, + REG_GPIO_DATA1 +}; + +static const u32 gpio_out_regs[] = { + REG_GPIO_OE, + REG_GPIO_OE1 +}; + +static const u32 gpio_dir_regs[] = { + REG_GPIO_CTRL, + REG_GPIO_CTRL1, + REG_GPIO_CTRL2, + REG_GPIO_CTRL3 +}; + +static const u32 irq_status_regs[] = { + REG_GPIO_INT, + REG_GPIO_INT1 +}; + +static const u32 irq_level_regs[] = { + REG_GPIO_INT_LEVEL, + REG_GPIO_INT_LEVEL1, + REG_GPIO_INT_LEVEL2, + REG_GPIO_INT_LEVEL3 +}; + +static const u32 irq_edge_regs[] = { + REG_GPIO_INT_EDGE, + REG_GPIO_INT_EDGE1, + REG_GPIO_INT_EDGE2, + REG_GPIO_INT_EDGE3 +}; + +static int pin_in_group(unsigned int pin, const struct pingroup *grp) +{ + for (int i = 0; i < grp->npins; i++) { + if (grp->pins[i] == pin) + return 1; + } + + return 0; +} + +static int pin_to_gpio(struct airoha_pinctrl *pinctrl, unsigned int pin) +{ + struct airoha_pinctrl_match_data *data = pinctrl->data; + + if (pin < data->gpio_offs || + pin >= data->gpio_offs + data->gpio_pin_cnt) + return -EINVAL; + + return pin - data->gpio_offs; +} + +/* gpio callbacks */ +static int airoha_gpio_set(struct airoha_pinctrl *pinctrl, unsigned int gpio, + int value) +{ + u32 offset = gpio % AIROHA_PIN_BANK_SIZE; + u8 index = gpio / AIROHA_PIN_BANK_SIZE; + + return regmap_update_bits(pinctrl->regmap, + pinctrl->gpiochip.data[index], + BIT(offset), value ? BIT(offset) : 0); +} + +static int airoha_gpio_get(struct airoha_pinctrl *pinctrl, unsigned int gpio) +{ + u32 val, pin = gpio % AIROHA_PIN_BANK_SIZE; + u8 index = gpio / AIROHA_PIN_BANK_SIZE; + int err; + + err = regmap_read(pinctrl->regmap, + pinctrl->gpiochip.data[index], &val); + + return err ? err : !!(val & BIT(pin)); +} + +static int airoha_gpio_get_direction(struct airoha_pinctrl *pinctrl, unsigned int gpio) +{ + u32 mask, index, val; + int err, field_shift; + + field_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN); + mask = GENMASK(field_shift + 1, field_shift); + index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN; + + err = regmap_read(pinctrl->regmap, + pinctrl->gpiochip.dir[index], &val); + if (err) + return err; + + if ((val & mask) > BIT(field_shift)) + return -EINVAL; + + return (val & mask) ? GPIOF_OUTPUT : GPIOF_INPUT; +} + +static int airoha_gpio_set_direction(struct airoha_pinctrl *pinctrl, + unsigned int gpio, bool input) +{ + u32 mask, index; + int err, field_shift; + + /* set output enable */ + mask = BIT(gpio % AIROHA_PIN_BANK_SIZE); + index = gpio / AIROHA_PIN_BANK_SIZE; + err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index], + mask, !input ? mask : 0); + if (err) + return err; + + /* set direction */ + field_shift = 2 * (gpio % AIROHA_REG_GPIOCTRL_NUM_PIN); + mask = GENMASK(field_shift + 1, field_shift); + index = gpio / AIROHA_REG_GPIOCTRL_NUM_PIN; + + return regmap_update_bits(pinctrl->regmap, + pinctrl->gpiochip.dir[index], + mask, !input ? BIT(field_shift) : 0); +} + +/* pinmux callbacks */ +static int airoha_pinmux_set_mux(struct airoha_pinctrl *pinctrl, + unsigned int func_selector, + unsigned int group_selector) +{ + const struct airoha_pinctrl_func *func; + const struct pingroup *grp; + int i; + + func = &pinctrl->data->funcs[func_selector]; + grp = &pinctrl->data->grps[group_selector]; + + dev_dbg(pinctrl->dev, "enable function %s group %s\n", + func->desc.name, grp->name); + + for (i = 0; i < func->group_size; i++) { + const struct airoha_pinctrl_func_group *group; + int j; + + group = &func->groups[i]; + if (strcmp(group->name, grp->name)) + continue; + + for (j = 0; j < group->regmap_size; j++) { + switch (group->regmap[j].mux) { + case AIROHA_FUNC_PWM_EXT_MUX: + case AIROHA_FUNC_PWM_MUX: + regmap_update_bits(pinctrl->regmap, + group->regmap[j].offset, + group->regmap[j].mask, + group->regmap[j].val); + break; + default: + regmap_update_bits(pinctrl->chip_scu, + group->regmap[j].offset, + group->regmap[j].mask, + group->regmap[j].val); + break; + } + } + return 0; + } + + return -EINVAL; +} + +static int airoha_pinmux_set_direction(struct airoha_pinctrl *pinctrl, + unsigned int p, bool input) +{ + int gpio; + + gpio = pin_to_gpio(pinctrl, p); + if (gpio < 0) + return gpio; + + return airoha_gpio_set_direction(pinctrl, gpio, input); +} + +/* pinconf callbacks */ +static const struct airoha_pinctrl_reg * +airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf, + int conf_size, int pin) +{ + int i; + + for (i = 0; i < conf_size; i++) { + if (conf[i].pin == pin) + return &conf[i].reg; + } + + return NULL; +} + +static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl, + enum airoha_pinctrl_confs_type conf_type, + int pin, u32 *val) +{ + const struct airoha_pinctrl_confs_info *confs_info; + const struct airoha_pinctrl_reg *reg; + + confs_info = &pinctrl->data->confs_info[conf_type]; + + reg = airoha_pinctrl_get_conf_reg(confs_info->confs, + confs_info->num_confs, + pin); + if (!reg) + return -EINVAL; + + if (regmap_read(pinctrl->chip_scu, reg->offset, val)) + return -EINVAL; + + *val = field_get(reg->mask, *val); + + return 0; +} + +static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl, + enum airoha_pinctrl_confs_type conf_type, + int pin, u32 val) +{ + const struct airoha_pinctrl_confs_info *confs_info; + const struct airoha_pinctrl_reg *reg = NULL; + + confs_info = &pinctrl->data->confs_info[conf_type]; + + reg = airoha_pinctrl_get_conf_reg(confs_info->confs, + confs_info->num_confs, + pin); + if (!reg) + return -EINVAL; + + if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask, + field_prep(reg->mask, val))) + return -EINVAL; + + return 0; +} + +static int airoha_pinconf_get_direction(struct airoha_pinctrl *pinctrl, u32 p) +{ + int gpio; + + gpio = pin_to_gpio(pinctrl, p); + if (gpio < 0) + return gpio; + + return airoha_gpio_get_direction(pinctrl, gpio); +} + +static int airoha_pinconf_get(struct airoha_pinctrl *pinctrl, + unsigned int pin, unsigned long *config) +{ + enum pin_config_param param = pinconf_to_config_param(*config); + u32 arg; + + switch (param) { + case PIN_CONFIG_BIAS_PULL_DOWN: + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: { + u32 pull_up, pull_down; + + if (airoha_pinctrl_get_pullup_conf(pinctrl, pin, &pull_up) || + airoha_pinctrl_get_pulldown_conf(pinctrl, pin, &pull_down)) + return -EINVAL; + + if (param == PIN_CONFIG_BIAS_PULL_UP && + !(pull_up && !pull_down)) + return -EINVAL; + else if (param == PIN_CONFIG_BIAS_PULL_DOWN && + !(pull_down && !pull_up)) + return -EINVAL; + else if (pull_up || pull_down) + return -EINVAL; + + arg = 1; + break; + } + case PIN_CONFIG_DRIVE_STRENGTH: { + u32 e2, e4; + + if (airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, &e2) || + airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, &e4)) + return -EINVAL; + + arg = e4 << 1 | e2; + break; + } + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + if (airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, &arg)) + return -EINVAL; + break; + case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_INPUT_ENABLE: + arg = airoha_pinconf_get_direction(pinctrl, pin); + if ((param != PIN_CONFIG_OUTPUT_ENABLE || arg != GPIOF_OUTPUT) && + (param != PIN_CONFIG_INPUT_ENABLE || arg != GPIOF_INPUT)) + return -EINVAL; + + arg = 1; + break; + default: + return -EOPNOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + + return 0; +} + +static int airoha_pinconf_set_pin_value(struct airoha_pinctrl *pinctrl, + unsigned int p, bool value) +{ + int gpio; + + gpio = pin_to_gpio(pinctrl, p); + if (gpio < 0) + return gpio; + + return airoha_gpio_set(pinctrl, gpio, value); +} + +static int airoha_pinconf_set(struct airoha_pinctrl *pinctrl, + unsigned int pin, unsigned long *configs, + unsigned int num_configs) +{ + int i, err; + + for (i = 0; i < num_configs; i++) { + u32 param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); + if (err) + return err; + + err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); + if (err) + return err; + + break; + + case PIN_CONFIG_BIAS_PULL_UP: + err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); + if (err) + return err; + + err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 1); + if (err) + return err; + + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + err = airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1); + if (err) + return err; + + err = airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); + if (err) + return err; + + break; + + case PIN_CONFIG_DRIVE_STRENGTH: { + u32 e2 = 0, e4 = 0; + + switch (arg) { + case MTK_DRIVE_2mA: + break; + case MTK_DRIVE_4mA: + e2 = 1; + break; + case MTK_DRIVE_6mA: + e4 = 1; + break; + case MTK_DRIVE_8mA: + e2 = 1; + e4 = 1; + break; + default: + return -EINVAL; + } + + err = airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, e2); + if (err) + return err; + + err = airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, e4); + if (err) + return err; + + break; + } + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + err = airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, !!arg); + if (err) + return err; + + break; + + case PIN_CONFIG_OUTPUT_ENABLE: + case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT: { + bool input = param == PIN_CONFIG_INPUT_ENABLE; + + err = airoha_pinmux_set_direction(pinctrl, pin, input); + if (err) + return err; + + if (param == PIN_CONFIG_OUTPUT) { + err = airoha_pinconf_set_pin_value(pinctrl, + pin, !!arg); + if (err) + return err; + } + + break; + } + default: + return -EOPNOTSUPP; + } + } + + return 0; +} + +static int airoha_pinconf_group_set(struct airoha_pinctrl *pinctrl, + unsigned int group, unsigned long *configs, + unsigned int num_configs) +{ + int i; + + for (i = 0; i < pinctrl->data->grps[group].npins; i++) { + int err; + + err = airoha_pinconf_set(pinctrl, + pinctrl->data->grps[group].pins[i], + configs, num_configs); + if (err) + return err; + } + + return 0; +} + +static int func_grp_active(struct airoha_pinctrl *pinctrl, + const struct airoha_pinctrl_func *func, + const char *grp_name) +{ + const struct airoha_pinctrl_func_group *func_grp; + u32 val, match; + int ret; + + for (int i = 0; i < func->group_size; i++) { + if (strcmp(func->groups[i].name, grp_name)) + continue; + + match = 0; + func_grp = &func->groups[i]; + for (int j = 0; j < func_grp->regmap_size; j++) { + switch (func_grp->regmap[j].mux) { + case AIROHA_FUNC_PWM_EXT_MUX: + case AIROHA_FUNC_PWM_MUX: + ret = regmap_read(pinctrl->regmap, + func_grp->regmap[j].offset, + &val); + break; + default: + ret = regmap_read(pinctrl->chip_scu, + func_grp->regmap[j].offset, + &val); + break; + } + + if (ret) + break; + + if ((val & func_grp->regmap[j].mask) != + func_grp->regmap[j].val) + break; + + match++; + } + + return match == func->groups[i].regmap_size; + } + + return 0; +} + +/*********************** + * gpio driver interface + ***********************/ +static int airoha_pinctrl_gpio_set(struct udevice *dev, unsigned int gpio, + int value) +{ + return airoha_gpio_set(dev_get_priv(dev->parent), gpio, value); +} + +static int airoha_pinctrl_gpio_get(struct udevice *dev, unsigned int gpio) +{ + return airoha_gpio_get(dev_get_priv(dev->parent), gpio); +} + +static int airoha_pinctrl_gpio_get_direction(struct udevice *dev, + unsigned int gpio) +{ + return airoha_gpio_get_direction(dev_get_priv(dev->parent), gpio); +} + +static int airoha_pinctrl_gpio_direction_input(struct udevice *dev, + unsigned int gpio) +{ + return airoha_gpio_set_direction(dev_get_priv(dev->parent), + gpio, true); +} + +static int airoha_pinctrl_gpio_direction_output(struct udevice *dev, + unsigned int gpio, int val) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev->parent); + int err; + + err = airoha_gpio_set_direction(pinctrl, gpio, false); + if (err) + return err; + + return airoha_gpio_set(pinctrl, gpio, val); +} + +static int airoha_pinctrl_gpio_probe(struct udevice *dev) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev->parent); + struct gpio_dev_priv *uc_priv; + + uc_priv = dev_get_uclass_priv(dev); + uc_priv->bank_name = "airoha"; + uc_priv->gpio_count = pinctrl->data->gpio_pin_cnt; + + return 0; +} + +static int airoha_pinctrl_gpio_bind(struct udevice *dev) +{ + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); + + return 0; +} + +static const struct dm_gpio_ops airoha_pinctrl_gpio_ops = { + .set_value = airoha_pinctrl_gpio_set, + .get_value = airoha_pinctrl_gpio_get, + .get_function = airoha_pinctrl_gpio_get_direction, + .direction_input = airoha_pinctrl_gpio_direction_input, + .direction_output = airoha_pinctrl_gpio_direction_output, +}; + +static struct driver airoha_pinctrl_gpio_driver = { + .name = "airoha_pinctrl_gpio", + .id = UCLASS_GPIO, + .probe = airoha_pinctrl_gpio_probe, + .bind = airoha_pinctrl_gpio_bind, + .ops = &airoha_pinctrl_gpio_ops, +}; + +static int airoha_pinctrl_gpio_register(struct udevice *parent) +{ + struct uclass_driver *drv; + ofnode node; + int ret; + + drv = lists_uclass_lookup(UCLASS_GPIO); + if (!drv) + return -ENOENT; + + /* + * Support upstream linux DTSI that define gpio-controller + * in the root node (instead of a dedicated subnode) + */ + if (dev_read_bool(parent, "gpio-controller")) { + /* upstream DTSI, use current node */ + node = dev_ofnode(parent); + } else { + /* legacy DTSI, search for gpio-controller subnode */ + ret = -ENOENT; + dev_for_each_subnode(node, parent) + if (ofnode_read_bool(node, "gpio-controller")) { + ret = 0; + break; + } + + if (ret) + return ret; + } + + return device_bind_with_driver_data(parent, + &airoha_pinctrl_gpio_driver, + "airoha_pinctrl_gpio", + 0, node, NULL); +} + +/************************** + * pinctrl driver interface + **************************/ +static int airoha_get_pins_count(struct udevice *dev) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + + return pinctrl->data->num_pins; +} + +static const char *airoha_get_pin_name(struct udevice *dev, + unsigned int selector) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + + return pinctrl->data->pins[selector].name; +} + +static int airoha_get_groups_count(struct udevice *dev) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + + return pinctrl->data->num_grps; +} + +static const char *airoha_get_group_name(struct udevice *dev, + unsigned int selector) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + + return pinctrl->data->grps[selector].name; +} + +static int airoha_get_funcs_count(struct udevice *dev) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + + return pinctrl->data->num_funcs; +} + +static const char *airoha_get_func_name(struct udevice *dev, + unsigned int selector) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + + return pinctrl->data->funcs[selector].desc.name; +} + +static int airoha_pinmux_group_set(struct udevice *dev, + unsigned int group_selector, + unsigned int func_selector) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + + dev_dbg(dev, "enabling %s function for pin group %s\n", + airoha_get_func_name(dev, func_selector), + airoha_get_group_name(dev, group_selector)); + + return airoha_pinmux_set_mux(pinctrl, func_selector, group_selector); +} + +static int airoha_pinmux_set(struct udevice *dev, + unsigned int pin_selector, + unsigned int func_selector) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + const struct airoha_pinctrl_match_data *data = pinctrl->data; + const char *pin_name; + unsigned int selector; + + pin_name = data->pins[pin_selector].name; + + /* find group matching the pin_name */ + for (selector = 0; selector < data->num_grps; selector++) { + if (!strcmp(pin_name, data->grps[selector].name)) + return airoha_pinmux_group_set(dev, selector, + func_selector); + } + + return -ENOENT; +} + +static const struct pinconf_param airoha_pinconf_params[] = { + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, + { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, + { "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 }, + { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, +}; + +static const char *airoha_pinconf_param_name(unsigned int param) +{ + for (int i = 0; i < ARRAY_SIZE(airoha_pinconf_params); i++) { + if (airoha_pinconf_params[i].param == param) + return airoha_pinconf_params[i].property; + } + + return NULL; +} + +static int airoha_pinconf_set_handler(struct udevice *dev, + unsigned pin_selector, + unsigned int param, + unsigned int argument) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + unsigned long configs[1] = { pinconf_to_config_packed(param, argument) }; + unsigned int pin = pinctrl->data->pins[pin_selector].number; + + dev_dbg(dev, "enabling %s=%d property for pin %s\n", + airoha_pinconf_param_name(param), argument, + airoha_get_pin_name(dev, pin_selector)); + + return airoha_pinconf_set(pinctrl, pin, configs, + ARRAY_SIZE(configs)); +} + +static int airoha_pinconf_group_set_handler(struct udevice *dev, + unsigned int group_selector, + unsigned int param, + unsigned int argument) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + unsigned long configs[1] = { pinconf_to_config_packed(param, argument) }; + + dev_dbg(dev, "enabling %s=%d property for pin group %s\n", + airoha_pinconf_param_name(param), argument, + airoha_get_group_name(dev, group_selector)); + + return airoha_pinconf_group_set(pinctrl, group_selector, + configs, ARRAY_SIZE(configs)); +} + +static int airoha_get_pin_muxing(struct udevice *dev, unsigned int selector, + char *buf, int size) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + struct airoha_pinctrl_match_data *data = pinctrl->data; + const char *name, *type; + int ret, gpio, found = 0; + unsigned long config; + unsigned int param, pin; + u32 val; + + pin = data->pins[selector].number; + for (int i = 0; i < data->num_grps; i++) { + if (!pin_in_group(pin, &data->grps[i])) + continue; + + name = data->grps[i].name; + for (int j = 0; j < data->num_funcs; j++) { + if (!func_grp_active(pinctrl, &data->funcs[j], name)) + continue; + + ret = scnprintf(buf, size, "%s(%s)", + data->funcs[j].desc.name, name); + if (ret < 0) + return -ENOSPC; + + found = 1; + buf += ret; + size -= ret; + break; + } + + if (found) + break; + } + + if (!found) { + gpio = pin_to_gpio(pinctrl, pin); + if (gpio < 0) { + /* + * WARNING: non-gpio pin with unknown function. + * + * This should not have happened, the function group + * tables are incomplete. Please fix ASAP. + */ + ret = scnprintf(buf, size, "default"); + } else { + /* assume gpio */ + val = airoha_gpio_get(pinctrl, gpio); + switch (airoha_gpio_get_direction(pinctrl, gpio)) { + case GPIOF_INPUT: + type = "input"; + break; + case GPIOF_OUTPUT: + type = "output"; + break; + default: + type = "unknown"; + break; + }; + ret = scnprintf(buf, size, "gpio%d, %s(%d)", + gpio, type, val); + } + + if (ret < 0) + return -ENOSPC; + + buf += ret; + size -= ret; + } + + for (int i = 0; i < ARRAY_SIZE(airoha_pinconf_params); i++) { + param = airoha_pinconf_params[i].param; + config = pinconf_to_config_packed(param, 0); + ret = airoha_pinconf_get(pinctrl, pin, &config); + if (ret < 0) + continue; + + name = airoha_pinconf_params[i].property; + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + case PIN_CONFIG_BIAS_PULL_UP: + case PIN_CONFIG_BIAS_PULL_DOWN: + ret = scnprintf(buf, size, ", %s", name); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + case PIN_CONFIG_DRIVE_OPEN_DRAIN: + val = pinconf_to_config_argument(config); + ret = scnprintf(buf, size, ", %s(%d)", name, val); + break; + + default: + break; + } + + if (ret < 0) + return -ENOSPC; + + buf += ret; + size -= ret; + } + + return 0; +} + +const struct pinctrl_ops airoha_pinctrl_ops = { + .get_pins_count = airoha_get_pins_count, + .get_pin_name = airoha_get_pin_name, + .get_groups_count = airoha_get_groups_count, + .get_group_name = airoha_get_group_name, + .get_functions_count = airoha_get_funcs_count, + .get_function_name = airoha_get_func_name, + .pinmux_set = airoha_pinmux_set, + .pinmux_group_set = airoha_pinmux_group_set, + + .pinconf_num_params = ARRAY_SIZE(airoha_pinconf_params), + .pinconf_params = airoha_pinconf_params, + .pinconf_set = airoha_pinconf_set_handler, + .pinconf_group_set = airoha_pinconf_group_set_handler, + + .set_state = pinctrl_generic_set_state, + .get_pin_muxing = airoha_get_pin_muxing, +}; + +int airoha_pinctrl_probe(struct udevice *dev) +{ + struct airoha_pinctrl *pinctrl = dev_get_priv(dev); + + pinctrl->dev = dev; + pinctrl->data = (struct airoha_pinctrl_match_data *)dev_get_driver_data(dev); + + pinctrl->regmap = syscon_node_to_regmap(dev_ofnode(dev->parent)); + if (IS_ERR(pinctrl->regmap)) + return PTR_ERR(pinctrl->regmap); + + pinctrl->chip_scu = airoha_get_chip_scu_regmap(); + if (IS_ERR(pinctrl->chip_scu)) + return PTR_ERR(pinctrl->chip_scu); + + pinctrl->gpiochip.data = gpio_data_regs; + pinctrl->gpiochip.dir = gpio_dir_regs; + pinctrl->gpiochip.out = gpio_out_regs; + pinctrl->gpiochip.status = irq_status_regs; + pinctrl->gpiochip.level = irq_level_regs; + pinctrl->gpiochip.edge = irq_edge_regs; + + return 0; +} + +int airoha_pinctrl_bind(struct udevice *dev) +{ + if (airoha_pinctrl_gpio_register(dev)) + debug("Warning: can't bind gpio driver with device node\n"); + + /* + * Make sure that the pinctrl driver gets probed after binding, + * otherwise GPIO interface driver will not be probed as well. + * GPIOs of non-probed driver can't be used. + */ + dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND); + + return 0; +} diff --git a/drivers/pinctrl/airoha/pinctrl-an7581.c b/drivers/pinctrl/airoha/pinctrl-an7581.c new file mode 100644 index 00000000000..4f7da74a1cf --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-an7581.c @@ -0,0 +1,1484 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi <[email protected]> + * Author: Benjamin Larsson <[email protected]> + * Author: Markus Gothe <[email protected]> + */ + +#include "airoha-common.h" + +/* MUX */ +#define REG_GPIO_2ND_I2C_MODE 0x0214 +#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(14) +#define GPIO_I2C_MASTER_MODE_MODE BIT(13) +#define GPIO_I2S_MODE_MASK BIT(12) +#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) +#define GPIO_2ND_I2C_MODE_MASK BIT(0) + +#define REG_GPIO_SPI_CS1_MODE 0x0218 +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS4_MODE_MASK BIT(3) +#define GPIO_SPI_CS3_MODE_MASK BIT(2) +#define GPIO_SPI_CS2_MODE_MASK BIT(1) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x021c +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define GPIO_PCIE_RESET2_MASK BIT(12) +#define SIPO_RCLK_MODE_MASK BIT(11) +#define GPIO_PCIE_RESET1_MASK BIT(10) +#define GPIO_PCIE_RESET0_MASK BIT(9) +#define GPIO_UART5_MODE_MASK BIT(8) +#define GPIO_UART4_MODE_MASK BIT(7) +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) +#define GPIO_HSUART_MODE_MASK BIT(5) +#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) +#define GPIO_UART2_MODE_MASK BIT(3) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_EMMC_MODE_MASK BIT(1) +#define GPIO_PON_MODE_MASK BIT(0) + +#define REG_NPU_UART_EN 0x0224 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) + +#define REG_FORCE_GPIO_EN 0x0228 +#define FORCE_GPIO_EN(n) BIT(n) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x027c +#define REG_LAN_LED1_MAPPING 0x0280 + +#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) +#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* CONF */ +#define REG_I2C_SDA_E2 0x001c +#define SPI_MISO_E2_MASK BIT(14) +#define SPI_MOSI_E2_MASK BIT(13) +#define SPI_CLK_E2_MASK BIT(12) +#define SPI_CS0_E2_MASK BIT(11) +#define PCIE2_RESET_E2_MASK BIT(10) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define SPI_MISO_E4_MASK BIT(14) +#define SPI_MOSI_E4_MASK BIT(13) +#define SPI_CLK_E4_MASK BIT(12) +#define SPI_CS0_E4_MASK BIT(11) +#define PCIE2_RESET_E4_MASK BIT(10) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 +#define REG_GPIO_H_E2 0x002c +#define REG_GPIO_H_E4 0x0030 + +#define REG_I2C_SDA_PU 0x0044 +#define SPI_MISO_PU_MASK BIT(14) +#define SPI_MOSI_PU_MASK BIT(13) +#define SPI_CLK_PU_MASK BIT(12) +#define SPI_CS0_PU_MASK BIT(11) +#define PCIE2_RESET_PU_MASK BIT(10) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define SPI_MISO_PD_MASK BIT(14) +#define SPI_MOSI_PD_MASK BIT(13) +#define SPI_CLK_PD_MASK BIT(12) +#define SPI_CS0_PD_MASK BIT(11) +#define PCIE2_RESET_PD_MASK BIT(10) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 +#define REG_GPIO_H_PU 0x0054 +#define REG_GPIO_H_PD 0x0058 + +#define REG_PCIE_RESET_OD 0x018c +#define PCIE2_RESET_OD_MASK BIT(2) +#define PCIE1_RESET_OD_MASK BIT(1) +#define PCIE0_RESET_OD_MASK BIT(0) + +/* PWM MODE CONF */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +/* PWM MODE CONF EXT */ +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO51_FLASH_MODE_CFG BIT(31) +#define GPIO50_FLASH_MODE_CFG BIT(30) +#define GPIO49_FLASH_MODE_CFG BIT(29) +#define GPIO48_FLASH_MODE_CFG BIT(28) +#define GPIO47_FLASH_MODE_CFG BIT(27) +#define GPIO46_FLASH_MODE_CFG BIT(26) +#define GPIO45_FLASH_MODE_CFG BIT(25) +#define GPIO44_FLASH_MODE_CFG BIT(24) +#define GPIO43_FLASH_MODE_CFG BIT(23) +#define GPIO42_FLASH_MODE_CFG BIT(22) +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +static struct pinctrl_pin_desc pinctrl_pins[] = { + PINCTRL_PIN(0, "uart1_txd"), + PINCTRL_PIN(1, "uart1_rxd"), + PINCTRL_PIN(2, "i2c_scl"), + PINCTRL_PIN(3, "i2c_sda"), + PINCTRL_PIN(4, "spi_cs0"), + PINCTRL_PIN(5, "spi_clk"), + PINCTRL_PIN(6, "spi_mosi"), + PINCTRL_PIN(7, "spi_miso"), + PINCTRL_PIN(13, "gpio0"), + PINCTRL_PIN(14, "gpio1"), + PINCTRL_PIN(15, "gpio2"), + PINCTRL_PIN(16, "gpio3"), + PINCTRL_PIN(17, "gpio4"), + PINCTRL_PIN(18, "gpio5"), + PINCTRL_PIN(19, "gpio6"), + PINCTRL_PIN(20, "gpio7"), + PINCTRL_PIN(21, "gpio8"), + PINCTRL_PIN(22, "gpio9"), + PINCTRL_PIN(23, "gpio10"), + PINCTRL_PIN(24, "gpio11"), + PINCTRL_PIN(25, "gpio12"), + PINCTRL_PIN(26, "gpio13"), + PINCTRL_PIN(27, "gpio14"), + PINCTRL_PIN(28, "gpio15"), + PINCTRL_PIN(29, "gpio16"), + PINCTRL_PIN(30, "gpio17"), + PINCTRL_PIN(31, "gpio18"), + PINCTRL_PIN(32, "gpio19"), + PINCTRL_PIN(33, "gpio20"), + PINCTRL_PIN(34, "gpio21"), + PINCTRL_PIN(35, "gpio22"), + PINCTRL_PIN(36, "gpio23"), + PINCTRL_PIN(37, "gpio24"), + PINCTRL_PIN(38, "gpio25"), + PINCTRL_PIN(39, "gpio26"), + PINCTRL_PIN(40, "gpio27"), + PINCTRL_PIN(41, "gpio28"), + PINCTRL_PIN(42, "gpio29"), + PINCTRL_PIN(43, "gpio30"), + PINCTRL_PIN(44, "gpio31"), + PINCTRL_PIN(45, "gpio32"), + PINCTRL_PIN(46, "gpio33"), + PINCTRL_PIN(47, "gpio34"), + PINCTRL_PIN(48, "gpio35"), + PINCTRL_PIN(49, "gpio36"), + PINCTRL_PIN(50, "gpio37"), + PINCTRL_PIN(51, "gpio38"), + PINCTRL_PIN(52, "gpio39"), + PINCTRL_PIN(53, "gpio40"), + PINCTRL_PIN(54, "gpio41"), + PINCTRL_PIN(55, "gpio42"), + PINCTRL_PIN(56, "gpio43"), + PINCTRL_PIN(57, "gpio44"), + PINCTRL_PIN(58, "gpio45"), + PINCTRL_PIN(59, "gpio46"), + PINCTRL_PIN(60, "pcie_reset0"), + PINCTRL_PIN(61, "pcie_reset1"), + PINCTRL_PIN(62, "pcie_reset2"), +}; + +static const int pon_pins[] = { 49, 50, 51, 52, 53, 54 }; +static const int pon_tod_1pps_pins[] = { 46 }; +static const int gsw_tod_1pps_pins[] = { 46 }; +static const int sipo_pins[] = { 16, 17 }; +static const int sipo_rclk_pins[] = { 16, 17, 43 }; +static const int mdio_pins[] = { 14, 15 }; +static const int uart2_pins[] = { 48, 55 }; +static const int uart2_cts_rts_pins[] = { 46, 47 }; +static const int hsuart_pins[] = { 28, 29 }; +static const int hsuart_cts_rts_pins[] = { 26, 27 }; +static const int uart4_pins[] = { 38, 39 }; +static const int uart5_pins[] = { 18, 19 }; +static const int i2c0_pins[] = { 2, 3 }; +static const int i2c1_pins[] = { 14, 15 }; +static const int jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; +static const int jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; +static const int i2s_pins[] = { 26, 27, 28, 29 }; +static const int pcm1_pins[] = { 22, 23, 24, 25 }; +static const int pcm2_pins[] = { 18, 19, 20, 21 }; +static const int spi_quad_pins[] = { 32, 33 }; +static const int spi_pins[] = { 4, 5, 6, 7 }; +static const int spi_cs1_pins[] = { 34 }; +static const int pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; +static const int pcm_spi_int_pins[] = { 14 }; +static const int pcm_spi_rst_pins[] = { 15 }; +static const int pcm_spi_cs1_pins[] = { 43 }; +static const int pcm_spi_cs2_pins[] = { 40 }; +static const int pcm_spi_cs2_p128_pins[] = { 40 }; +static const int pcm_spi_cs2_p156_pins[] = { 40 }; +static const int pcm_spi_cs3_pins[] = { 41 }; +static const int pcm_spi_cs4_pins[] = { 42 }; +static const int emmc_pins[] = { + 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 +}; +static const int pnand_pins[] = { + 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 +}; +static const int gpio0_pins[] = { 13 }; +static const int gpio1_pins[] = { 14 }; +static const int gpio2_pins[] = { 15 }; +static const int gpio3_pins[] = { 16 }; +static const int gpio4_pins[] = { 17 }; +static const int gpio5_pins[] = { 18 }; +static const int gpio6_pins[] = { 19 }; +static const int gpio7_pins[] = { 20 }; +static const int gpio8_pins[] = { 21 }; +static const int gpio9_pins[] = { 22 }; +static const int gpio10_pins[] = { 23 }; +static const int gpio11_pins[] = { 24 }; +static const int gpio12_pins[] = { 25 }; +static const int gpio13_pins[] = { 26 }; +static const int gpio14_pins[] = { 27 }; +static const int gpio15_pins[] = { 28 }; +static const int gpio16_pins[] = { 29 }; +static const int gpio17_pins[] = { 30 }; +static const int gpio18_pins[] = { 31 }; +static const int gpio19_pins[] = { 32 }; +static const int gpio20_pins[] = { 33 }; +static const int gpio21_pins[] = { 34 }; +static const int gpio22_pins[] = { 35 }; +static const int gpio23_pins[] = { 36 }; +static const int gpio24_pins[] = { 37 }; +static const int gpio25_pins[] = { 38 }; +static const int gpio26_pins[] = { 39 }; +static const int gpio27_pins[] = { 40 }; +static const int gpio28_pins[] = { 41 }; +static const int gpio29_pins[] = { 42 }; +static const int gpio30_pins[] = { 43 }; +static const int gpio31_pins[] = { 44 }; +static const int gpio32_pins[] = { 45 }; +static const int gpio33_pins[] = { 46 }; +static const int gpio34_pins[] = { 47 }; +static const int gpio35_pins[] = { 48 }; +static const int gpio36_pins[] = { 49 }; +static const int gpio37_pins[] = { 50 }; +static const int gpio38_pins[] = { 51 }; +static const int gpio39_pins[] = { 52 }; +static const int gpio40_pins[] = { 53 }; +static const int gpio41_pins[] = { 54 }; +static const int gpio42_pins[] = { 55 }; +static const int gpio43_pins[] = { 56 }; +static const int gpio44_pins[] = { 57 }; +static const int gpio45_pins[] = { 58 }; +static const int gpio46_pins[] = { 59 }; +static const int gpio47_pins[] = { 60 }; +static const int gpio48_pins[] = { 61 }; +static const int gpio49_pins[] = { 62 }; +static const int pcie_reset0_pins[] = { 60 }; +static const int pcie_reset1_pins[] = { 61 }; +static const int pcie_reset2_pins[] = { 62 }; + +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), + PINCTRL_PIN_GROUP("uart4", uart4), + PINCTRL_PIN_GROUP("uart5", uart5), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("i2s", i2s), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156), + PINCTRL_PIN_GROUP("pcm_spi_cs2", pcm_spi_cs2), + PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4), + PINCTRL_PIN_GROUP("emmc", emmc), + PINCTRL_PIN_GROUP("pnand", pnand), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("gpio30", gpio30), + PINCTRL_PIN_GROUP("gpio31", gpio31), + PINCTRL_PIN_GROUP("gpio32", gpio32), + PINCTRL_PIN_GROUP("gpio33", gpio33), + PINCTRL_PIN_GROUP("gpio34", gpio34), + PINCTRL_PIN_GROUP("gpio35", gpio35), + PINCTRL_PIN_GROUP("gpio36", gpio36), + PINCTRL_PIN_GROUP("gpio37", gpio37), + PINCTRL_PIN_GROUP("gpio38", gpio38), + PINCTRL_PIN_GROUP("gpio39", gpio39), + PINCTRL_PIN_GROUP("gpio40", gpio40), + PINCTRL_PIN_GROUP("gpio41", gpio41), + PINCTRL_PIN_GROUP("gpio42", gpio42), + PINCTRL_PIN_GROUP("gpio43", gpio43), + PINCTRL_PIN_GROUP("gpio44", gpio44), + PINCTRL_PIN_GROUP("gpio45", gpio45), + PINCTRL_PIN_GROUP("gpio46", gpio46), + PINCTRL_PIN_GROUP("gpio47", gpio47), + PINCTRL_PIN_GROUP("gpio48", gpio48), + PINCTRL_PIN_GROUP("gpio49", gpio49), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), + PINCTRL_PIN_GROUP("pcie_reset2", pcie_reset2), +}; + +static const char *const pon_groups[] = { "pon" }; +static const char *const tod_1pps_groups[] = { + "pon_tod_1pps", "gsw_tod_1pps" +}; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { + "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", + "uart4", "uart5" +}; +static const char *const i2c_groups[] = { "i2c1" }; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] = { + "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1", + "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", + "pcm_spi_cs4" +}; +static const char *const i2s_groups[] = { "i2s" }; +static const char *const emmc_groups[] = { "emmc" }; +static const char *const pnand_groups[] = { "pnand" }; +static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" }; +static const char *const pcie_reset_groups[] = { + "pcie_reset0", "pcie_reset1", "pcie_reset2" +}; +static const char *const pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", "gpio49" +}; +static const char *const phy1_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy2_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy3_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy4_led0_groups[] = { + "gpio33", "gpio34", "gpio35", "gpio42" +}; +static const char *const phy1_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char *const phy2_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char *const phy3_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; +static const char *const phy4_led1_groups[] = { + "gpio43", "gpio44", "gpio45", "gpio46" +}; + +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { + { + .name = "pon_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "gsw_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_MDC_IO_MASTER_MODE_MASK, + GPIO_MDC_IO_MASTER_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_FORCE_GPIO_EN, + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), + FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "uart2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart2_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "hsuart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK + }, + .regmap_size = 1, + }, + { + .name = "hsuart_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART4_MODE_MASK, + GPIO_UART4_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart5", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART5_MODE_MASK, + GPIO_UART5_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2c_func_group[] = { + { + .name = "i2c1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_2ND_I2C_MODE_MASK, + GPIO_2ND_I2C_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS2_MODE_MASK, + GPIO_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS3_MODE_MASK, + GPIO_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS4_MODE_MASK, + GPIO_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p128", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P128_MASK, + GPIO_PCM_SPI_CS2_MODE_P128_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p156", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P156_MASK, + GPIO_PCM_SPI_CS2_MODE_P156_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2s_func_group[] = { + { + .name = "i2s", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_I2S_MODE_MASK, + GPIO_I2S_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group emmc_func_group[] = { + { + .name = "emmc", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_EMMC_MODE_MASK, + GPIO_EMMC_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pnand_func_group[] = { + { + .name = "pnand", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PARALLEL_NAND_MODE_MASK, + GPIO_PARALLEL_NAND_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET2_MASK), +}; + +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET2_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET2_MASK), +}; + +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("i2s", i2s), + PINCTRL_FUNC_DESC("emmc", emmc), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), + PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), + PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), + PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), + PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), + PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), + PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), + PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), + PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), + PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), + PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), + PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), + PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), + PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), + PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), + PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), + PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), + PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), + PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { + PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), + PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), +}; + +static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .gpio_offs = 13, + .gpio_pin_cnt = 50, + .chip_scu_compatible = "airoha,en7581-chip-scu", + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { + .confs = pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf), + }, + }, +}; + +static const struct udevice_id pinctrl_of_match[] = { + { .compatible = "airoha,en7581-pinctrl", + .data = (uintptr_t)&pinctrl_match_data }, + { .compatible = "airoha,an7581-pinctrl", + .data = (uintptr_t)&pinctrl_match_data }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(airoha_an7581_pinctrl) = { + .name = "airoha-an7581-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(pinctrl_of_match), + .probe = airoha_pinctrl_probe, + .bind = airoha_pinctrl_bind, + .priv_auto = sizeof(struct airoha_pinctrl), + .ops = &airoha_pinctrl_ops, +}; diff --git a/drivers/pinctrl/airoha/pinctrl-an7583.c b/drivers/pinctrl/airoha/pinctrl-an7583.c new file mode 100644 index 00000000000..2f6f3651ec8 --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-an7583.c @@ -0,0 +1,1492 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi <[email protected]> + * Author: Benjamin Larsson <[email protected]> + * Author: Markus Gothe <[email protected]> + */ + +#include "airoha-common.h" + +/* MUX */ +#define REG_SW_TOD_1PPS_MODE 0x0214 +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) + +#define REG_GPIO_SPI_CS1_MODE 0x0218 +#define GPIO_MDC_IO_MASTER_MODE_MASK BIT(22) +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS4_MODE_MASK BIT(3) +#define GPIO_SPI_CS3_MODE_MASK BIT(2) +#define GPIO_SPI_CS2_MODE_MASK BIT(1) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x021c +#define GPIO_PON_ALT_MODE_MASK BIT(27) +#define MDIO_0_GPIO_MODE_MASK BIT(26) +#define MDC_0_GPIO_MODE_MASK BIT(25) +#define UART_RXD_GPIO_MODE_MASK BIT(24) +#define UART_TXD_GPIO_MODE_MASK BIT(23) +#define SPI_MISO_GPIO_MODE_MASK BIT(22) +#define SPI_MOSI_GPIO_MODE_MASK BIT(21) +#define SPI_CS_GPIO_MODE_MASK BIT(20) +#define SPI_CLK_GPIO_MODE_MASK BIT(19) +#define I2C1_SDA_GPIO_MODE_MASK BIT(18) +#define I2C1_SCL_GPIO_MODE_MASK BIT(17) +#define I2C0_SDA_GPIO_MODE_MASK BIT(16) +#define I2C0_SCL_GPIO_MODE_MASK BIT(15) +#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define GPIO_OLT_MODE_MASK BIT(12) +#define SIPO_RCLK_MODE_MASK BIT(11) +#define GPIO_PCIE_RESET1_MASK BIT(10) +#define GPIO_PCIE_RESET0_MASK BIT(9) +#define GPIO_UART5_MODE_MASK BIT(8) +#define GPIO_UART4_MODE_MASK BIT(7) +#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) +#define GPIO_HSUART_MODE_MASK BIT(5) +#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) +#define GPIO_UART2_MODE_MASK BIT(3) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_EMMC_MODE_MASK BIT(1) +#define GPIO_PON_MODE_MASK BIT(0) + +#define REG_NPU_UART_EN 0x0224 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) +#define NPU_UART_EN_MASK BIT(2) + +#define REG_FORCE_GPIO_EN 0x0228 +#define FORCE_GPIO_EN(n) BIT(n) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x027c +#define REG_LAN_LED1_MAPPING 0x0280 + +#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) +#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* CONF */ +#define REG_I2C_SDA_E2 0x001c +#define I2C1_SCL_E2_MASK BIT(16) +#define I2C1_SDA_E2_MASK BIT(15) +#define SPI_MISO_E2_MASK BIT(14) +#define SPI_MOSI_E2_MASK BIT(13) +#define SPI_CLK_E2_MASK BIT(12) +#define SPI_CS0_E2_MASK BIT(11) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define MDIO_0_E2_MASK BIT(5) +#define MDC_0_E2_MASK BIT(4) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define I2C1_SCL_E4_MASK BIT(16) +#define I2C1_SDA_E4_MASK BIT(15) +#define SPI_MISO_E4_MASK BIT(14) +#define SPI_MOSI_E4_MASK BIT(13) +#define SPI_CLK_E4_MASK BIT(12) +#define SPI_CS0_E4_MASK BIT(11) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define MDIO_0_E4_MASK BIT(5) +#define MDC_0_E4_MASK BIT(4) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 +#define REG_GPIO_H_E2 0x002c +#define REG_GPIO_H_E4 0x0030 + +#define REG_I2C_SDA_PU 0x0044 +#define I2C1_SCL_PU_MASK BIT(16) +#define I2C1_SDA_PU_MASK BIT(15) +#define SPI_MISO_PU_MASK BIT(14) +#define SPI_MOSI_PU_MASK BIT(13) +#define SPI_CLK_PU_MASK BIT(12) +#define SPI_CS0_PU_MASK BIT(11) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define MDIO_0_PU_MASK BIT(5) +#define MDC_0_PU_MASK BIT(4) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define I2C1_SCL_PD_MASK BIT(16) +#define I2C1_SDA_PD_MASK BIT(15) +#define SPI_MISO_PD_MASK BIT(14) +#define SPI_MOSI_PD_MASK BIT(13) +#define SPI_CLK_PD_MASK BIT(12) +#define SPI_CS0_PD_MASK BIT(11) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define MDIO_0_PD_MASK BIT(5) +#define MDC_0_PD_MASK BIT(4) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 +#define REG_GPIO_H_PU 0x0054 +#define REG_GPIO_H_PD 0x0058 + +#define REG_PCIE_RESET_OD 0x018c +#define PCIE1_RESET_OD_MASK BIT(1) +#define PCIE0_RESET_OD_MASK BIT(0) + +/* PWM MODE CONF */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +/* PWM MODE CONF EXT */ +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO51_FLASH_MODE_CFG BIT(31) +#define GPIO50_FLASH_MODE_CFG BIT(30) +#define GPIO49_FLASH_MODE_CFG BIT(29) +#define GPIO48_FLASH_MODE_CFG BIT(28) +#define GPIO47_FLASH_MODE_CFG BIT(27) +#define GPIO46_FLASH_MODE_CFG BIT(26) +#define GPIO45_FLASH_MODE_CFG BIT(25) +#define GPIO44_FLASH_MODE_CFG BIT(24) +#define GPIO43_FLASH_MODE_CFG BIT(23) +#define GPIO42_FLASH_MODE_CFG BIT(22) +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_SW_TOD_1PPS_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_SW_TOD_1PPS_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +static struct pinctrl_pin_desc pinctrl_pins[] = { + PINCTRL_PIN(2, "gpio0"), + PINCTRL_PIN(3, "gpio1"), + PINCTRL_PIN(4, "gpio2"), + PINCTRL_PIN(5, "gpio3"), + PINCTRL_PIN(6, "gpio4"), + PINCTRL_PIN(7, "gpio5"), + PINCTRL_PIN(8, "gpio6"), + PINCTRL_PIN(9, "gpio7"), + PINCTRL_PIN(10, "gpio8"), + PINCTRL_PIN(11, "gpio9"), + PINCTRL_PIN(12, "gpio10"), + PINCTRL_PIN(13, "gpio11"), + PINCTRL_PIN(14, "gpio12"), + PINCTRL_PIN(15, "gpio13"), + PINCTRL_PIN(16, "gpio14"), + PINCTRL_PIN(17, "gpio15"), + PINCTRL_PIN(18, "gpio16"), + PINCTRL_PIN(19, "gpio17"), + PINCTRL_PIN(20, "gpio18"), + PINCTRL_PIN(21, "gpio19"), + PINCTRL_PIN(22, "gpio20"), + PINCTRL_PIN(23, "gpio21"), + PINCTRL_PIN(24, "gpio22"), + PINCTRL_PIN(25, "gpio23"), + PINCTRL_PIN(26, "gpio24"), + PINCTRL_PIN(27, "gpio25"), + PINCTRL_PIN(28, "gpio26"), + PINCTRL_PIN(29, "gpio27"), + PINCTRL_PIN(30, "gpio28"), + PINCTRL_PIN(31, "gpio29"), + PINCTRL_PIN(32, "gpio30"), + PINCTRL_PIN(33, "gpio31"), + PINCTRL_PIN(34, "gpio32"), + PINCTRL_PIN(35, "gpio33"), + PINCTRL_PIN(36, "gpio34"), + PINCTRL_PIN(37, "gpio35"), + PINCTRL_PIN(38, "gpio36"), + PINCTRL_PIN(39, "gpio37"), + PINCTRL_PIN(40, "gpio38"), + PINCTRL_PIN(41, "i2c0_scl"), + PINCTRL_PIN(42, "i2c0_sda"), + PINCTRL_PIN(43, "i2c1_scl"), + PINCTRL_PIN(44, "i2c1_sda"), + PINCTRL_PIN(45, "spi_clk"), + PINCTRL_PIN(46, "spi_cs"), + PINCTRL_PIN(47, "spi_mosi"), + PINCTRL_PIN(48, "spi_miso"), + PINCTRL_PIN(49, "uart_txd"), + PINCTRL_PIN(50, "uart_rxd"), + PINCTRL_PIN(51, "pcie_reset0"), + PINCTRL_PIN(52, "pcie_reset1"), + PINCTRL_PIN(53, "mdc_0"), + PINCTRL_PIN(54, "mdio_0"), +}; + +static const int pon_pins[] = { 15, 16, 17, 18, 19, 20 }; +static const int pon_alt_pins[] = { 36, 37, 38, 39, 40 }; +static const int olt_pins[] = { 36, 37, 38, 39, 40 }; +static const int pon_tod_1pps_pins[] = { 32 }; +static const int gsw_tod_1pps_pins[] = { 32 }; +static const int sipo_pins[] = { 34, 35 }; +static const int sipo_rclk_pins[] = { 34, 35, 33 }; +static const int mdio_pins[] = { 43, 44 }; +static const int uart2_pins[] = { 34, 35 }; +static const int uart2_cts_rts_pins[] = { 32, 33 }; +static const int hsuart_pins[] = { 30, 31 }; +static const int hsuart_cts_rts_pins[] = { 28, 29 }; +static const int npu_uart_pins[] = { 7, 8 }; +static const int uart4_pins[] = { 7, 8 }; +static const int uart5_pins[] = { 23, 24 }; +static const int i2c0_pins[] = { 41, 42 }; +static const int i2c1_pins[] = { 43, 44 }; +static const int jtag_udi_pins[] = { 23, 24, 22, 25, 26 }; +static const int jtag_dfd_pins[] = { 23, 24, 22, 25, 26 }; +static const int pcm1_pins[] = { 10, 11, 12, 13, 14 }; +static const int pcm2_pins[] = { 28, 29, 30, 31, 24 }; +static const int spi_pins[] = { 28, 29, 30, 31 }; +static const int spi_quad_pins[] = { 25, 26 }; +static const int spi_cs1_pins[] = { 27 }; +static const int pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 }; +static const int pcm_spi_rst_pins[] = { 14 }; +static const int pcm_spi_cs1_pins[] = { 24 }; +static const int emmc_pins[] = { + 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 +}; +static const int pnand_pins[] = { + 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 +}; +static const int gpio0_pins[] = { 2 }; +static const int gpio1_pins[] = { 3 }; +static const int gpio2_pins[] = { 4 }; +static const int gpio3_pins[] = { 5 }; +static const int gpio4_pins[] = { 6 }; +static const int gpio5_pins[] = { 7 }; +static const int gpio6_pins[] = { 8 }; +static const int gpio7_pins[] = { 9 }; +static const int gpio8_pins[] = { 10 }; +static const int gpio9_pins[] = { 11 }; +static const int gpio10_pins[] = { 12 }; +static const int gpio11_pins[] = { 13 }; +static const int gpio12_pins[] = { 14 }; +static const int gpio13_pins[] = { 15 }; +static const int gpio14_pins[] = { 16 }; +static const int gpio15_pins[] = { 17 }; +static const int gpio16_pins[] = { 18 }; +static const int gpio17_pins[] = { 19 }; +static const int gpio18_pins[] = { 20 }; +static const int gpio19_pins[] = { 21 }; +static const int gpio20_pins[] = { 22 }; +static const int gpio21_pins[] = { 23 }; +static const int gpio22_pins[] = { 24 }; +static const int gpio23_pins[] = { 25 }; +static const int gpio24_pins[] = { 26 }; +static const int gpio25_pins[] = { 27 }; +static const int gpio26_pins[] = { 28 }; +static const int gpio27_pins[] = { 29 }; +static const int gpio28_pins[] = { 30 }; +static const int gpio29_pins[] = { 31 }; +static const int gpio30_pins[] = { 32 }; +static const int gpio31_pins[] = { 33 }; +static const int gpio32_pins[] = { 34 }; +static const int gpio33_pins[] = { 35 }; +static const int gpio34_pins[] = { 36 }; +static const int gpio35_pins[] = { 37 }; +static const int gpio36_pins[] = { 38 }; +static const int gpio37_pins[] = { 39 }; +static const int gpio38_pins[] = { 40 }; +static const int gpio39_pins[] = { 41 }; +static const int gpio40_pins[] = { 42 }; +static const int gpio41_pins[] = { 43 }; +static const int gpio42_pins[] = { 44 }; +static const int gpio43_pins[] = { 45 }; +static const int gpio44_pins[] = { 46 }; +static const int gpio45_pins[] = { 47 }; +static const int gpio46_pins[] = { 48 }; +static const int gpio47_pins[] = { 49 }; +static const int gpio48_pins[] = { 50 }; +static const int gpio49_pins[] = { 51 }; +static const int gpio50_pins[] = { 52 }; +static const int gpio51_pins[] = { 53 }; +static const int gpio52_pins[] = { 54 }; +static const int pcie_reset0_pins[] = { 51 }; +static const int pcie_reset1_pins[] = { 52 }; + +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_alt", pon_alt), + PINCTRL_PIN_GROUP("olt", olt), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("uart2_cts_rts", uart2_cts_rts), + PINCTRL_PIN_GROUP("hsuart", hsuart), + PINCTRL_PIN_GROUP("hsuart_cts_rts", hsuart_cts_rts), + PINCTRL_PIN_GROUP("npu_uart", npu_uart), + PINCTRL_PIN_GROUP("uart4", uart4), + PINCTRL_PIN_GROUP("uart5", uart5), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("emmc", emmc), + PINCTRL_PIN_GROUP("pnand", pnand), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("gpio30", gpio30), + PINCTRL_PIN_GROUP("gpio31", gpio31), + PINCTRL_PIN_GROUP("gpio32", gpio32), + PINCTRL_PIN_GROUP("gpio33", gpio33), + PINCTRL_PIN_GROUP("gpio34", gpio34), + PINCTRL_PIN_GROUP("gpio35", gpio35), + PINCTRL_PIN_GROUP("gpio36", gpio36), + PINCTRL_PIN_GROUP("gpio37", gpio37), + PINCTRL_PIN_GROUP("gpio38", gpio38), + PINCTRL_PIN_GROUP("gpio39", gpio39), + PINCTRL_PIN_GROUP("gpio40", gpio40), + PINCTRL_PIN_GROUP("gpio41", gpio41), + PINCTRL_PIN_GROUP("gpio42", gpio42), + PINCTRL_PIN_GROUP("gpio43", gpio43), + PINCTRL_PIN_GROUP("gpio44", gpio44), + PINCTRL_PIN_GROUP("gpio45", gpio45), + PINCTRL_PIN_GROUP("gpio46", gpio46), + PINCTRL_PIN_GROUP("gpio47", gpio47), + PINCTRL_PIN_GROUP("gpio48", gpio48), + PINCTRL_PIN_GROUP("gpio49", gpio49), + PINCTRL_PIN_GROUP("gpio50", gpio50), + PINCTRL_PIN_GROUP("gpio51", gpio51), + PINCTRL_PIN_GROUP("gpio52", gpio52), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), +}; + +static const char *const pon_groups[] = { "pon", "pon_alt" }; +static const char *const olt_groups[] = { "olt" }; +static const char *const tod_1pps_groups[] = { + "pon_tod_1pps", "gsw_tod_1pps" +}; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { + "uart2", "uart2_cts_rts", "hsuart", "hsuart_cts_rts", + "uart4", "uart5", "npu_uart" +}; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] = { + "pcm_spi", "pcm_spi_rst", "pcm_spi_cs1" +}; +static const char *const emmc_groups[] = { "emmc" }; +static const char *const pnand_groups[] = { "pnand" }; +static const char *const gpio_groups[] = { + "gpio39", "gpio40", "gpio41", "gpio42", "gpio43", + "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", + "gpio49", "gpio50", "gpio51", "gpio52" +}; +static const char *const pcie_reset_groups[] = { + "pcie_reset0", "pcie_reset1" +}; +static const char *const pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", + "gpio30", "gpio31", "gpio36", "gpio37", "gpio38", "gpio39", + "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45", + "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51" +}; +static const char *const phy1_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const phy2_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const phy3_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const phy4_led0_groups[] = { + "gpio1", "gpio2", "gpio3", "gpio4" +}; +static const char *const phy1_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy2_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy3_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; +static const char *const phy4_led1_groups[] = { + "gpio8", "gpio9", "gpio10", "gpio11" +}; + +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pon_alt", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK | GPIO_PON_ALT_MODE_MASK, + GPIO_PON_ALT_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group olt_func_group[] = { + { + .name = "olt", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_OLT_MODE_MASK, + GPIO_OLT_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { + { + .name = "pon_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_SW_TOD_1PPS_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "gsw_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_SW_TOD_1PPS_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SGMII_MDIO_MODE_MASK, + GPIO_SGMII_MDIO_MODE_MASK + }, + .regmap[1] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_MDC_IO_MASTER_MODE_MASK, + GPIO_MDC_IO_MASTER_MODE_MASK + }, + .regmap_size = 2, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "uart2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart2_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, + GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "hsuart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK + }, + .regmap_size = 1, + }, + { + .name = "hsuart_cts_rts", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, + GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART4_MODE_MASK, + GPIO_UART4_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "uart5", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART5_MODE_MASK, + GPIO_UART5_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "npu_uart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + NPU_UART_EN_MASK, + NPU_UART_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS2_MODE_MASK, + GPIO_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS3_MODE_MASK, + GPIO_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS4_MODE_MASK, + GPIO_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_MASK, + GPIO_PCM_SPI_CS2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group emmc_func_group[] = { + { + .name = "emmc", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_EMMC_MODE_MASK, + GPIO_EMMC_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pnand_func_group[] = { + { + .name = "pnand", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PARALLEL_NAND_MODE_MASK, + GPIO_PARALLEL_NAND_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio39", GPIO39_FLASH_MODE_CFG, + I2C0_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio40", GPIO40_FLASH_MODE_CFG, + I2C0_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio41", GPIO41_FLASH_MODE_CFG, + I2C1_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio42", GPIO42_FLASH_MODE_CFG, + I2C1_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio43", GPIO43_FLASH_MODE_CFG, + SPI_CLK_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio44", GPIO44_FLASH_MODE_CFG, + SPI_CS_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio45", GPIO45_FLASH_MODE_CFG, + SPI_MOSI_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio46", GPIO46_FLASH_MODE_CFG, + SPI_MISO_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG, + UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG, + UART_RXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio50", GPIO50_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio51", GPIO51_FLASH_MODE_CFG, + MDC_0_GPIO_MODE_MASK), + AIROHA_PINCTRL_GPIO("gpio52", MDIO_0_GPIO_MODE_MASK), +}; + +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio39", GPIO39_FLASH_MODE_CFG, + I2C0_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio40", GPIO40_FLASH_MODE_CFG, + I2C0_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio41", GPIO41_FLASH_MODE_CFG, + I2C1_SCL_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio42", GPIO42_FLASH_MODE_CFG, + I2C1_SDA_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio43", GPIO43_FLASH_MODE_CFG, + SPI_CLK_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio44", GPIO44_FLASH_MODE_CFG, + SPI_CS_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio45", GPIO45_FLASH_MODE_CFG, + SPI_MOSI_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio46", GPIO46_FLASH_MODE_CFG, + SPI_MISO_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG, + UART_TXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG, + UART_RXD_GPIO_MODE_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio50", GPIO50_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio51", GPIO51_FLASH_MODE_CFG, + MDC_0_GPIO_MODE_MASK), +}; + +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("olt", olt), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("emmc", emmc), + PINCTRL_FUNC_DESC("pnand", pnand), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, I2C1_SCL_PU_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, I2C1_SDA_PU_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, MDC_0_PU_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, MDIO_0_PU_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, I2C1_SCL_PD_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, I2C1_SDA_PD_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, MDC_0_PD_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, MDIO_0_PD_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, I2C1_SCL_E2_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, I2C1_SDA_E2_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, MDC_0_E2_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, MDIO_0_E2_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), + PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), + PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), + PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), + PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), + PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), + PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), + PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), + PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), + PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), + PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, I2C1_SCL_E4_MASK), + PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, I2C1_SDA_E4_MASK), + PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), + PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), + PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), + PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), + PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), + PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), + PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), + PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), + PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, MDC_0_E4_MASK), + PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, MDIO_0_E4_MASK), +}; + +static const struct airoha_pinctrl_conf pinctrl_pcie_rst_od_conf[] = { + PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), + PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), +}; + +static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .gpio_offs = 2, + .gpio_pin_cnt = 53, + .chip_scu_compatible = "airoha,en7581-chip-scu", + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), + }, + [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { + .confs = pinctrl_pcie_rst_od_conf, + .num_confs = ARRAY_SIZE(pinctrl_pcie_rst_od_conf), + }, + }, +}; + +static const struct udevice_id pinctrl_of_match[] = { + { .compatible = "airoha,an7583-pinctrl", + .data = (uintptr_t)&pinctrl_match_data }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(airoha_an7583_pinctrl) = { + .name = "airoha-an7583-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(pinctrl_of_match), + .probe = airoha_pinctrl_probe, + .bind = airoha_pinctrl_bind, + .priv_auto = sizeof(struct airoha_pinctrl), + .ops = &airoha_pinctrl_ops, +}; diff --git a/drivers/pinctrl/airoha/pinctrl-en7523.c b/drivers/pinctrl/airoha/pinctrl-en7523.c new file mode 100644 index 00000000000..958fcc8418f --- /dev/null +++ b/drivers/pinctrl/airoha/pinctrl-en7523.c @@ -0,0 +1,1118 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Author: Lorenzo Bianconi <[email protected]> + * Author: Benjamin Larsson <[email protected]> + * Author: Markus Gothe <[email protected]> + * Author: Matheus Sampaio Queiroga <[email protected]> + * Author: Mikhail Kshevetskiy <[email protected]> + */ +#include "airoha-common.h" + +/* MUX */ +#define REG_GPIO_2ND_I2C_MODE 0x0210 +#define GPIO_I2S_MODE_MASK BIT(12) +#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) +#define GPIO_LAN3_LED1_MODE_MASK BIT(10) +#define GPIO_LAN3_LED0_MODE_MASK BIT(9) +#define GPIO_LAN2_LED1_MODE_MASK BIT(8) +#define GPIO_LAN2_LED0_MODE_MASK BIT(7) +#define GPIO_LAN1_LED1_MODE_MASK BIT(6) +#define GPIO_LAN1_LED0_MODE_MASK BIT(5) +#define GPIO_LAN0_LED1_MODE_MASK BIT(4) +#define GPIO_LAN0_LED0_MODE_MASK BIT(3) +#define PON_TOD_1PPS_MODE_MASK BIT(2) +#define GSW_TOD_1PPS_MODE_MASK BIT(1) +#define GPIO_2ND_I2C_MODE_MASK BIT(0) + +#define REG_GPIO_SPI_CS1_MODE 0x0214 +#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) +#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) +#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) +#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) +#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) +#define GPIO_PCM_SPI_MODE_MASK BIT(16) +#define GPIO_PCM2_MODE_MASK BIT(13) +#define GPIO_PCM1_MODE_MASK BIT(12) +#define GPIO_PCM_INT_MODE_MASK BIT(9) +#define GPIO_PCM_RESET_MODE_MASK BIT(8) +#define GPIO_SPI_QUAD_MODE_MASK BIT(4) +#define GPIO_SPI_CS1_MODE_MASK BIT(0) + +#define REG_GPIO_PON_MODE 0x0218 +#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) +#define SIPO_RCLK_MODE_MASK BIT(11) +#define GPIO_PCIE_RESET1_MASK BIT(10) +#define GPIO_PCIE_RESET0_MASK BIT(9) +#define GPIO_UART2_MODE_MASK BIT(3) +#define GPIO_SIPO_MODE_MASK BIT(2) +#define GPIO_PON_MODE_MASK BIT(0) + +#define REG_NPU_UART_EN 0x0220 +#define JTAG_UDI_EN_MASK BIT(4) +#define JTAG_DFD_EN_MASK BIT(3) +#define NPU_UART_EN_MASK BIT(2) + +#define REG_FORCE_GPIO_EN 0x0224 +#define FORCE_GPIO_EN(n) BIT(n) + +/* LED MAP */ +#define REG_LAN_LED0_MAPPING 0x0278 +#define REG_LAN_LED1_MAPPING 0x027c + +#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) +#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) + +#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) +#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) + +#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) +#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) + +#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) +#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) + +/* CONF */ +#define REG_I2C_SDA_E2 0x001c +#define SPI_MISO_E2_MASK BIT(13) +#define SPI_MOSI_E2_MASK BIT(12) +#define SPI_CLK_E2_MASK BIT(11) +#define SPI_CS0_E2_MASK BIT(10) +#define PCIE1_RESET_E2_MASK BIT(9) +#define PCIE0_RESET_E2_MASK BIT(8) +#define UART1_RXD_E2_MASK BIT(3) +#define UART1_TXD_E2_MASK BIT(2) +#define I2C_SCL_E2_MASK BIT(1) +#define I2C_SDA_E2_MASK BIT(0) + +#define REG_I2C_SDA_E4 0x0020 +#define SPI_MISO_E4_MASK BIT(13) +#define SPI_MOSI_E4_MASK BIT(12) +#define SPI_CLK_E4_MASK BIT(11) +#define SPI_CS0_E4_MASK BIT(10) +#define PCIE1_RESET_E4_MASK BIT(9) +#define PCIE0_RESET_E4_MASK BIT(8) +#define UART1_RXD_E4_MASK BIT(3) +#define UART1_TXD_E4_MASK BIT(2) +#define I2C_SCL_E4_MASK BIT(1) +#define I2C_SDA_E4_MASK BIT(0) + +#define REG_GPIO_L_E2 0x0024 +#define REG_GPIO_L_E4 0x0028 + +#define REG_I2C_SDA_PU 0x0044 +#define SPI_MISO_PU_MASK BIT(13) +#define SPI_MOSI_PU_MASK BIT(12) +#define SPI_CLK_PU_MASK BIT(11) +#define SPI_CS0_PU_MASK BIT(10) +#define PCIE1_RESET_PU_MASK BIT(9) +#define PCIE0_RESET_PU_MASK BIT(8) +#define UART1_RXD_PU_MASK BIT(3) +#define UART1_TXD_PU_MASK BIT(2) +#define I2C_SCL_PU_MASK BIT(1) +#define I2C_SDA_PU_MASK BIT(0) + +#define REG_I2C_SDA_PD 0x0048 +#define SPI_MISO_PD_MASK BIT(13) +#define SPI_MOSI_PD_MASK BIT(12) +#define SPI_CLK_PD_MASK BIT(11) +#define SPI_CS0_PD_MASK BIT(10) +#define PCIE1_RESET_PD_MASK BIT(9) +#define PCIE0_RESET_PD_MASK BIT(8) +#define UART1_RXD_PD_MASK BIT(3) +#define UART1_TXD_PD_MASK BIT(2) +#define I2C_SCL_PD_MASK BIT(1) +#define I2C_SDA_PD_MASK BIT(0) + +#define REG_GPIO_L_PU 0x004c +#define REG_GPIO_L_PD 0x0050 + +/* PWM MODE CONF */ +#define REG_GPIO_FLASH_MODE_CFG 0x0034 +#define GPIO15_FLASH_MODE_CFG BIT(15) +#define GPIO14_FLASH_MODE_CFG BIT(14) +#define GPIO13_FLASH_MODE_CFG BIT(13) +#define GPIO12_FLASH_MODE_CFG BIT(12) +#define GPIO11_FLASH_MODE_CFG BIT(11) +#define GPIO10_FLASH_MODE_CFG BIT(10) +#define GPIO9_FLASH_MODE_CFG BIT(9) +#define GPIO8_FLASH_MODE_CFG BIT(8) +#define GPIO7_FLASH_MODE_CFG BIT(7) +#define GPIO6_FLASH_MODE_CFG BIT(6) +#define GPIO5_FLASH_MODE_CFG BIT(5) +#define GPIO4_FLASH_MODE_CFG BIT(4) +#define GPIO3_FLASH_MODE_CFG BIT(3) +#define GPIO2_FLASH_MODE_CFG BIT(2) +#define GPIO1_FLASH_MODE_CFG BIT(1) +#define GPIO0_FLASH_MODE_CFG BIT(0) + +/* PWM MODE CONF EXT */ +#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 +#define GPIO51_FLASH_MODE_CFG BIT(31) +#define GPIO50_FLASH_MODE_CFG BIT(30) +#define GPIO49_FLASH_MODE_CFG BIT(29) +#define GPIO48_FLASH_MODE_CFG BIT(28) +#define GPIO47_FLASH_MODE_CFG BIT(27) +#define GPIO46_FLASH_MODE_CFG BIT(26) +#define GPIO45_FLASH_MODE_CFG BIT(25) +#define GPIO44_FLASH_MODE_CFG BIT(24) +#define GPIO43_FLASH_MODE_CFG BIT(23) +#define GPIO42_FLASH_MODE_CFG BIT(22) +#define GPIO41_FLASH_MODE_CFG BIT(21) +#define GPIO40_FLASH_MODE_CFG BIT(20) +#define GPIO39_FLASH_MODE_CFG BIT(19) +#define GPIO38_FLASH_MODE_CFG BIT(18) +#define GPIO37_FLASH_MODE_CFG BIT(17) +#define GPIO36_FLASH_MODE_CFG BIT(16) +#define GPIO31_FLASH_MODE_CFG BIT(15) +#define GPIO30_FLASH_MODE_CFG BIT(14) +#define GPIO29_FLASH_MODE_CFG BIT(13) +#define GPIO28_FLASH_MODE_CFG BIT(12) +#define GPIO27_FLASH_MODE_CFG BIT(11) +#define GPIO26_FLASH_MODE_CFG BIT(10) +#define GPIO25_FLASH_MODE_CFG BIT(9) +#define GPIO24_FLASH_MODE_CFG BIT(8) +#define GPIO23_FLASH_MODE_CFG BIT(7) +#define GPIO22_FLASH_MODE_CFG BIT(6) +#define GPIO21_FLASH_MODE_CFG BIT(5) +#define GPIO20_FLASH_MODE_CFG BIT(4) +#define GPIO19_FLASH_MODE_CFG BIT(3) +#define GPIO18_FLASH_MODE_CFG BIT(2) +#define GPIO17_FLASH_MODE_CFG BIT(1) +#define GPIO16_FLASH_MODE_CFG BIT(0) + +#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + 0 \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +/* PWM */ +#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_MUX, \ + REG_GPIO_FLASH_MODE_CFG, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap_size = 1, \ + } + +#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_PWM_EXT_MUX, \ + REG_GPIO_FLASH_MODE_CFG_EXT, \ + (mux_val), \ + (mux_val) \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_PON_MODE, \ + (smux_val), \ + (smux_val) \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED0_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ + { \ + .name = (gpio), \ + .regmap[0] = { \ + AIROHA_FUNC_MUX, \ + REG_GPIO_2ND_I2C_MODE, \ + (mux_val), \ + (mux_val), \ + }, \ + .regmap[1] = { \ + AIROHA_FUNC_MUX, \ + REG_LAN_LED1_MAPPING, \ + (map_mask), \ + (map_val), \ + }, \ + .regmap_size = 2, \ + } + +static struct pinctrl_pin_desc pinctrl_pins[] = { + PINCTRL_PIN(2, "i2c_sda"), + PINCTRL_PIN(3, "i2c_scl"), + PINCTRL_PIN(4, "spi_cs0"), + PINCTRL_PIN(5, "spi_clk"), + PINCTRL_PIN(6, "spi_mosi"), + PINCTRL_PIN(7, "spi_miso"), + PINCTRL_PIN(8, "uart1_txd"), + PINCTRL_PIN(9, "uart1_rxd"), + PINCTRL_PIN(12, "gpio0"), + PINCTRL_PIN(13, "gpio1"), + PINCTRL_PIN(14, "gpio2"), + PINCTRL_PIN(15, "gpio3"), + PINCTRL_PIN(16, "gpio4"), + PINCTRL_PIN(17, "gpio5"), + PINCTRL_PIN(18, "gpio6"), + PINCTRL_PIN(19, "gpio7"), + PINCTRL_PIN(20, "gpio8"), + PINCTRL_PIN(21, "gpio9"), + PINCTRL_PIN(22, "gpio10"), + PINCTRL_PIN(23, "gpio11"), + PINCTRL_PIN(24, "gpio12"), + PINCTRL_PIN(25, "gpio13"), + PINCTRL_PIN(26, "gpio14"), + PINCTRL_PIN(27, "gpio15"), + PINCTRL_PIN(28, "gpio16"), + PINCTRL_PIN(29, "gpio17"), + PINCTRL_PIN(30, "gpio18"), + PINCTRL_PIN(31, "gpio19"), + PINCTRL_PIN(32, "gpio20"), + PINCTRL_PIN(33, "gpio21"), + PINCTRL_PIN(34, "gpio22"), + PINCTRL_PIN(35, "gpio23"), + PINCTRL_PIN(36, "gpio24"), + PINCTRL_PIN(37, "gpio25"), + PINCTRL_PIN(38, "gpio26"), + PINCTRL_PIN(39, "gpio27"), + PINCTRL_PIN(40, "pcie_reset0"), + PINCTRL_PIN(41, "pcie_reset1"), +}; + +static const int pon_pins[] = { 28, 29, 30, 31, 32, 33 }; +static const int pon_tod_1pps_pins[] = { 21 }; +static const int gsw_tod_1pps_pins[] = { 21 }; +static const int sipo_pins[] = { 13, 38 }; +static const int sipo_rclk_pins[] = { 13, 30, 38 }; +static const int mdio_pins[] = { 20, 21 }; +static const int uart2_pins[] = { 20, 21 }; +static const int npu_uart_pins[] = { 13, 38 }; +static const int i2c0_pins[] = { 2, 3 }; +static const int i2c1_pins[] = { 14, 15 }; +static const int jtag_udi_pins[] = { 34, 35, 36, 37, 38 }; +static const int jtag_dfd_pins[] = { 34, 35, 36, 37, 38 }; +static const int i2s_pins[] = { 16, 17, 18, 19 }; +static const int pcm1_pins[] = { 24, 25, 26, 27 }; +static const int pcm2_pins[] = { 16, 17, 18, 19 }; +static const int spi_pins[] = { 4, 5, 6, 7 }; +static const int spi_quad_pins[] = { 14, 15 }; +static const int spi_cs1_pins[] = { 21 }; +static const int pcm_spi_pins[] = { 16, 17, 18, 19, 24, 25, 26, 27 }; +static const int pcm_spi_int_pins[] = { 15 }; +static const int pcm_spi_rst_pins[] = { 14 }; +static const int pcm_spi_cs1_pins[] = { 22 }; +static const int pcm_spi_cs2_p128_pins[] = { 39 }; +static const int pcm_spi_cs2_p156_pins[] = { 39 }; +static const int pcm_spi_cs3_pins[] = { 20 }; +static const int pcm_spi_cs4_pins[] = { 23 }; +static const int gpio0_pins[] = { 12 }; +static const int gpio1_pins[] = { 13 }; +static const int gpio2_pins[] = { 14 }; +static const int gpio3_pins[] = { 15 }; +static const int gpio4_pins[] = { 16 }; +static const int gpio5_pins[] = { 17 }; +static const int gpio6_pins[] = { 18 }; +static const int gpio7_pins[] = { 19 }; +static const int gpio8_pins[] = { 20 }; +static const int gpio9_pins[] = { 21 }; +static const int gpio10_pins[] = { 22 }; +static const int gpio11_pins[] = { 23 }; +static const int gpio12_pins[] = { 24 }; +static const int gpio13_pins[] = { 25 }; +static const int gpio14_pins[] = { 26 }; +static const int gpio15_pins[] = { 27 }; +static const int gpio16_pins[] = { 28 }; +static const int gpio17_pins[] = { 29 }; +static const int gpio18_pins[] = { 30 }; +static const int gpio19_pins[] = { 31 }; +static const int gpio20_pins[] = { 32 }; +static const int gpio21_pins[] = { 33 }; +static const int gpio22_pins[] = { 34 }; +static const int gpio23_pins[] = { 35 }; +static const int gpio24_pins[] = { 36 }; +static const int gpio25_pins[] = { 37 }; +static const int gpio26_pins[] = { 38 }; +static const int gpio27_pins[] = { 39 }; +static const int gpio28_pins[] = { 40 }; +static const int gpio29_pins[] = { 41 }; +static const int pcie_reset0_pins[] = { 40 }; +static const int pcie_reset1_pins[] = { 41 }; + +static const struct pingroup pinctrl_groups[] = { + PINCTRL_PIN_GROUP("pon", pon), + PINCTRL_PIN_GROUP("pon_tod_1pps", pon_tod_1pps), + PINCTRL_PIN_GROUP("gsw_tod_1pps", gsw_tod_1pps), + PINCTRL_PIN_GROUP("sipo", sipo), + PINCTRL_PIN_GROUP("sipo_rclk", sipo_rclk), + PINCTRL_PIN_GROUP("mdio", mdio), + PINCTRL_PIN_GROUP("uart2", uart2), + PINCTRL_PIN_GROUP("npu_uart", npu_uart), + PINCTRL_PIN_GROUP("i2c0", i2c0), + PINCTRL_PIN_GROUP("i2c1", i2c1), + PINCTRL_PIN_GROUP("jtag_udi", jtag_udi), + PINCTRL_PIN_GROUP("jtag_dfd", jtag_dfd), + PINCTRL_PIN_GROUP("i2s", i2s), + PINCTRL_PIN_GROUP("pcm1", pcm1), + PINCTRL_PIN_GROUP("pcm2", pcm2), + PINCTRL_PIN_GROUP("spi", spi), + PINCTRL_PIN_GROUP("spi_quad", spi_quad), + PINCTRL_PIN_GROUP("spi_cs1", spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi", pcm_spi), + PINCTRL_PIN_GROUP("pcm_spi_int", pcm_spi_int), + PINCTRL_PIN_GROUP("pcm_spi_rst", pcm_spi_rst), + PINCTRL_PIN_GROUP("pcm_spi_cs1", pcm_spi_cs1), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", pcm_spi_cs2_p128), + PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", pcm_spi_cs2_p156), + PINCTRL_PIN_GROUP("pcm_spi_cs3", pcm_spi_cs3), + PINCTRL_PIN_GROUP("pcm_spi_cs4", pcm_spi_cs4), + PINCTRL_PIN_GROUP("gpio0", gpio0), + PINCTRL_PIN_GROUP("gpio1", gpio1), + PINCTRL_PIN_GROUP("gpio2", gpio2), + PINCTRL_PIN_GROUP("gpio3", gpio3), + PINCTRL_PIN_GROUP("gpio4", gpio4), + PINCTRL_PIN_GROUP("gpio5", gpio5), + PINCTRL_PIN_GROUP("gpio6", gpio6), + PINCTRL_PIN_GROUP("gpio7", gpio7), + PINCTRL_PIN_GROUP("gpio8", gpio8), + PINCTRL_PIN_GROUP("gpio9", gpio9), + PINCTRL_PIN_GROUP("gpio10", gpio10), + PINCTRL_PIN_GROUP("gpio11", gpio11), + PINCTRL_PIN_GROUP("gpio12", gpio12), + PINCTRL_PIN_GROUP("gpio13", gpio13), + PINCTRL_PIN_GROUP("gpio14", gpio14), + PINCTRL_PIN_GROUP("gpio15", gpio15), + PINCTRL_PIN_GROUP("gpio16", gpio16), + PINCTRL_PIN_GROUP("gpio17", gpio17), + PINCTRL_PIN_GROUP("gpio18", gpio18), + PINCTRL_PIN_GROUP("gpio19", gpio19), + PINCTRL_PIN_GROUP("gpio20", gpio20), + PINCTRL_PIN_GROUP("gpio21", gpio21), + PINCTRL_PIN_GROUP("gpio22", gpio22), + PINCTRL_PIN_GROUP("gpio23", gpio23), + PINCTRL_PIN_GROUP("gpio24", gpio24), + PINCTRL_PIN_GROUP("gpio25", gpio25), + PINCTRL_PIN_GROUP("gpio26", gpio26), + PINCTRL_PIN_GROUP("gpio27", gpio27), + PINCTRL_PIN_GROUP("gpio28", gpio28), + PINCTRL_PIN_GROUP("gpio29", gpio29), + PINCTRL_PIN_GROUP("pcie_reset0", pcie_reset0), + PINCTRL_PIN_GROUP("pcie_reset1", pcie_reset1), +}; + +static const char *const pon_groups[] = { "pon" }; +static const char *const tod_1pps_groups[] = { + "pon_tod_1pps", "gsw_tod_1pps" +}; +static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; +static const char *const mdio_groups[] = { "mdio" }; +static const char *const uart_groups[] = { "uart2", "npu_uart" }; +static const char *const i2c_groups[] = { "i2c1" }; +static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; +static const char *const pcm_groups[] = { "pcm1", "pcm2" }; +static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; +static const char *const pcm_spi_groups[] = { + "pcm_spi", "pcm_spi_int", "pcm_spi_rst", "pcm_spi_cs1", + "pcm_spi_cs2_p156", "pcm_spi_cs2_p128", "pcm_spi_cs3", "pcm_spi_cs4" +}; +static const char *const i2s_groups[] = { "i2s" }; +static const char *const gpio_groups[] = { "gpio28", "gpio29" }; +static const char *const pcie_reset_groups[] = { + "pcie_reset0", "pcie_reset1" +}; +static const char *const pwm_groups[] = { + "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", + "gpio6", "gpio7", "gpio8", "gpio9", "gpio10", "gpio11", + "gpio12", "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", + "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", "gpio23", + "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29" +}; +static const char *const phy1_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy2_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy3_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy4_led0_groups[] = { + "gpio22", "gpio23", "gpio24", "gpio25" +}; +static const char *const phy1_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy2_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy3_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; +static const char *const phy4_led1_groups[] = { + "gpio7", "gpio6", "gpio5", "gpio4" +}; + +static const struct airoha_pinctrl_func_group pon_func_group[] = { + { + .name = "pon", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PON_MODE_MASK, + GPIO_PON_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { + { + .name = "pon_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + PON_TOD_1PPS_MODE_MASK, + PON_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "gsw_tod_1pps", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GSW_TOD_1PPS_MODE_MASK, + GSW_TOD_1PPS_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group sipo_func_group[] = { + { + .name = "sipo", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "sipo_rclk", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, + GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group mdio_func_group[] = { + { + .name = "mdio", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_SGMII_MDIO_MODE_MASK, + GPIO_SGMII_MDIO_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group uart_func_group[] = { + { + .name = "uart2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_UART2_MODE_MASK, + GPIO_UART2_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "npu_uart", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + NPU_UART_EN_MASK, + NPU_UART_EN_MASK + }, + .regmap_size = 1, + } +}; + +static const struct airoha_pinctrl_func_group i2c_func_group[] = { + { + .name = "i2c1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_2ND_I2C_MODE_MASK, + GPIO_2ND_I2C_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group jtag_func_group[] = { + { + .name = "jtag_udi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_UDI_EN_MASK, + JTAG_UDI_EN_MASK + }, + .regmap_size = 1, + }, { + .name = "jtag_dfd", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_NPU_UART_EN, + JTAG_DFD_EN_MASK, + JTAG_DFD_EN_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_func_group[] = { + { + .name = "pcm1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM1_MODE_MASK, + GPIO_PCM1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm2", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM2_MODE_MASK, + GPIO_PCM2_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group spi_func_group[] = { + { + .name = "spi_quad", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_QUAD_MODE_MASK, + GPIO_SPI_QUAD_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_SPI_CS1_MODE_MASK, + GPIO_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { + { + .name = "pcm_spi", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_MODE_MASK, + GPIO_PCM_SPI_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_int", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_INT_MODE_MASK, + GPIO_PCM_INT_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_rst", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_RESET_MODE_MASK, + GPIO_PCM_RESET_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS1_MODE_MASK, + GPIO_PCM_SPI_CS1_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p128", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P128_MASK, + GPIO_PCM_SPI_CS2_MODE_P128_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs2_p156", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS2_MODE_P156_MASK, + GPIO_PCM_SPI_CS2_MODE_P156_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs3", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS3_MODE_MASK, + GPIO_PCM_SPI_CS3_MODE_MASK + }, + .regmap_size = 1, + }, { + .name = "pcm_spi_cs4", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_SPI_CS1_MODE, + GPIO_PCM_SPI_CS4_MODE_MASK, + GPIO_PCM_SPI_CS4_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group i2s_func_group[] = { + { + .name = "i2s", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_2ND_I2C_MODE, + GPIO_I2S_MODE_MASK, + GPIO_I2S_MODE_MASK + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group gpio_func_group[] = { + AIROHA_PINCTRL_GPIO_EXT("gpio28", GPIO28_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_GPIO_EXT("gpio29", GPIO29_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), +}; + +static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { + { + .name = "pcie_reset0", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET0_MASK, + 0 + }, + .regmap_size = 1, + }, { + .name = "pcie_reset1", + .regmap[0] = { + AIROHA_FUNC_MUX, + REG_GPIO_PON_MODE, + GPIO_PCIE_RESET1_MASK, + 0 + }, + .regmap_size = 1, + }, +}; + +static const struct airoha_pinctrl_func_group pwm_func_group[] = { + AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio28", GPIO28_FLASH_MODE_CFG, + GPIO_PCIE_RESET0_MASK), + AIROHA_PINCTRL_PWM_EXT_SEC("gpio29", GPIO29_FLASH_MODE_CFG, + GPIO_PCIE_RESET1_MASK), +}; + +static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { + AIROHA_PINCTRL_PHY_LED0("gpio22", GPIO_LAN0_LED0_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio23", GPIO_LAN1_LED0_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio24", GPIO_LAN2_LED0_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED0("gpio25", GPIO_LAN3_LED0_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), +}; + +static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), +}; + +static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), +}; + +static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { + AIROHA_PINCTRL_PHY_LED1("gpio7", GPIO_LAN0_LED1_MODE_MASK, + LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio6", GPIO_LAN1_LED1_MODE_MASK, + LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio5", GPIO_LAN2_LED1_MODE_MASK, + LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), + AIROHA_PINCTRL_PHY_LED1("gpio4", GPIO_LAN3_LED1_MODE_MASK, + LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), +}; + +static const struct airoha_pinctrl_func pinctrl_funcs[] = { + PINCTRL_FUNC_DESC("pon", pon), + PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), + PINCTRL_FUNC_DESC("sipo", sipo), + PINCTRL_FUNC_DESC("mdio", mdio), + PINCTRL_FUNC_DESC("uart", uart), + PINCTRL_FUNC_DESC("i2c", i2c), + PINCTRL_FUNC_DESC("jtag", jtag), + PINCTRL_FUNC_DESC("pcm", pcm), + PINCTRL_FUNC_DESC("spi", spi), + PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), + PINCTRL_FUNC_DESC("i2s", i2s), + PINCTRL_FUNC_DESC("gpio", gpio), + PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), + PINCTRL_FUNC_DESC("pwm", pwm), + PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), + PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), + PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), + PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), + PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), + PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), + PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), + PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), +}; + +static const struct airoha_pinctrl_conf pinctrl_pullup_conf[] = { + PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(27)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(28)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(29)), +}; + +static const struct airoha_pinctrl_conf pinctrl_pulldown_conf[] = { + PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(27)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(28)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(29)), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e2_conf[] = { + PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(27)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(28)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(29)), +}; + +static const struct airoha_pinctrl_conf pinctrl_drive_e4_conf[] = { + PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(0)), + PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(1)), + PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(2)), + PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(3)), + PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(4)), + PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(5)), + PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(6)), + PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(7)), + PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(8)), + PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(9)), + PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(10)), + PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(11)), + PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(12)), + PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(13)), + PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(14)), + PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(15)), + PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(16)), + PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(17)), + PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(18)), + PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(19)), + PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(20)), + PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(21)), + PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(22)), + PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(23)), + PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(24)), + PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(25)), + PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(26)), + PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(27)), + PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(28)), + PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(29)), +}; + +static const struct airoha_pinctrl_match_data pinctrl_match_data = { + .gpio_offs = 12, + .gpio_pin_cnt = 30, + .chip_scu_compatible = "airoha,en7523-chip-scu", + .pins = pinctrl_pins, + .num_pins = ARRAY_SIZE(pinctrl_pins), + .grps = pinctrl_groups, + .num_grps = ARRAY_SIZE(pinctrl_groups), + .funcs = pinctrl_funcs, + .num_funcs = ARRAY_SIZE(pinctrl_funcs), + .confs_info = { + [AIROHA_PINCTRL_CONFS_PULLUP] = { + .confs = pinctrl_pullup_conf, + .num_confs = ARRAY_SIZE(pinctrl_pullup_conf), + }, + [AIROHA_PINCTRL_CONFS_PULLDOWN] = { + .confs = pinctrl_pulldown_conf, + .num_confs = ARRAY_SIZE(pinctrl_pulldown_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { + .confs = pinctrl_drive_e2_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e2_conf), + }, + [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { + .confs = pinctrl_drive_e4_conf, + .num_confs = ARRAY_SIZE(pinctrl_drive_e4_conf), + }, + }, +}; + +static const struct udevice_id pinctrl_of_match[] = { + { .compatible = "airoha,en7523-pinctrl", + .data = (uintptr_t)&pinctrl_match_data }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(airoha_en7523_pinctrl) = { + .name = "airoha-en7523-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(pinctrl_of_match), + .probe = airoha_pinctrl_probe, + .bind = airoha_pinctrl_bind, + .priv_auto = sizeof(struct airoha_pinctrl), + .ops = &airoha_pinctrl_ops, +}; diff --git a/drivers/pinctrl/broadcom/Kconfig b/drivers/pinctrl/broadcom/Kconfig index b01b725583a..d7cf3855928 100644 --- a/drivers/pinctrl/broadcom/Kconfig +++ b/drivers/pinctrl/broadcom/Kconfig @@ -3,13 +3,13 @@ config PINCTRL_BCM283X default y bool "Broadcom 283x family pin control driver" help - Support pin multiplexing and pin configuration control on - Broadcom's 283x family of SoCs. + Support pin multiplexing and pin configuration control on + Broadcom's 283x family of SoCs. config PINCTRL_BCM6838 depends on ARCH_BMIPS && PINCTRL_FULL && OF_CONTROL default y bool "Broadcom 6838 family pin control driver" help - Support pin multiplexing and pin configuration control on - Broadcom's 6838 family of SoCs. + Support pin multiplexing and pin configuration control on + Broadcom's 6838 family of SoCs. diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig index cf72a7df62c..5a90d74a9e1 100644 --- a/drivers/pinctrl/mediatek/Kconfig +++ b/drivers/pinctrl/mediatek/Kconfig @@ -59,7 +59,7 @@ config PINCTRL_MT8516 select PINCTRL_MTK config PINCTRL_MT8518 - bool "MT8518 SoC pinctrl driver" + bool "MT8518 SoC pinctrl driver" select PINCTRL_MTK endif diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig index 567c93f404c..285787c4467 100644 --- a/drivers/pinctrl/mscc/Kconfig +++ b/drivers/pinctrl/mscc/Kconfig @@ -10,8 +10,8 @@ config PINCTRL_MSCC_OCELOT default y bool "Microsemi ocelot family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi ocelot SoCs. + Support pin multiplexing and pin configuration control on + Microsemi ocelot SoCs. config PINCTRL_MSCC_LUTON depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL @@ -19,8 +19,8 @@ config PINCTRL_MSCC_LUTON default y bool "Microsemi luton family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi luton SoCs. + Support pin multiplexing and pin configuration control on + Microsemi luton SoCs. config PINCTRL_MSCC_JR2 depends on SOC_JR2 && PINCTRL_FULL && OF_CONTROL @@ -28,8 +28,8 @@ config PINCTRL_MSCC_JR2 default y bool "Microsemi jr2 family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi jr2 SoCs. + Support pin multiplexing and pin configuration control on + Microsemi jr2 SoCs. config PINCTRL_MSCC_SERVALT depends on SOC_SERVALT && PINCTRL_FULL && OF_CONTROL @@ -37,8 +37,8 @@ config PINCTRL_MSCC_SERVALT default y bool "Microsemi servalt family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi servalt SoCs. + Support pin multiplexing and pin configuration control on + Microsemi servalt SoCs. config PINCTRL_MSCC_SERVAL depends on SOC_SERVAL && PINCTRL_FULL && OF_CONTROL @@ -46,6 +46,6 @@ config PINCTRL_MSCC_SERVAL default y bool "Microsemi serval family pin control driver" help - Support pin multiplexing and pin configuration control on - Microsemi serval SoCs. + Support pin multiplexing and pin configuration control on + Microsemi serval SoCs. diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig index 10ba440f246..72b97a7935d 100644 --- a/drivers/pinctrl/mvebu/Kconfig +++ b/drivers/pinctrl/mvebu/Kconfig @@ -4,22 +4,22 @@ config PINCTRL_ARMADA_38X depends on ARMADA_38X && PINCTRL_FULL bool "Armada 38x pin control driver" help - Support pin multiplexing and pin configuration control on - Marvell's Armada-38x SoC. + Support pin multiplexing and pin configuration control on + Marvell's Armada-38x SoC. config PINCTRL_ARMADA_37XX depends on ARMADA_3700 && PINCTRL_FULL select DEVRES bool "Armada 37xx pin control driver" help - Support pin multiplexing and pin configuration control on - Marvell's Armada-37xx SoC. + Support pin multiplexing and pin configuration control on + Marvell's Armada-37xx SoC. config PINCTRL_ARMADA_8K depends on (ARMADA_8K || ALLEYCAT_5) && PINCTRL_FULL bool "Armada 7k/8k pin control driver" help - Support pin multiplexing and pin configuration control on - Marvell's Armada-8K SoC. + Support pin multiplexing and pin configuration control on + Marvell's Armada-8K SoC. endif diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index 43100d5d981..0bea461fcc3 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -79,12 +79,12 @@ config PINCTRL_QCOM_QCS404 as well as the associated GPIO driver. config PINCTRL_QCOM_QCS615 - bool "Qualcomm QCS615 Pinctrl" + bool "Qualcomm QCS615 Pinctrl" default y if PINCTRL_QCOM_GENERIC - select PINCTRL_QCOM - help - Say Y here to enable support for pinctrl on the Snapdragon QCS615 SoC, - as well as the associated GPIO driver. + select PINCTRL_QCOM + help + Say Y here to enable support for pinctrl on the Snapdragon QCS615 SoC, + as well as the associated GPIO driver. config PINCTRL_QCOM_SA8775P bool "Qualcomm SA8775P Pinctrl" diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig index 1b06d8a66c7..66c389d073b 100644 --- a/drivers/power/Kconfig +++ b/drivers/power/Kconfig @@ -1,7 +1,7 @@ menuconfig POWER - bool "Power" - default y - help + bool "Power" + default y + help Enable support for power control in U-Boot. This includes support for PMICs (Power-management Integrated Circuits) and some of the features provided by PMICs. In particular, voltage regulators can @@ -63,98 +63,98 @@ choice config SUNXI_NO_PMIC bool "board without a pmic" - ---help--- - Select this for boards which do not use a PMIC. + help + Select this for boards which do not use a PMIC. config AXP152_POWER bool "axp152 pmic support" depends on MACH_SUN5I select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp152 pmic found on most - A10s boards. + help + Select this to enable support for the axp152 pmic found on most + A10s boards. config AXP209_POWER bool "axp209 pmic support" depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3S select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp209 pmic found on most - A10, A13 and A20 boards. + help + Select this to enable support for the axp209 pmic found on most + A10, A13 and A20 boards. config AXP221_POWER bool "axp221 / axp223 pmic support" depends on MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_R40 select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp221/axp223 pmic found on most - A23 and A31 boards. + help + Select this to enable support for the axp221/axp223 pmic found on most + A23 and A31 boards. config AXP305_POWER bool "axp305 pmic support" depends on MACH_SUN50I_H616 select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the axp305 pmic found on most - H616 boards. + help + Select this to enable support for the axp305 pmic found on most + H616 boards. config AXP313_POWER bool "axp313 pmic support" depends on MACH_SUN50I_H616 select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the AXP313 PMIC found on some - H616 boards. + help + Select this to enable support for the AXP313 PMIC found on some + H616 boards. config AXP717_POWER bool "axp717 pmic support" select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the AXP717 PMIC found on some boards. + help + Select this to enable support for the AXP717 PMIC found on some boards. config AXP803_POWER bool "AXP803 PMIC support" select AXP_PMIC_BUS - ---help--- - Select this to enable support for the AXP803 PMIC found on some boards. + help + Select this to enable support for the AXP803 PMIC found on some boards. config AXP809_POWER bool "axp809 pmic support" depends on MACH_SUN9I select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Say y here to enable support for the axp809 pmic found on A80 boards. + help + Say y here to enable support for the axp809 pmic found on A80 boards. config AXP818_POWER bool "axp818 pmic support" depends on MACH_SUN8I_A83T select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Say y here to enable support for the axp818 pmic found on - A83T dev board. + help + Say y here to enable support for the axp818 pmic found on + A83T dev board. config AXP318W_POWER bool "axp318w pmic support" select AXP_PMIC_BUS select CMD_POWEROFF - ---help--- - Select this to enable support for the AXP318W PMIC found on some - A733 boards. + help + Select this to enable support for the AXP318W PMIC found on some + A733 boards. config SY8106A_POWER bool "SY8106A pmic support" depends on MACH_SUNXI_H3_H5 - ---help--- - Select this to enable support for the SY8106A pmic found on some - H3 boards. + help + Select this to enable support for the SY8106A pmic found on some + H3 boards. endchoice @@ -166,22 +166,22 @@ config AXP_I2C_ADDRESS default 0x36 if AXP318W_POWER default 0x30 if AXP152_POWER default 0x34 - ---help--- - I2C address of the AXP PMIC, used for the SPL only. + help + I2C address of the AXP PMIC, used for the SPL only. config AXP_DCDC1_VOLT int "axp pmic dcdc1 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER default 3300 if AXP818_POWER || MACH_SUN8I_R40 || AXP803_POWER default 3000 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to - disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for - generic 3.3V IO voltage for external devices like the lcd-panal and - sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to - save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T - dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally - powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG. + help + Set the voltage (mV) to program the axp pmic dcdc1 at, set to 0 to + disable dcdc1. On A23 / A31 / A33 (axp221) boards dcdc1 is used for + generic 3.3V IO voltage for external devices like the lcd-panal and + sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to + save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T + dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally + powers some of the pingroups, NAND/eMMC, SD/MMC, and USB OTG. config AXP_DCDC2_VOLT int "axp pmic dcdc2 voltage" @@ -194,16 +194,16 @@ config AXP_DCDC2_VOLT default 1200 if MACH_SUN6I default 1100 if MACH_SUN8I default 0 if MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to - disable dcdc2. - On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V. - On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V. - On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V. - On A80 boards dcdc2 powers the GPU and can be left off. - On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. - On R40 boards dcdc2 is VDD-CPU and should be 1.1V - On boards using the AXP313 or AXP717 it's often VDD-CPU. + help + Set the voltage (mV) to program the axp pmic dcdc2 at, set to 0 to + disable dcdc2. + On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V. + On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V. + On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V. + On A80 boards dcdc2 powers the GPU and can be left off. + On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V. + On R40 boards dcdc2 is VDD-CPU and should be 1.1V + On boards using the AXP313 or AXP717 it's often VDD-CPU. config AXP_DCDC3_VOLT int "axp pmic dcdc3 voltage" @@ -214,18 +214,18 @@ config AXP_DCDC3_VOLT default 1100 if AXP313_POWER default 1100 if MACH_SUN8I_R40 default 1200 if MACH_SUN6I || MACH_SUN8I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to - disable dcdc3. - On A10(s) / A13 / A20 boards with an axp209 dcdc3 is VDD-INT-DLL and - should be 1.25V. - On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V. - On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. - On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. - On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. - On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V. - On boards using the AXP313 or AXP717 it's often VDD-DRAM and should - be 1.1V for LPDDR4. + help + Set the voltage (mV) to program the axp pmic dcdc3 at, set to 0 to + disable dcdc3. + On A10(s) / A13 / A20 boards with an axp209 dcdc3 is VDD-INT-DLL and + should be 1.25V. + On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V. + On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V. + On A80 boards dcdc3 is used for VDD-CPUA(cluster 0) and should be 0.9V. + On A83T boards dcdc3 is used for VDD-CPUB(cluster 1) and should be 0.9V. + On R40 boards dcdc3 is VDD-SYS and VDD-GPU and should be 1.1V. + On boards using the AXP313 or AXP717 it's often VDD-DRAM and should + be 1.1V for LPDDR4. config AXP_DCDC4_VOLT int "axp pmic dcdc4 voltage" @@ -235,25 +235,25 @@ config AXP_DCDC4_VOLT default 0 if MACH_SUN8I default 900 if MACH_SUN9I default 1500 if AXP305_POWER - ---help--- - Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to - disable dcdc4. - On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V. - On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V. - On A23 / A33 boards dcdc4 is unused and should be disabled. - On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V. - On A83T boards dcdc4 is used for VDD-GPU. - On H616 boards dcdcd is used for VCC-DRAM. + help + Set the voltage (mV) to program the axp pmic dcdc4 at, set to 0 to + disable dcdc4. + On A10s boards with an axp152 dcdc4 is VDD-INT-DLL and should be 1.25V. + On A31 boards dcdc4 is used for VDD-SYS and should be 1.2V. + On A23 / A33 boards dcdc4 is unused and should be disabled. + On A80 boards dcdc4 powers VDD-SYS, HDMI, USB OTG and should be 0.9V. + On A83T boards dcdc4 is used for VDD-GPU. + On H616 boards dcdcd is used for VCC-DRAM. config AXP_DCDC5_VOLT int "axp pmic dcdc5 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER || AXP803_POWER default 1500 if MACH_SUN6I || MACH_SUN8I || MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to - disable dcdc5. - On A23 / A31 / A33 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and - should be 1.5V, 1.35V if DDR3L is used. + help + Set the voltage (mV) to program the axp pmic dcdc5 at, set to 0 to + disable dcdc5. + On A23 / A31 / A33 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and + should be 1.5V, 1.35V if DDR3L is used. config AXP_ALDO1_VOLT int "axp pmic (a)ldo1 voltage" @@ -261,14 +261,14 @@ config AXP_ALDO1_VOLT default 0 if MACH_SUN6I || MACH_SUN8I_R40 default 1800 if MACH_SUN8I_A83T default 3000 if MACH_SUN8I || MACH_SUN9I - ---help--- - Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to - disable aldo1. - On A31 boards aldo1 is often used to power the wifi module. - On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V. - On A80 boards aldo1 powers the USB hosts and should be 3.0V. - On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and - should be 1.8V. + help + Set the voltage (mV) to program the axp pmic aldo1 at, set to 0 to + disable aldo1. + On A31 boards aldo1 is often used to power the wifi module. + On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V. + On A80 boards aldo1 powers the USB hosts and should be 3.0V. + On A83T / H8 boards aldo1 is used for MIPI CSI, DSI, HDMI, EFUSE, and + should be 1.8V. config AXP_ALDO2_VOLT int "axp pmic (a)ldo2 voltage" @@ -277,188 +277,188 @@ config AXP_ALDO2_VOLT default 0 if MACH_SUN6I || MACH_SUN9I default 1800 if MACH_SUN8I_A83T default 2500 if MACH_SUN8I - ---help--- - Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to - disable aldo2. - On A10(s) / A13 / A20 boards aldo2 is AVCC and should be 3.0V. - On A31 boards aldo2 is typically unused and should be disabled. - On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V. - On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V. - On A80 boards aldo2 powers PB pingroup and camera IO and can be left off. - On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC, - LPDDR2, and the codec. It should be 1.8V. + help + Set the voltage (mV) to program the axp pmic aldo2 at, set to 0 to + disable aldo2. + On A10(s) / A13 / A20 boards aldo2 is AVCC and should be 3.0V. + On A31 boards aldo2 is typically unused and should be disabled. + On A31 boards aldo2 may be used for LPDDR2 then it should be 1.8V. + On A23 / A33 boards aldo2 is used for VDD-DLL and should be 2.5V. + On A80 boards aldo2 powers PB pingroup and camera IO and can be left off. + On A83T / H8 boards aldo2 powers VDD-DLL, VCC18-PLL, CPVDD, VDD18-ADC, + LPDDR2, and the codec. It should be 1.8V. config AXP_ALDO3_VOLT int "axp pmic (a)ldo3 voltage" depends on AXP209_POWER || AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 if AXP209_POWER || MACH_SUN9I default 3000 if MACH_SUN6I || MACH_SUN8I - ---help--- - Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to - disable aldo3. - On A10(s) / A13 / A20 boards aldo3 should be 2.8V. - On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should - be 3.0V. - On A80 boards aldo3 is normally not used. - On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be - 3.0V. + help + Set the voltage (mV) to program the axp pmic aldo3 at, set to 0 to + disable aldo3. + On A10(s) / A13 / A20 boards aldo3 should be 2.8V. + On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should + be 3.0V. + On A80 boards aldo3 is normally not used. + On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be + 3.0V. choice prompt "axp pmic (a)ldo3 voltage rate control" depends on AXP209_POWER default AXP_ALDO3_VOLT_SLOPE_NONE - ---help--- - The AXP can slowly ramp up voltage to reduce the inrush current when - changing voltages. - Note, this does not apply when enabling/disabling LDO3. See - "axp pmic (a)ldo3 inrush quirk" below to enable a slew rate to limit - inrush current on broken board designs. + help + The AXP can slowly ramp up voltage to reduce the inrush current when + changing voltages. + Note, this does not apply when enabling/disabling LDO3. See + "axp pmic (a)ldo3 inrush quirk" below to enable a slew rate to limit + inrush current on broken board designs. config AXP_ALDO3_VOLT_SLOPE_NONE bool "No voltage slope" - ---help--- - Tries to reach the next voltage setting near instantaneously. Measurements - indicate that this is about 0.0167 V/uS. + help + Tries to reach the next voltage setting near instantaneously. Measurements + indicate that this is about 0.0167 V/uS. config AXP_ALDO3_VOLT_SLOPE_16 bool "1.6 mV per uS" - ---help--- - Increases the voltage by 1.6 mV per uS until the final voltage has - been reached. Note that the scaling is in 25 mV steps and thus - the slew rate in reality is about 25 mV/31.250 uS. + help + Increases the voltage by 1.6 mV per uS until the final voltage has + been reached. Note that the scaling is in 25 mV steps and thus + the slew rate in reality is about 25 mV/31.250 uS. config AXP_ALDO3_VOLT_SLOPE_08 bool "0.8 mV per uS" - ---help--- - Increases the voltage by 0.8 mV per uS until the final voltage has - been reached. Note that the scaling is in 25 mV steps however and thus - the slew rate in reality is about 25 mV/15.625 uS. - This is the slowest supported rate. + help + Increases the voltage by 0.8 mV per uS until the final voltage has + been reached. Note that the scaling is in 25 mV steps however and thus + the slew rate in reality is about 25 mV/15.625 uS. + This is the slowest supported rate. endchoice config AXP_ALDO3_INRUSH_QUIRK bool "axp pmic (a)ldo3 inrush quirk" depends on AXP209_POWER - ---help--- - The reference design denotes a value of 4.7 uF for the output capacitor - of LDO3. Some boards have too high capacitance causing an inrush current - and resulting an AXP209 shutdown. + help + The reference design denotes a value of 4.7 uF for the output capacitor + of LDO3. Some boards have too high capacitance causing an inrush current + and resulting an AXP209 shutdown. config AXP_ALDO4_VOLT int "axp pmic (a)ldo4 voltage" depends on AXP209_POWER default 0 if AXP209_POWER - ---help--- - Set the voltage (mV) to program the axp pmic aldo4 at, set to 0 to - disable aldo4. - On A10(s) / A13 / A20 boards aldo4 should be 2.8V. + help + Set the voltage (mV) to program the axp pmic aldo4 at, set to 0 to + disable aldo4. + On A10(s) / A13 / A20 boards aldo4 should be 2.8V. config AXP_DLDO1_VOLT int "axp pmic dldo1 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to - disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used - to power the ethernet phy. On A23, A33 and A80 boards this is often - used to power the wifi. + help + Set the voltage (mV) to program the axp pmic dldo1 at, set to 0 to + disable dldo1. On sun6i (A31) boards with ethernet dldo1 is often used + to power the ethernet phy. On A23, A33 and A80 boards this is often + used to power the wifi. config AXP_DLDO2_VOLT int "axp pmic dldo2 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 3000 if MACH_SUN9I default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to - disable dldo2. - On A80 boards dldo2 normally powers the PL pins and should be 3.0V. + help + Set the voltage (mV) to program the axp pmic dldo2 at, set to 0 to + disable dldo2. + On A80 boards dldo2 normally powers the PL pins and should be 3.0V. config AXP_DLDO3_VOLT int "axp pmic dldo3 voltage" depends on AXP221_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to - disable dldo3. + help + Set the voltage (mV) to program the axp pmic dldo3 at, set to 0 to + disable dldo3. config AXP_DLDO4_VOLT int "axp pmic dldo4 voltage" depends on AXP221_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to - disable dldo4. + help + Set the voltage (mV) to program the axp pmic dldo4 at, set to 0 to + disable dldo4. config AXP_ELDO1_VOLT int "axp pmic eldo1 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to - disable eldo1. + help + Set the voltage (mV) to program the axp pmic eldo1 at, set to 0 to + disable eldo1. config AXP_ELDO2_VOLT int "axp pmic eldo2 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to - disable eldo2. + help + Set the voltage (mV) to program the axp pmic eldo2 at, set to 0 to + disable eldo2. config AXP_ELDO3_VOLT int "axp pmic eldo3 voltage" depends on AXP221_POWER || AXP809_POWER || AXP818_POWER default 3000 if MACH_SUN9I default 0 - ---help--- - Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to - disable eldo3. On some A31(s) tablets it might be used to supply - 1.2V for the SSD2828 chip (converter of parallel LCD interface - into MIPI DSI). - On A80 boards it powers the PM pingroup and should be 3.0V. + help + Set the voltage (mV) to program the axp pmic eldo3 at, set to 0 to + disable eldo3. On some A31(s) tablets it might be used to supply + 1.2V for the SSD2828 chip (converter of parallel LCD interface + into MIPI DSI). + On A80 boards it powers the PM pingroup and should be 3.0V. config AXP_FLDO1_VOLT int "axp pmic fldo1 voltage" depends on AXP818_POWER default 0 if MACH_SUN8I_A83T - ---help--- - Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to - disable fldo1. - On A83T / H8 boards fldo1 is VCC-HSIC and should be 1.2V if HSIC is - used. + help + Set the voltage (mV) to program the axp pmic fldo1 at, set to 0 to + disable fldo1. + On A83T / H8 boards fldo1 is VCC-HSIC and should be 1.2V if HSIC is + used. config AXP_FLDO2_VOLT int "axp pmic fldo2 voltage" depends on AXP818_POWER default 900 if MACH_SUN8I_A83T - ---help--- - Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to - disable fldo2. - On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V. + help + Set the voltage (mV) to program the axp pmic fldo2 at, set to 0 to + disable fldo2. + On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V. config AXP_FLDO3_VOLT int "axp pmic fldo3 voltage" depends on AXP818_POWER default 0 - ---help--- - Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to - disable fldo3. + help + Set the voltage (mV) to program the axp pmic fldo3 at, set to 0 to + disable fldo3. config AXP_SW_ON bool "axp pmic sw on" depends on AXP809_POWER || AXP818_POWER - ---help--- - Enable to turn on axp pmic sw. + help + Enable to turn on axp pmic sw. config SY8106A_VOUT1_VOLT int "SY8106A pmic VOUT1 voltage" depends on SY8106A_POWER default 1200 - ---help--- - Set the voltage (mV) to program the SY8106A pmic VOUT1. This - is typically used to power the VDD-CPU and should be 1200mV. - Values can range from 680mV till 1950mV. + help + Set the voltage (mV) to program the SY8106A pmic VOUT1. This + is typically used to power the VDD-CPU and should be 1200mV. + Values can range from 680mV till 1950mV. config TPS6586X_POWER bool "Enable legacy driver for TI TPS6586x power management chip" @@ -467,9 +467,9 @@ config TWL4030_POWER depends on OMAP34XX bool "Enable driver for TI TWL4030 power management chip" imply CMD_POWEROFF - ---help--- - The TWL4030 in a combination audio CODEC/power management with - GPIO and it is commonly used with the OMAP3 family of processors + help + The TWL4030 in a combination audio CODEC/power management with + GPIO and it is commonly used with the OMAP3 family of processors config POWER_MT6323 bool "Poweroff driver for mediatek mt6323" diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 4112b777371..bb9c52155d2 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -35,10 +35,10 @@ config BCM6328_POWER_DOMAIN config IMX8_POWER_DOMAIN bool "Enable i.MX8 power domain driver" - depends on ARCH_IMX8 - help - Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC - requests to the SCU. + depends on ARCH_IMX8 + help + Enable support for manipulating NXP i.MX8 on-SoC power domains via IPC + requests to the SCU. config IMX8M_POWER_DOMAIN bool "Enable i.MX8M power domain driver" diff --git a/drivers/power/domain/renesas-r8a78000-power-domain.c b/drivers/power/domain/renesas-r8a78000-power-domain.c index d621373f90d..57b3b56b2d9 100644 --- a/drivers/power/domain/renesas-r8a78000-power-domain.c +++ b/drivers/power/domain/renesas-r8a78000-power-domain.c @@ -11,6 +11,7 @@ #include <dm/lists.h> #include <linux/io.h> #include <linux/iopoll.h> +#include <linux/bitfield.h> #include <power-domain-uclass.h> #include <reset-uclass.h> @@ -21,9 +22,6 @@ #include <dt-bindings/power/r8a78000-power-scmi.h> #include <dt-bindings/reset/r8a78000-reset-scmi.h> -#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1)) -#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - #define PKC_PROT_LOCK 0xa5a5a500 #define PKC_PROT_UNLOCK 0xa5a5a501 diff --git a/drivers/power/domain/scmi-power-domain.c b/drivers/power/domain/scmi-power-domain.c index 6dcc259ad8f..a369fe52f2f 100644 --- a/drivers/power/domain/scmi-power-domain.c +++ b/drivers/power/domain/scmi-power-domain.c @@ -165,15 +165,9 @@ static int scmi_power_domain_probe(struct udevice *dev) for (i = 0; i < priv->num_pwdoms; i++) { ret = scmi_pwd_attrs(dev, i, &priv->prop[i].attributes, &priv->prop[i].name); - if (ret) { + if (ret) dev_err(dev, "failed to get attributes pwd:%d (%d)\n", i, ret); - for (i--; i >= 0; i--) - free(priv->prop[i].name); - free(priv->prop); - - return ret; - } } return 0; diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig index 5bc14842e66..4bd9b4e1940 100644 --- a/drivers/power/pmic/Kconfig +++ b/drivers/power/pmic/Kconfig @@ -1,14 +1,14 @@ config DM_PMIC bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC)" depends on DM - ---help--- - This config enables the driver-model PMIC support. - UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. - For the multi-function PMIC devices, this can be used as parent I/O - device for each IC's interface. Then, each children uses its parent - for read/write. For detailed description, please refer to the files: - - 'drivers/power/pmic/pmic-uclass.c' - - 'include/power/pmic.h' + help + This config enables the driver-model PMIC support. + UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. + For the multi-function PMIC devices, this can be used as parent I/O + device for each IC's interface. Then, each children uses its parent + for read/write. For detailed description, please refer to the files: + - 'drivers/power/pmic/pmic-uclass.c' + - 'include/power/pmic.h' if DM_PMIC @@ -16,34 +16,34 @@ config SPL_DM_PMIC bool "Enable Driver Model for PMIC drivers (UCLASS_PMIC) in SPL" depends on SPL_DM default y - ---help--- - This config enables the driver-model PMIC support in SPL. - UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. - For the multi-function PMIC devices, this can be used as parent I/O - device for each IC's interface. Then, each children uses its parent - for read/write. For detailed description, please refer to the files: - - 'drivers/power/pmic/pmic-uclass.c' - - 'include/power/pmic.h' + help + This config enables the driver-model PMIC support in SPL. + UCLASS_PMIC - designed to provide an I/O interface for PMIC devices. + For the multi-function PMIC devices, this can be used as parent I/O + device for each IC's interface. Then, each children uses its parent + for read/write. For detailed description, please refer to the files: + - 'drivers/power/pmic/pmic-uclass.c' + - 'include/power/pmic.h' config PMIC_CHILDREN bool "Allow child devices for PMICs" default y - ---help--- - This allows PMICs to support child devices (such as regulators) in - SPL. This adds quite a bit of code so if you are not using this - feature you can turn it off. Most likely you should turn it on for - U-Boot proper. + help + This allows PMICs to support child devices (such as regulators) in + SPL. This adds quite a bit of code so if you are not using this + feature you can turn it off. Most likely you should turn it on for + U-Boot proper. config SPL_PMIC_CHILDREN bool "Allow child devices for PMICs in SPL" depends on SPL_DM_PMIC default y - ---help--- - This allows PMICs to support child devices (such as regulators) in - SPL. This adds quite a bit of code so if you are not using this - feature you can turn it off. In this case you may need a 'back door' - to call your regulator code (e.g. see rk8xx.c for direct functions - for use in SPL). + help + This allows PMICs to support child devices (such as regulators) in + SPL. This adds quite a bit of code so if you are not using this + feature you can turn it off. In this case you may need a 'back door' + to call your regulator code (e.g. see rk8xx.c for direct functions + for use in SPL). config PMIC_AB8500 bool "Enable driver for ST-Ericsson AB8500 PMIC via PRCMU" @@ -57,11 +57,11 @@ config PMIC_AB8500 config PMIC_ACT8846 bool "Enable support for the active-semi 8846 PMIC" depends on DM_I2C - ---help--- - This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout - regulators (LDOs). It also provides some GPIO, reset and battery - functions. It uses an I2C interface and is designed for use with - tablets and smartphones. + help + This PMIC includes 4 DC/DC step-down buck regulators and 8 low-dropout + regulators (LDOs). It also provides some GPIO, reset and battery + functions. It uses an I2C interface and is designed for use with + tablets and smartphones. config PMIC_AXP bool "Enable Driver Model for X-Powers AXP PMICs" @@ -101,8 +101,8 @@ config PMIC_AS3722 required for a tablets or laptop. config DM_PMIC_BD71837 - bool "Enable Driver Model for PMIC BD71837" - help + bool "Enable Driver Model for PMIC BD71837" + help This config enables implementation of driver-model pmic uclass features for PMIC BD71837. The driver implements read/write operations. @@ -173,257 +173,257 @@ config SPL_DM_PMIC_PCA9450 config DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC PFUZE100. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC PFUZE100. The driver implements read/write operations. config SPL_DM_PMIC_PFUZE100 bool "Enable Driver Model for PMIC PFUZE100 in SPL" depends on SPL_DM_PMIC - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC PFUZE100 in SPL. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC PFUZE100 in SPL. The driver implements read/write operations. config DM_PMIC_MAX8907 bool "Enable Driver Model for PMIC MAX8907" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX8907. The driver implements read/write operations. - This is a Power Management IC with a decent set of peripherals from which - 3 DC-to-DC Step-Down (SD) Regulators, 20 Low-Dropout Linear (LDO) Regulators, - Real-Time Clock (RTC) and more with I2C Compatible Interface. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8907. The driver implements read/write operations. + This is a Power Management IC with a decent set of peripherals from which + 3 DC-to-DC Step-Down (SD) Regulators, 20 Low-Dropout Linear (LDO) Regulators, + Real-Time Clock (RTC) and more with I2C Compatible Interface. config DM_PMIC_MAX77663 bool "Enable Driver Model for PMIC MAX77663" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX77663. The driver implements read/write operations. - This is a Power Management IC with a decent set of peripherals from which - 4 DC-to-DC Step-Down (SD) Regulators, 9 Low-Dropout Linear (LDO) Regulators, - 8 GPIOs, Real-Time Clock (RTC) and more with I2C Compatible Interface. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX77663. The driver implements read/write operations. + This is a Power Management IC with a decent set of peripherals from which + 4 DC-to-DC Step-Down (SD) Regulators, 9 Low-Dropout Linear (LDO) Regulators, + 8 GPIOs, Real-Time Clock (RTC) and more with I2C Compatible Interface. config DM_PMIC_MAX77686 bool "Enable Driver Model for PMIC MAX77686" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX77686. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX77686. The driver implements read/write operations. config DM_PMIC_MAX8998 bool "Enable Driver Model for PMIC MAX8998" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX8998. The driver implements read/write operations. + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8998. The driver implements read/write operations. config DM_PMIC_MC34708 bool "Enable Driver Model for PMIC MC34708" help - This config enables implementation of driver-model pmic uclass features - for PMIC MC34708. The driver implements read/write operations. + This config enables implementation of driver-model pmic uclass features + for PMIC MC34708. The driver implements read/write operations. config PMIC_MAX8997 bool "Enable Driver Model for PMIC MAX8997" - ---help--- - This config enables implementation of driver-model pmic uclass features - for PMIC MAX8997. The driver implements read/write operations. - This is a Power Management IC with RTC, Fuel Gauge, MUIC control on Chip. - - 21x LDOs - - 12x GPIOs - - Haptic motor driver - - RTC with two alarms - - Fuel Gauge and one backup battery charger - - MUIC - - Others + help + This config enables implementation of driver-model pmic uclass features + for PMIC MAX8997. The driver implements read/write operations. + This is a Power Management IC with RTC, Fuel Gauge, MUIC control on Chip. + - 21x LDOs + - 12x GPIOs + - Haptic motor driver + - RTC with two alarms + - Fuel Gauge and one backup battery charger + - MUIC + - Others config PMIC_QCOM bool "Enable Driver Model for Qualcomm generic PMIC" - ---help--- - The Qcom PMIC is connected to one (or several) processors - with SPMI bus. It has 2 slaves with several peripherals: - - 18x LDO - - 4x GPIO - - Power and Reset buttons - - Watchdog - - RTC - - Vibrator drivers - - Others + help + The Qcom PMIC is connected to one (or several) processors + with SPMI bus. It has 2 slaves with several peripherals: + - 18x LDO + - 4x GPIO + - Power and Reset buttons + - Watchdog + - RTC + - Vibrator drivers + - Others - Driver binding info: doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt + Driver binding info: doc/device-tree-bindings/pmic/qcom,spmi-pmic.txt config PMIC_RK8XX bool "Enable support for Rockchip PMIC RK8XX" select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF - ---help--- - The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, - an RTC and two low Rds (resistance (drain to source)) switches. It is - accessed via an I2C interface. The device is used with Rockchip SoCs. - This driver implements register read/write operations. + help + The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, + an RTC and two low Rds (resistance (drain to source)) switches. It is + accessed via an I2C interface. The device is used with Rockchip SoCs. + This driver implements register read/write operations. config SPL_PMIC_RK8XX bool "Enable support for Rockchip PMIC RK8XX in SPL" depends on SPL_DM_PMIC - ---help--- - The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, - an RTC and two low Rds (resistance (drain to source)) switches. It is - accessed via an I2C interface. The device is used with Rockchip SoCs. - This driver implements register read/write operations. + help + The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs, + an RTC and two low Rds (resistance (drain to source)) switches. It is + accessed via an I2C interface. The device is used with Rockchip SoCs. + This driver implements register read/write operations. config PMIC_S2MPS11 bool "Enable Driver Model for PMIC Samsung S2MPS11" - ---help--- - The Samsung S2MPS11 PMIC provides: - - 38 adjustable LDO regulators - - 9 High-Efficiency Buck Converters - - 1 BuckBoost Converter - - RTC with two alarms - - Backup battery charger - - I2C Configuration Interface - This driver provides access to I/O interface only. - Binding info: doc/device-tree-bindings/pmic/s2mps11.txt + help + The Samsung S2MPS11 PMIC provides: + - 38 adjustable LDO regulators + - 9 High-Efficiency Buck Converters + - 1 BuckBoost Converter + - RTC with two alarms + - Backup battery charger + - I2C Configuration Interface + This driver provides access to I/O interface only. + Binding info: doc/device-tree-bindings/pmic/s2mps11.txt config DM_PMIC_SANDBOX bool "Enable Driver Model for emulated Sandbox PMIC" - ---help--- - Enable the driver for Sandbox PMIC emulation. The emulated PMIC device - depends on two drivers: - - sandbox PMIC I/O driver - implements dm pmic operations - - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission + help + Enable the driver for Sandbox PMIC emulation. The emulated PMIC device + depends on two drivers: + - sandbox PMIC I/O driver - implements dm pmic operations + - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission - A detailed information can be found in header: '<power/sandbox_pmic.h>' + A detailed information can be found in header: '<power/sandbox_pmic.h>' - The Sandbox PMIC info: - * I/O interface: - - I2C chip address: 0x40 - - first register address: 0x0 - - register count: 0x10 - * Adjustable outputs: - - 2x LDO - - 2x BUCK - - Each, with a different operating conditions (header). - * Reset values: - - set by i2c emul driver's probe() (defaults in header) + The Sandbox PMIC info: + * I/O interface: + - I2C chip address: 0x40 + - first register address: 0x0 + - register count: 0x10 + * Adjustable outputs: + - 2x LDO + - 2x BUCK + - Each, with a different operating conditions (header). + * Reset values: + - set by i2c emul driver's probe() (defaults in header) - Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt + Driver binding info: doc/device-tree-bindings/pmic/sandbox.txt config DM_PMIC_CPCAP bool "Enable Driver Model for Motorola CPCAP" help - The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC - whose main purpose is power control. It was used in a wide variety of - Motorola products, both Tegra and OMAP based. The most notable devices - using this PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2. - Unlike most PMICs, this one is not I2C based; it uses the SPI bus. The - core driver provides both read and write access to the device registers. + The CPCAP is a Motorola/ST-Ericsson creation, a multifunctional IC + whose main purpose is power control. It was used in a wide variety of + Motorola products, both Tegra and OMAP based. The most notable devices + using this PMIC are the Motorola Droid 4, Atrix 4G, and Droid X2. + Unlike most PMICs, this one is not I2C based; it uses the SPI bus. The + core driver provides both read and write access to the device registers. config PMIC_S5M8767 bool "Enable Driver Model for the Samsung S5M8767 PMIC" - ---help--- - The S5M8767 PMIC provides a large array of LDOs and BUCKs for use - as a SoC power controller. It also provides 32KHz clock outputs. This - driver provides basic register access and sets up the attached - regulators if regulator support is enabled. + help + The S5M8767 PMIC provides a large array of LDOs and BUCKs for use + as a SoC power controller. It also provides 32KHz clock outputs. This + driver provides basic register access and sets up the attached + regulators if regulator support is enabled. config PMIC_RN5T567 bool "Enable driver for Ricoh RN5T567 PMIC" - ---help--- - The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO - regulators Real-Time Clock and 4 GPIOs. This driver provides - register access only. + help + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO + regulators Real-Time Clock and 4 GPIOs. This driver provides + register access only. config SPL_PMIC_RN5T567 bool "Enable driver for Ricoh RN5T567 PMIC in SPL" depends on SPL_DM_PMIC - ---help--- - The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO - regulators Real-Time Clock and 4 GPIOs. This driver provides - register access only. + help + The RN5T567 is a PMIC with 4 step-down DC/DC converters, 5 LDO + regulators Real-Time Clock and 4 GPIOs. This driver provides + register access only. config PMIC_TPS65090 bool "Enable driver for Texas Instruments TPS65090 PMIC" - ---help--- - The TPS65090 is a PMIC containing several LDOs, DC to DC convertors, - FETs and a battery charger. This driver provides register access - only, and you can enable the regulator/charger drivers separately if - required. + help + The TPS65090 is a PMIC containing several LDOs, DC to DC convertors, + FETs and a battery charger. This driver provides register access + only, and you can enable the regulator/charger drivers separately if + required. config PMIC_PALMAS bool "Enable driver for Texas Instruments PALMAS PMIC" - ---help--- - The PALMAS is a PMIC containing several LDOs, SMPS. - This driver binds the pmic children. + help + The PALMAS is a PMIC containing several LDOs, SMPS. + This driver binds the pmic children. config PMIC_LP873X bool "Enable driver for Texas Instruments LP873X PMIC" - ---help--- - The LP873X is a PMIC containing couple of LDOs and couple of SMPS. - This driver binds the pmic children. + help + The LP873X is a PMIC containing couple of LDOs and couple of SMPS. + This driver binds the pmic children. config PMIC_LP87565 bool "Enable driver for Texas Instruments LP87565 PMIC" - ---help--- - The LP87565 is a PMIC containing a bunch of SMPS. - This driver binds the pmic children. + help + The LP87565 is a PMIC containing a bunch of SMPS. + This driver binds the pmic children. config DM_PMIC_TPS65910 bool "Enable driver for Texas Instruments TPS65910 PMIC" - ---help--- - The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost - DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO - pmic children. + help + The TPS65910 is a PMIC containing 3 buck DC-DC converters, one boost + DC-DC converter, 8 LDOs and a RTC. This driver binds the SMPS and LDO + pmic children. config DM_PMIC_TPS80031 bool "Enable driver for Texas Instruments TPS80031/TPS80032 PMIC" - ---help--- - This config enables implementation of driver-model pmic uclass features - for TPS80031/TPS80032 PMICs. The driver implements read/write operations. - This is a Power Management IC with a decent set of peripherals from which - 5 Buck Converters refered as Switched-mode power supply (SMPS), 11 General- - Purpose Low-Dropout Voltage Regulators (LDO), USB OTG Module, Real-Time - Clock (RTC) with Timer and Alarm Wake-Up, Two Digital PWM Outputs and more - with I2C Compatible Interface. PMIC occupies 4 I2C addresses. + help + This config enables implementation of driver-model pmic uclass features + for TPS80031/TPS80032 PMICs. The driver implements read/write operations. + This is a Power Management IC with a decent set of peripherals from which + 5 Buck Converters referred as Switched-mode power supply (SMPS), 11 General- + Purpose Low-Dropout Voltage Regulators (LDO), USB OTG Module, Real-Time + Clock (RTC) with Timer and Alarm Wake-Up, Two Digital PWM Outputs and more + with I2C Compatible Interface. PMIC occupies 4 I2C addresses. config PMIC_STPMIC1 bool "Enable support for STMicroelectronics STPMIC1 PMIC" depends on DM_I2C select SYSRESET_CMD_POWEROFF if SYSRESET && CMD_POWEROFF && !ARM_PSCI_FW - ---help--- - The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. - It is accessed via an I2C interface. The device is used with STM32MP1 - SoCs. This driver implements register read/write operations. + help + The STPMIC1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches. + It is accessed via an I2C interface. The device is used with STM32MP1 + SoCs. This driver implements register read/write operations. config SPL_PMIC_PALMAS bool "Enable driver for Texas Instruments PALMAS PMIC" depends on SPL_DM_PMIC help - The PALMAS is a PMIC containing several LDOs, SMPS. - This driver binds the pmic children in SPL. + The PALMAS is a PMIC containing several LDOs, SMPS. + This driver binds the pmic children in SPL. config SPL_PMIC_LP873X bool "Enable driver for Texas Instruments LP873X PMIC" depends on SPL_DM_PMIC help - The LP873X is a PMIC containing couple of LDOs and couple of SMPS. - This driver binds the pmic children in SPL. + The LP873X is a PMIC containing couple of LDOs and couple of SMPS. + This driver binds the pmic children in SPL. config SPL_PMIC_LP87565 bool "Enable driver for Texas Instruments LP87565 PMIC" depends on SPL_DM_PMIC help - The LP87565 is a PMIC containing a bunch of SMPS. - This driver binds the pmic children in SPL. + The LP87565 is a PMIC containing a bunch of SMPS. + This driver binds the pmic children in SPL. config PMIC_TPS65941 bool "Enable driver for Texas Instruments TPS65941 PMIC" depends on DM_PMIC help - The TPS65941 is a PMIC containing a bunch of SMPS & LDOs. - This driver binds the pmic children. + The TPS65941 is a PMIC containing a bunch of SMPS & LDOs. + This driver binds the pmic children. config PMIC_TPS65219 bool "Enable driver for Texas Instruments TPS65219 PMIC" depends on DM_PMIC help - The TPS65219 is a PMIC containing a bunch of SMPS & LDOs. - This driver binds the pmic children. + The TPS65219 is a PMIC containing a bunch of SMPS & LDOs. + This driver binds the pmic children. config PMIC_RAA215300 bool "Renesas RAA215300 PMIC driver" @@ -445,11 +445,11 @@ endif config PMIC_TPS65217 bool "Enable driver for Texas Instruments TPS65217 PMIC" - ---help--- - The TPS65217 is a PMIC containing several LDOs, DC to DC convertors, - FETs and a battery charger. This driver provides register access - only, and you can enable the regulator/charger drivers separately if - required. + help + The TPS65217 is a PMIC containing several LDOs, DC to DC convertors, + FETs and a battery charger. This driver provides register access + only, and you can enable the regulator/charger drivers separately if + required. config POWER_TPS65218 bool "Enable legacy driver for TPS65218 PMIC" @@ -485,9 +485,9 @@ config POWER_PFUZE3000 config POWER_MC34VR500 bool "Enable driver for Freescale MC34VR500 PMIC" - ---help--- - The MC34VR500 is used in conjunction with the FSL T1 and LS1 series - SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed - via an I2C interface. + help + The MC34VR500 is used in conjunction with the FSL T1 and LS1 series + SoC. It provides 4 buck DC-DC convertors and 5 LDOs, and it is accessed + via an I2C interface. endif diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig index ca5de5b8726..3b3ed97eb9f 100644 --- a/drivers/power/regulator/Kconfig +++ b/drivers/power/regulator/Kconfig @@ -1,38 +1,38 @@ config DM_REGULATOR bool "Enable Driver Model for REGULATOR drivers (UCLASS_REGULATOR)" depends on DM - ---help--- - This config enables the driver model regulator support. - UCLASS_REGULATOR - designed to provide a common API for basic regulator's - functions, like get/set Voltage or Current value, enable state, etc... - Note: - When enabling this, please read the description, found in the files: - - 'include/power/pmic.h' - - 'include/power/regulator.h' - - 'drivers/power/pmic/pmic-uclass.c' - - 'drivers/power/pmic/regulator-uclass.c' - It's important to call the device_bind() with the proper node offset, - when binding the regulator devices. The pmic_bind_childs() can be used - for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_dev() - otherwise. Detailed information can be found in the header file. + help + This config enables the driver model regulator support. + UCLASS_REGULATOR - designed to provide a common API for basic regulator's + functions, like get/set Voltage or Current value, enable state, etc... + Note: + When enabling this, please read the description, found in the files: + - 'include/power/pmic.h' + - 'include/power/regulator.h' + - 'drivers/power/pmic/pmic-uclass.c' + - 'drivers/power/pmic/regulator-uclass.c' + It's important to call the device_bind() with the proper node offset, + when binding the regulator devices. The pmic_bind_childs() can be used + for this purpose if PMIC I/O driver is implemented or dm_scan_fdt_dev() + otherwise. Detailed information can be found in the header file. config SPL_DM_REGULATOR bool "Enable regulators for SPL" depends on DM_REGULATOR && SPL_POWER - ---help--- - Regulators are seldom needed in SPL. Even if they are accessed, some - code space can be saved by accessing the PMIC registers directly. - Enable this option if you need regulators in SPL and can cope with - the extra code size. + help + Regulators are seldom needed in SPL. Even if they are accessed, some + code space can be saved by accessing the PMIC registers directly. + Enable this option if you need regulators in SPL and can cope with + the extra code size. config REGULATOR_ACT8846 bool "Enable driver for ACT8846 regulator" depends on DM_REGULATOR && PMIC_ACT8846 - ---help--- - Enable support for the regulator functions of the ACT8846 PMIC. The - driver implements get/set api for the various BUCKS and LDOS supported - by the PMIC device. This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the regulator functions of the ACT8846 PMIC. The + driver implements get/set api for the various BUCKS and LDOS supported + by the PMIC device. This driver is controlled by a device tree node + which includes voltage limits. config REGULATOR_AS3722 bool "Enable driver for AS7322 regulator" @@ -75,33 +75,33 @@ config DM_REGULATOR_BD71837 bool "Enable Driver Model for ROHM BD71837/BD71847 regulators" depends on DM_REGULATOR && DM_PMIC_BD71837 help - This config enables implementation of driver-model regulator uclass - features for regulators on ROHM BD71837 and BD71847 PMICs. - BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version - containing 6 bucks and 6 LDOs. The driver implements get/set api for - value and enable. + This config enables implementation of driver-model regulator uclass + features for regulators on ROHM BD71837 and BD71847 PMICs. + BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version + containing 6 bucks and 6 LDOs. The driver implements get/set api for + value and enable. config SPL_DM_REGULATOR_BD71837 bool "Enable Driver Model for ROHM BD71837/BD71847 regulators in SPL" depends on DM_REGULATOR_BD71837 && SPL help - This config enables implementation of driver-model regulator uclass - features for regulators on ROHM BD71837 and BD71847 in SPL. + This config enables implementation of driver-model regulator uclass + features for regulators on ROHM BD71837 and BD71847 in SPL. config DM_REGULATOR_PCA9450 bool "Enable Driver Model for NXP PCA9450 regulators" depends on DM_REGULATOR && DM_PMIC_PCA9450 help - This config enables implementation of driver-model regulator uclass - features for regulators on NXP PCA9450 PMICs. PCA9450 contains 6 bucks - and 5 LDOS. The driver implements get/set api for value and enable. + This config enables implementation of driver-model regulator uclass + features for regulators on NXP PCA9450 PMICs. PCA9450 contains 6 bucks + and 5 LDOS. The driver implements get/set api for value and enable. config SPL_DM_REGULATOR_PCA9450 bool "Enable Driver Model for NXP PCA9450 regulators in SPL" depends on DM_REGULATOR_PCA9450 && SPL help - This config enables implementation of driver-model regulator uclass - features for regulators on ROHM PCA9450 in SPL. + This config enables implementation of driver-model regulator uclass + features for regulators on ROHM PCA9450 in SPL. config DM_REGULATOR_DA9063 bool "Enable Driver Model for REGULATOR DA9063" @@ -127,55 +127,55 @@ config DM_REGULATOR_PFUZE100 bool "Enable Driver Model for REGULATOR PFUZE100" depends on DM_REGULATOR && DM_PMIC_PFUZE100 default DM_PMIC_PFUZE100 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR PFUZE100. The driver implements get/set api for: - value, enable and mode. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR PFUZE100. The driver implements get/set api for: + value, enable and mode. config SPL_DM_REGULATOR_PFUZE100 bool "Enable Driver Model for REGULATOR PFUZE100 in SPL" depends on SPL_DM_REGULATOR && SPL_DM_PMIC_PFUZE100 default SPL_DM_PMIC_PFUZE100 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR PFUZE100. The driver implements get/set api for: - value, enable and mode. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR PFUZE100. The driver implements get/set api for: + value, enable and mode. config REGULATOR_PWM bool "Enable driver for PWM regulators" depends on DM_REGULATOR && DM_PWM - ---help--- - Enable support for the PWM regulator functions which voltage are - controlled by PWM duty ratio. Some of Rockchip board using this kind - of regulator. The driver implements get/set api for the various BUCKS. - This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the PWM regulator functions which voltage are + controlled by PWM duty ratio. Some of Rockchip board using this kind + of regulator. The driver implements get/set api for the various BUCKS. + This driver is controlled by a device tree node + which includes voltage limits. config DM_REGULATOR_MAX8907 bool "Enable Driver Model for REGULATOR MAX8907" depends on DM_REGULATOR && DM_PMIC_MAX8907 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR MAX8907. The driver supports both DC-to-DC - Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators - found in MAX8907 PMIC and implements get/set api for value and enable. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR MAX8907. The driver supports both DC-to-DC + Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators + found in MAX8907 PMIC and implements get/set api for value and enable. config DM_REGULATOR_MAX77663 bool "Enable Driver Model for REGULATOR MAX77663" depends on DM_REGULATOR && DM_PMIC_MAX77663 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR MAX77663. The driver supports both DC-to-DC - Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators - found in MAX77663 PMIC and implements get/set api for value and enable. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR MAX77663. The driver supports both DC-to-DC + Step-Down (SD) Regulators and Low-Dropout Linear (LDO) Regulators + found in MAX77663 PMIC and implements get/set api for value and enable. config DM_REGULATOR_MAX77686 bool "Enable Driver Model for REGULATOR MAX77686" depends on DM_REGULATOR && DM_PMIC_MAX77686 - ---help--- - This config enables implementation of driver-model regulator uclass - features for REGULATOR MAX77686. The driver implements get/set api for: - value, enable and mode. + help + This config enables implementation of driver-model regulator uclass + features for REGULATOR MAX77686. The driver implements get/set api for: + value, enable and mode. config DM_REGULATOR_NPCM8XX bool "Enable Driver Model for NPCM8xx voltage supply" @@ -221,33 +221,33 @@ config DM_REGULATOR_FIXED bool "Enable Driver Model for REGULATOR Fixed value" depends on DM_REGULATOR select DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for fixed value regulators. The driver implements get/set api - for enable and get only for voltage value. + help + This config enables implementation of driver-model regulator uclass + features for fixed value regulators. The driver implements get/set api + for enable and get only for voltage value. config SPL_DM_REGULATOR_FIXED bool "Enable Driver Model for REGULATOR Fixed value in SPL" depends on DM_REGULATOR_FIXED && SPL select SPL_DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for fixed value regulators in SPL. + help + This config enables implementation of driver-model regulator uclass + features for fixed value regulators in SPL. config DM_REGULATOR_GPIO bool "Enable Driver Model for GPIO REGULATOR" depends on DM_REGULATOR && DM_GPIO select DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for gpio regulators. The driver implements get/set for - voltage value. + help + This config enables implementation of driver-model regulator uclass + features for gpio regulators. The driver implements get/set for + voltage value. config DM_REGULATOR_QCOM_RPMH bool "Enable driver model for Qualcomm RPMh regulator" depends on DM_REGULATOR && QCOM_RPMH select DEVRES - ---help--- + help Enable support for the Qualcomm RPMh regulator. The driver implements get/set api for a limited set of regulators used by u-boot. @@ -255,7 +255,7 @@ config DM_REGULATOR_QCOM_RPMH config DM_REGULATOR_QCOM_USB_VBUS bool "Enable driver model for Qualcomm USB vbus regulator" depends on DM_REGULATOR && DM_PMIC - ---help--- + help Enable support for the Qualcomm USB Vbus regulator. The driver implements get/set api for the regulator to be used by u-boot. @@ -263,18 +263,18 @@ config SPL_DM_REGULATOR_GPIO bool "Enable Driver Model for GPIO REGULATOR in SPL" depends on DM_REGULATOR_GPIO && SPL_DM_GPIO select SPL_DM_REGULATOR_COMMON - ---help--- - This config enables implementation of driver-model regulator uclass - features for gpio regulators in SPL. + help + This config enables implementation of driver-model regulator uclass + features for gpio regulators in SPL. config REGULATOR_RK8XX bool "Enable driver for RK8XX regulators" depends on DM_REGULATOR && PMIC_RK8XX - ---help--- - Enable support for the regulator functions of the RK8XX PMIC. The - driver implements get/set api for the various BUCKS and LDOs supported - by the PMIC device. This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the regulator functions of the RK8XX PMIC. The + driver implements get/set api for the various BUCKS and LDOs supported + by the PMIC device. This driver is controlled by a device tree node + which includes voltage limits. config SPL_REGULATOR_RK8XX bool "Enable driver for RK8XX regulators in SPL" @@ -288,162 +288,162 @@ config SPL_REGULATOR_RK8XX config DM_REGULATOR_S2MPS11 bool "Enable driver for S2MPS11 regulator" depends on DM_REGULATOR && PMIC_S2MPS11 - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR S2MPS11. - The driver implements get/set api for: value and enable. + help + This enables implementation of driver-model regulator uclass + features for REGULATOR S2MPS11. + The driver implements get/set api for: value and enable. config REGULATOR_S5M8767 bool "Enable support for S5M8767 regulator" depends on DM_REGULATOR && PMIC_S5M8767 - ---help--- - This enables the regulator features of the S5M8767, allowing voltages - to be set, etc. The driver is not fully complete but supports most - common requirements, including all LDOs and BUCKs. This allows many - supplies to be set automatically using the device tree values. + help + This enables the regulator features of the S5M8767, allowing voltages + to be set, etc. The driver is not fully complete but supports most + common requirements, including all LDOs and BUCKs. This allows many + supplies to be set automatically using the device tree values. config DM_REGULATOR_SANDBOX bool "Enable Driver Model for Sandbox PMIC regulator" depends on DM_REGULATOR && DM_PMIC_SANDBOX - ---help--- - Enable the regulator driver for emulated Sandbox PMIC. - The emulated PMIC device depends on two drivers: - - sandbox PMIC I/O driver - implements dm pmic operations - - sandbox PMIC regulator driver - implements dm regulator operations - - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission + help + Enable the regulator driver for emulated Sandbox PMIC. + The emulated PMIC device depends on two drivers: + - sandbox PMIC I/O driver - implements dm pmic operations + - sandbox PMIC regulator driver - implements dm regulator operations + - sandbox PMIC i2c emul driver - emulates the PMIC's I2C transmission - The regulator driver provides uclass operations for sandbox PMIC's - regulators. The driver implements get/set api for: voltage, current, - operation mode and enable state. - The driver supports LDO and BUCK regulators. + The regulator driver provides uclass operations for sandbox PMIC's + regulators. The driver implements get/set api for: voltage, current, + operation mode and enable state. + The driver supports LDO and BUCK regulators. - The Sandbox PMIC info: - * I/O interface: - - I2C chip address: 0x40 - - first register address: 0x0 - - register count: 0x10 - * Adjustable outputs: - - 2x LDO - - 2x BUCK - - Each, with a different operating conditions (header). - * Reset values: - - set by i2c emul driver's probe() (defaults in header) + The Sandbox PMIC info: + * I/O interface: + - I2C chip address: 0x40 + - first register address: 0x0 + - register count: 0x10 + * Adjustable outputs: + - 2x LDO + - 2x BUCK + - Each, with a different operating conditions (header). + * Reset values: + - set by i2c emul driver's probe() (defaults in header) - A detailed information can be found in header: '<power/sandbox_pmic.h>' - Binding info: 'doc/device-tree-bindings/pmic/max77686.txt' + A detailed information can be found in header: '<power/sandbox_pmic.h>' + Binding info: 'doc/device-tree-bindings/pmic/max77686.txt' config REGULATOR_TPS65090 bool "Enable driver for TPS65090 PMIC regulators" depends on PMIC_TPS65090 - ---help--- - The TPS65090 provides several FETs (Field-effect Transistors, - effectively switches) which are supported by this driver as - regulators, one for each FET. The standard regulator interface is - supported, but it is only possible to turn the regulators on or off. - There is no voltage/current control. + help + The TPS65090 provides several FETs (Field-effect Transistors, + effectively switches) which are supported by this driver as + regulators, one for each FET. The standard regulator interface is + supported, but it is only possible to turn the regulators on or off. + There is no voltage/current control. config DM_REGULATOR_PALMAS bool "Enable driver for PALMAS PMIC regulators" - depends on PMIC_PALMAS - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR PALMAS and the family of PALMAS PMICs. - The driver implements get/set api for: value and enable. + depends on PMIC_PALMAS + help + This enables implementation of driver-model regulator uclass + features for REGULATOR PALMAS and the family of PALMAS PMICs. + The driver implements get/set api for: value and enable. config DM_REGULATOR_PBIAS bool "Enable driver for PBIAS regulator" depends on DM_REGULATOR select REGMAP select SYSCON - ---help--- - This enables implementation of driver-model regulator uclass - features for pseudo-regulator PBIAS found in the OMAP SOCs. - This pseudo-regulator is used to provide a BIAS voltage to MMC1 - signal pads and must be configured properly during a voltage switch. - Voltage switching is required by some operating modes of SDcards and - eMMC. + help + This enables implementation of driver-model regulator uclass + features for pseudo-regulator PBIAS found in the OMAP SOCs. + This pseudo-regulator is used to provide a BIAS voltage to MMC1 + signal pads and must be configured properly during a voltage switch. + Voltage switching is required by some operating modes of SDcards and + eMMC. config DM_REGULATOR_LP873X bool "Enable driver for LP873X PMIC regulators" - depends on PMIC_LP873X - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR LP873X and the family of LP873X PMICs. - The driver implements get/set api for: value and enable. + depends on PMIC_LP873X + help + This enables implementation of driver-model regulator uclass + features for REGULATOR LP873X and the family of LP873X PMICs. + The driver implements get/set api for: value and enable. config DM_REGULATOR_LP87565 bool "Enable driver for LP87565 PMIC regulators" - depends on PMIC_LP87565 - ---help--- - This enables implementation of driver-model regulator uclass - features for REGULATOR LP87565 and the family of LP87565 PMICs. - LP87565 series of PMICs have 4 single phase BUCKs that can also - be configured in multi phase modes. The driver implements - get/set api for value and enable. + depends on PMIC_LP87565 + help + This enables implementation of driver-model regulator uclass + features for REGULATOR LP87565 and the family of LP87565 PMICs. + LP87565 series of PMICs have 4 single phase BUCKs that can also + be configured in multi phase modes. The driver implements + get/set api for value and enable. config DM_REGULATOR_STM32_VREFBUF bool "Enable driver for STMicroelectronics STM32 VREFBUF" depends on DM_REGULATOR && (STM32H7 || ARCH_STM32MP) help - This driver supports STMicroelectronics STM32 VREFBUF (voltage - reference buffer) which can be used as voltage reference for - internal ADCs, DACs and also for external components through - dedicated Vref+ pin. + This driver supports STMicroelectronics STM32 VREFBUF (voltage + reference buffer) which can be used as voltage reference for + internal ADCs, DACs and also for external components through + dedicated Vref+ pin. config DM_REGULATOR_TPS65910 bool "Enable driver for TPS65910 PMIC regulators" depends on DM_PMIC_TPS65910 - ---help--- - The TPS65910 PMIC provides 4 SMPSs and 8 LDOs. This driver supports all - regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements - the get/set api for value and enable. + help + The TPS65910 PMIC provides 4 SMPSs and 8 LDOs. This driver supports all + regulator types of the TPS65910 (BUCK, BOOST and LDO). It implements + the get/set api for value and enable. config DM_REGULATOR_TPS65911 bool "Enable driver for TPS65911 PMIC regulators" depends on DM_PMIC_TPS65910 - ---help--- - This config enables implementation of driver-model regulator - uclass features for the TPS65911 PMIC. The driver supports Step-Down - DC-DC Converters for Processor Cores (VDD1 and VDD2), Step-Down DC-DC - Converter for I/O Power (VIO), Controller for External FETs (VDDCtrl) - and LDO Voltage Regulators found in TPS65911 PMIC and implements - get/set api for value and enable. + help + This config enables implementation of driver-model regulator + uclass features for the TPS65911 PMIC. The driver supports Step-Down + DC-DC Converters for Processor Cores (VDD1 and VDD2), Step-Down DC-DC + Converter for I/O Power (VIO), Controller for External FETs (VDDCtrl) + and LDO Voltage Regulators found in TPS65911 PMIC and implements + get/set api for value and enable. config DM_REGULATOR_TPS62360 bool "Enable driver for TPS6236x Power Regulator" depends on DM_REGULATOR help - The TPS6236X DC/DC step down converter provides a single output - power line peaking at 3A current. This driver supports all four - variants of the chip (TPS62360, TPS62361, TPS62362, TPS62363). It - implements the get/set api for value only, as the power line is - always on. + The TPS6236X DC/DC step down converter provides a single output + power line peaking at 3A current. This driver supports all four + variants of the chip (TPS62360, TPS62361, TPS62362, TPS62363). It + implements the get/set api for value only, as the power line is + always on. config DM_REGULATOR_TPS80031 bool "Enable driver for TPS80031/TPS80032 PMIC regulators" depends on DM_PMIC_TPS80031 - ---help--- - This enables implementation of driver-model regulator uclass - features for TPS80031/TPS80032 PMICs. The driver implements - get/set api for: value and enable. + help + This enables implementation of driver-model regulator uclass + features for TPS80031/TPS80032 PMICs. The driver implements + get/set api for: value and enable. config DM_REGULATOR_TPS6287X bool "Enable driver for TPS6287x Power Regulator" depends on DM_REGULATOR help - The TPS6287X is a step down converter with a fast transient - response. This driver supports all four variants of the chip - (TPS62870, TPS62871, TPS62872, TPS62873). It implements the - get/set api for value only, as the power line is always on. + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. config DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators" depends on DM_REGULATOR && PMIC_STPMIC1 - ---help--- - Enable support for the regulator functions of the STPMIC1 PMIC. The - driver implements get/set api for the various BUCKS and LDOs supported - by the PMIC device. This driver is controlled by a device tree node - which includes voltage limits. + help + Enable support for the regulator functions of the STPMIC1 PMIC. The + driver implements get/set api for the various BUCKS and LDOs supported + by the PMIC device. This driver is controlled by a device tree node + which includes voltage limits. config DM_REGULATOR_ANATOP bool "Enable driver for ANATOP regulators" @@ -451,18 +451,18 @@ config DM_REGULATOR_ANATOP select REGMAP select SYSCON help - Enable support for the Freescale i.MX on-chip ANATOP LDO - regulators. It is recommended that this option be enabled on - i.MX6 platform. + Enable support for the Freescale i.MX on-chip ANATOP LDO + regulators. It is recommended that this option be enabled on + i.MX6 platform. config SPL_DM_REGULATOR_TPS6287X bool "Enable driver for TPS6287x Power Regulator" depends on SPL_DM_REGULATOR help - The TPS6287X is a step down converter with a fast transient - response. This driver supports all four variants of the chip - (TPS62870, TPS62871, TPS62872, TPS62873). It implements the - get/set api for value only, as the power line is always on. + The TPS6287X is a step down converter with a fast transient + response. This driver supports all four variants of the chip + (TPS62870, TPS62871, TPS62872, TPS62873). It implements the + get/set api for value only, as the power line is always on. config SPL_DM_REGULATOR_STPMIC1 bool "Enable driver for STPMIC1 regulators in SPL" @@ -474,54 +474,54 @@ config SPL_DM_REGULATOR_PALMAS bool "Enable driver for PALMAS PMIC regulators" depends on SPL_PMIC_PALMAS help - This enables implementation of driver-model regulator uclass - features for REGULATOR PALMAS and the family of PALMAS PMICs. - The driver implements get/set api for: value and enable in SPL. + This enables implementation of driver-model regulator uclass + features for REGULATOR PALMAS and the family of PALMAS PMICs. + The driver implements get/set api for: value and enable in SPL. config SPL_DM_REGULATOR_LP87565 bool "Enable driver for LP87565 PMIC regulators" depends on SPL_PMIC_LP87565 help - This enables implementation of driver-model regulator uclass - features for REGULATOR LP87565 and the family of LP87565 PMICs. - LP87565 series of PMICs have 4 single phase BUCKs that can also - be configured in multi phase modes. The driver implements - get/set api for value and enable in SPL. + This enables implementation of driver-model regulator uclass + features for REGULATOR LP87565 and the family of LP87565 PMICs. + LP87565 series of PMICs have 4 single phase BUCKs that can also + be configured in multi phase modes. The driver implements + get/set api for value and enable in SPL. config SPL_DM_REGULATOR_LP873X bool "Enable driver for LP873X PMIC regulators" depends on SPL_PMIC_LP873X help - This enables implementation of driver-model regulator uclass - features for REGULATOR LP873X and the family of LP873X PMICs. - The driver implements get/set api for: value and enable in SPL. + This enables implementation of driver-model regulator uclass + features for REGULATOR LP873X and the family of LP873X PMICs. + The driver implements get/set api for: value and enable in SPL. config DM_REGULATOR_TPS65941 bool "Enable driver for TPS65941 PMIC regulators" - depends on PMIC_TPS65941 + depends on PMIC_TPS65941 help - This enables implementation of driver-model regulator uclass - features for REGULATOR TPS65941 and the family of TPS65941 PMICs. - TPS65941 series of PMICs have 5 single phase BUCKs that can also - be configured in multi phase modes & 4 LDOs. The driver implements - get/set api for value and enable. + This enables implementation of driver-model regulator uclass + features for REGULATOR TPS65941 and the family of TPS65941 PMICs. + TPS65941 series of PMICs have 5 single phase BUCKs that can also + be configured in multi phase modes & 4 LDOs. The driver implements + get/set api for value and enable. config DM_REGULATOR_SCMI bool "Enable driver for SCMI voltage domain regulators" depends on DM_REGULATOR select SCMI_AGENT - help - Enable this option if you want to support regulators exposed through + help + Enable this option if you want to support regulators exposed through the SCMI voltage domain protocol by a SCMI server. config DM_REGULATOR_TPS65219 bool "Enable driver for TPS65219 PMIC regulators" - depends on PMIC_TPS65219 + depends on PMIC_TPS65219 help - This enables implementation of driver-model regulator uclass - features for REGULATOR TPS65219 and the family of TPS65219 PMICs. - TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs. - The driver implements get/set api for value and enable. + This enables implementation of driver-model regulator uclass + features for REGULATOR TPS65219 and the family of TPS65219 PMICs. + TPS65219 series of PMICs have 3 single phase BUCKs & 4 LDOs. + The driver implements get/set api for value and enable. config REGULATOR_RZG2L_USBPHY bool "Enable driver for RZ/G2L USB PHY VBUS supply" @@ -534,11 +534,11 @@ config REGULATOR_RZG2L_USBPHY config DM_REGULATOR_CPCAP bool "Enable driver for CPCAP PMIC regulators" depends on DM_REGULATOR && DM_PMIC_CPCAP - ---help--- - Enable implementation of driver-model regulator uclass features for - REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching - (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP - PMIC and implements get/set api for voltage and state. + help + Enable implementation of driver-model regulator uclass features for + REGULATOR CPCAP. The driver supports both DC-to-DC Step-Down Switching + (SW) Regulators and Low-Dropout Linear (LDO) Regulators found in CPCAP + PMIC and implements get/set api for voltage and state. config DM_REGULATOR_MT6357 bool "Enable driver for MediaTek MT6357 PMIC regulators" diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig index e4918460de6..fa5c890bb7a 100644 --- a/drivers/ram/aspeed/Kconfig +++ b/drivers/ram/aspeed/Kconfig @@ -4,19 +4,19 @@ menuconfig ASPEED_RAM depends on ARCH_ASPEED || TARGET_ASPEED_AST2700_IBEX default ARCH_ASPEED help - Configuration options for DDR SDRAM on ASPEED systems. + Configuration options for DDR SDRAM on ASPEED systems. - RAM initialisation is always built in for the platform. This menu - allows customisation of the configuration used. + RAM initialisation is always built in for the platform. This menu + allows customisation of the configuration used. config ASPEED_DDR4_DUALX8 bool "Enable Dual X8 DDR4 die" depends on ASPEED_RAM help - Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM - SRAM controller needs to know if the memory chip mounted on the - board is dual x8 die or not, otherwise it may get the wrong - size of the memory space. + Say Y if dual X8 DDR4 die is used on the board. The ASPEED DDRM + SRAM controller needs to know if the memory chip mounted on the + board is dual x8 die or not, otherwise it may get the wrong + size of the memory space. config ASPEED_BYPASS_SELFTEST depends on ASPEED_RAM @@ -77,7 +77,7 @@ choice prompt "AST2700 DDR target date rate" default ASPEED_DDR_3200 depends on ASPEED_RAM - depends on TARGET_ASPEED_AST2700_IBEX + depends on ASPEED_AST2700 || TARGET_ASPEED_AST2700_IBEX config ASPEED_DDR_1600 bool "1600 Mbps" diff --git a/drivers/ram/aspeed/Makefile b/drivers/ram/aspeed/Makefile index 1f0b22c8e9f..d29e2154ce9 100644 --- a/drivers/ram/aspeed/Makefile +++ b/drivers/ram/aspeed/Makefile @@ -2,4 +2,5 @@ # obj-$(CONFIG_ASPEED_AST2500) += sdram_ast2500.o obj-$(CONFIG_ASPEED_AST2600) += sdram_ast2600.o +obj-$(CONFIG_ASPEED_AST2700) += sdram_ast2700.o obj-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += sdram_ast2700.o diff --git a/drivers/ram/aspeed/sdram_ast2700.c b/drivers/ram/aspeed/sdram_ast2700.c index 00974da52bb..8605a92abb2 100644 --- a/drivers/ram/aspeed/sdram_ast2700.c +++ b/drivers/ram/aspeed/sdram_ast2700.c @@ -14,6 +14,11 @@ #include <linux/sizes.h> #include <ram.h> +__weak int fmc_hdr_get_prebuilt(u32 type, u32 *ofst, u32 *size) +{ + return -ENOSYS; +} + enum ddr_type { DDR4_1600 = 0x0, DDR4_2400, @@ -128,13 +133,13 @@ static size_t ast2700_sdrammc_get_vga_mem_size(struct sdrammc *sdrammc) reg = readl(scu0 + SCU0_PCI_MISC70); if (reg & SCU0_PCI_MISC70_EN_PCIEVGA0) { - debug("VGA0:%dMB\n", vga_memsz[sel] / SZ_1M); + debug("VGA0:%zuMB\n", vga_memsz[sel] / SZ_1M); dual++; } reg = readl(scu0 + SCU0_PCI_MISC80); if (reg & SCU0_PCI_MISC80_EN_PCIEVGA1) { - debug("VGA1:%dMB\n", vga_memsz[sel] / SZ_1M); + debug("VGA1:%zuMB\n", vga_memsz[sel] / SZ_1M); dual++; } @@ -560,7 +565,7 @@ void dwc_get_mailbox(struct sdrammc *sdrammc, const int mode, u32 *mbox) dwc_ddrphy_apb_wr(0xd0031, 1); } -uint32_t dwc_readMsgBlock(struct sdrammc *sdrammc, const u32 addr_half) +u32 dwc_readMsgBlock(struct sdrammc *sdrammc, const u32 addr_half) { u32 data_word; @@ -727,7 +732,7 @@ int dwc_ddrphy_phyinit_userCustom_D_loadIMEM(struct sdrammc *sdrammc, const int fmc_hdr_get_prebuilt(pb_type, &imem_ofst, &imem_size); memcpy(sdrammc->phy + (DWC_PHY_IMEM_OFST << 1), - (void *)(0x20000000 + imem_ofst), imem_size); + (void *)(uintptr_t)(0x20000000 + imem_ofst), imem_size); return 0; } @@ -746,7 +751,7 @@ int dwc_ddrphy_phyinit_userCustom_F_loadDMEM(struct sdrammc *sdrammc, fmc_hdr_get_prebuilt(pb_type, &dmem_ofst, &dmem_size); memcpy(sdrammc->phy + (DWC_PHY_DMEM_OFST << 1), - (void *)(0x20000000 + dmem_ofst), dmem_size); + (void *)(uintptr_t)(0x20000000 + dmem_ofst), dmem_size); return 0; } diff --git a/drivers/ram/octeon/Kconfig b/drivers/ram/octeon/Kconfig index f19957293f9..37bf4851400 100644 --- a/drivers/ram/octeon/Kconfig +++ b/drivers/ram/octeon/Kconfig @@ -2,14 +2,14 @@ config RAM_OCTEON bool "Ram drivers for Octeon SoCs" depends on RAM && ARCH_OCTEON help - This enables support for RAM drivers for Octeon SoCs. + This enables support for RAM drivers for Octeon SoCs. if RAM_OCTEON config RAM_OCTEON_DDR4 bool "Octeon III DDR4 RAM support" help - This enables support for DDR4 RAM suppoort for Octeon III. This does - not include support for Octeon CN70XX. + This enables support for DDR4 RAM suppoort for Octeon III. This does + not include support for Octeon CN70XX. endif # RAM_OCTEON diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig index 1aaf064c30c..76bd17a8874 100644 --- a/drivers/ram/stm32mp1/Kconfig +++ b/drivers/ram/stm32mp1/Kconfig @@ -6,43 +6,43 @@ config STM32MP1_DDR select SPL_RAM if SPL default y help - activate STM32MP1 DDR controller driver for STM32MP1 soc - family: support for LPDDR2, LPDDR3 and DDR3 - the SDRAM parameters for controleur and phy need to be provided - in device tree (computed by DDR tuning tools) + activate STM32MP1 DDR controller driver for STM32MP1 soc + family: support for LPDDR2, LPDDR3 and DDR3 + the SDRAM parameters for controleur and phy need to be provided + in device tree (computed by DDR tuning tools) config STM32MP1_DDR_INTERACTIVE bool "STM32MP1 DDR driver : interactive support" depends on STM32MP1_DDR help - activate interactive support in STM32MP1 DDR controller driver - used for DDR tuning tools - to enter in intercative mode type 'd' during SPL DDR driver - initialisation + activate interactive support in STM32MP1 DDR controller driver + used for DDR tuning tools + to enter in intercative mode type 'd' during SPL DDR driver + initialisation config STM32MP1_DDR_INTERACTIVE_FORCE bool "STM32MP1 DDR driver : force interactive mode" depends on STM32MP1_DDR_INTERACTIVE help - force interactive mode in STM32MP1 DDR controller driver - skip the polling of character 'd' in console - useful when SPL is loaded in sysram - directly by programmer + force interactive mode in STM32MP1 DDR controller driver + skip the polling of character 'd' in console + useful when SPL is loaded in sysram + directly by programmer config STM32MP1_DDR_TESTS bool "STM32MP1 DDR driver : tests support" depends on STM32MP1_DDR_INTERACTIVE default y help - activate test support for interactive support in - STM32MP1 DDR controller driver: command test + activate test support for interactive support in + STM32MP1 DDR controller driver: command test config STM32MP1_DDR_TUNING bool "STM32MP1 DDR driver : support of tuning" depends on STM32MP1_DDR_INTERACTIVE default y help - activate tuning command in STM32MP1 DDR interactive mode - used for DDR tuning tools - - DQ Deskew algorithm - - DQS Trimming + activate tuning command in STM32MP1 DDR interactive mode + used for DDR tuning tools + - DQ Deskew algorithm + - DQS Trimming diff --git a/drivers/reboot-mode/Kconfig b/drivers/reboot-mode/Kconfig index 72b33d71223..3fdb4218a8b 100644 --- a/drivers/reboot-mode/Kconfig +++ b/drivers/reboot-mode/Kconfig @@ -11,26 +11,26 @@ config DM_REBOOT_MODE depends on DM select DEVRES help - Enable support for reboot mode control. This will allow users to - adjust the boot process based on reboot mode parameter - passed to U-Boot. + Enable support for reboot mode control. This will allow users to + adjust the boot process based on reboot mode parameter + passed to U-Boot. config DM_REBOOT_MODE_GPIO bool "Use GPIOs as reboot mode backend" depends on DM_REBOOT_MODE help - Use GPIOs to control the reboot mode. This will allow users to boot - a device in a specific mode by using a GPIO that can be controlled - outside U-Boot. + Use GPIOs to control the reboot mode. This will allow users to boot + a device in a specific mode by using a GPIO that can be controlled + outside U-Boot. config DM_REBOOT_MODE_RTC bool "Use RTC as reboot mode backend" depends on DM_RTC depends on DM_REBOOT_MODE help - Use RTC non volatile memory to control the reboot mode. This will allow users to boot - a device in a specific mode by using a register(s) that can be controlled - outside U-Boot (e.g. Kernel). + Use RTC non volatile memory to control the reboot mode. This will allow users to boot + a device in a specific mode by using a register(s) that can be controlled + outside U-Boot (e.g. Kernel). config REBOOT_MODE_NVMEM bool "Use NVMEM reboot mode" diff --git a/drivers/remoteproc/ti_k3_r5f_rproc.c b/drivers/remoteproc/ti_k3_r5f_rproc.c index 7326f5a4b30..c5810dd0994 100644 --- a/drivers/remoteproc/ti_k3_r5f_rproc.c +++ b/drivers/remoteproc/ti_k3_r5f_rproc.c @@ -861,7 +861,7 @@ static int k3_r5f_probe(struct udevice *dev) return 0; } - ret = k3_r5f_proc_request(core); + ret = ti_sci_proc_request(&core->tsp); if (ret) return ret; diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index e7c0870c918..c851354c7a5 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -107,6 +107,15 @@ config RESET_AST2600 Say Y if you want to control reset signals of different peripherals through System Control Unit (SCU). +config RESET_AST2700 + bool "Reset controller driver for AST2700 SoCs" + depends on DM_RESET && ASPEED_AST2700 + default y if ASPEED_AST2700 + help + Support for reset controller on AST2700 SoC. + Say Y if you want to control reset signals of different peripherals + through System Control Unit (SCU). + config RESET_ROCKCHIP bool "Reset controller driver for Rockchip SoCs" depends on DM_RESET && ARCH_ROCKCHIP && CLK diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 2c83f858895..3fce96509cd 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o obj-$(CONFIG_RESET_AST2500) += reset-ast2500.o obj-$(CONFIG_RESET_AST2600) += reset-ast2600.o +obj-$(CONFIG_RESET_AST2700) += reset-ast2700.o obj-$(CONFIG_$(PHASE_)RESET_ROCKCHIP) += reset-rockchip.o rst-rk3506.o rst-rk3528.o rst-rk3576.o rst-rk3588.o obj-$(CONFIG_RESET_MESON) += reset-meson.o obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o diff --git a/drivers/reset/reset-ast2700.c b/drivers/reset/reset-ast2700.c new file mode 100644 index 00000000000..2dd9e36cc0a --- /dev/null +++ b/drivers/reset/reset-ast2700.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#include <asm/io.h> +#include <dm.h> +#include <linux/err.h> +#include <reset.h> +#include <reset-uclass.h> + +/* Offset of the modrst register block within the SCU. */ +#define AST2700_RESET_OFFSET 0x200 + +struct ast2700_reset_priv { + void __iomem *base; +}; + +static int ast2700_reset_assert(struct reset_ctl *reset_ctl) +{ + struct ast2700_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + if (reset_ctl->id < 32) + writel(BIT(reset_ctl->id), priv->base); + else + writel(BIT(reset_ctl->id - 32), priv->base + 0x20); + + return 0; +} + +static int ast2700_reset_deassert(struct reset_ctl *reset_ctl) +{ + struct ast2700_reset_priv *priv = dev_get_priv(reset_ctl->dev); + + if (reset_ctl->id < 32) + writel(BIT(reset_ctl->id), priv->base + 0x04); + else + writel(BIT(reset_ctl->id - 32), priv->base + 0x24); + + return 0; +} + +static int ast2700_reset_status(struct reset_ctl *reset_ctl) +{ + struct ast2700_reset_priv *priv = dev_get_priv(reset_ctl->dev); + int status; + + if (reset_ctl->id < 32) + status = BIT(reset_ctl->id) & readl(priv->base); + else + status = BIT(reset_ctl->id - 32) & readl(priv->base + 0x20); + + return !!status; +} + +static int ast2700_reset_probe(struct udevice *dev) +{ + struct ast2700_reset_priv *priv = dev_get_priv(dev); + void __iomem *scu_base; + + scu_base = dev_read_addr_ptr(dev); + if (!scu_base) + return -EINVAL; + + priv->base = scu_base + AST2700_RESET_OFFSET; + + return 0; +} + +static const struct reset_ops ast2700_reset_ops = { + .rst_assert = ast2700_reset_assert, + .rst_deassert = ast2700_reset_deassert, + .rst_status = ast2700_reset_status, +}; + +U_BOOT_DRIVER(ast2700_reset) = { + .name = "ast2700_reset", + .id = UCLASS_RESET, + .probe = ast2700_reset_probe, + .ops = &ast2700_reset_ops, + .priv_auto = sizeof(struct ast2700_reset_priv), +}; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 3b74770b18a..6fb3019a644 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -44,8 +44,8 @@ config VPL_DM_RTC config RTC_ENABLE_32KHZ_OUTPUT bool "Enable RTC 32Khz output" help - Some real-time clocks support the output of 32kHz square waves (such as ds3231), - the config symbol choose Real Time Clock device 32Khz output feature. + Some real-time clocks support the output of 32kHz square waves (such as ds3231), + the config symbol choose Real Time Clock device 32Khz output feature. config RTC_ARMADA38X bool "Enable Armada 38x Marvell SoC RTC" diff --git a/drivers/rtc/mcfrtc.c b/drivers/rtc/mcfrtc.c index 9708971c5c4..23ffb2b31a1 100644 --- a/drivers/rtc/mcfrtc.c +++ b/drivers/rtc/mcfrtc.c @@ -73,7 +73,7 @@ int rtc_set(struct rtc_time *tmp) days += month_days[i]; if (i == 1) - days += isleap(i); + days += isleap(tmp->tm_year); } days += tmp->tm_mday - 1; diff --git a/drivers/rtc/sandbox_rtc.c b/drivers/rtc/sandbox_rtc.c index 4404501c2f6..1ade5d50b23 100644 --- a/drivers/rtc/sandbox_rtc.c +++ b/drivers/rtc/sandbox_rtc.c @@ -73,7 +73,7 @@ static int sandbox_rtc_get_name(const struct udevice *dev, char *out_name) return acpi_copy_name(out_name, "RTCC"); } -struct acpi_ops sandbox_rtc_acpi_ops = { +static const struct acpi_ops sandbox_rtc_acpi_ops = { .get_name = sandbox_rtc_get_name, }; #endif diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index c6e457572b1..e221800d5d0 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -759,11 +759,11 @@ config MVEBU_A3700_UART config MCFUART bool "Freescale ColdFire UART support" depends on M68K - help - Choose this option to add support for UART driver on the ColdFire - SoC's family. The serial communication channel provides a full-duplex - asynchronous/synchronous receiver and transmitter deriving an - operating frequency from the internal bus clock or an external clock. + help + Choose this option to add support for UART driver on the ColdFire + SoC's family. The serial communication channel provides a full-duplex + asynchronous/synchronous receiver and transmitter deriving an + operating frequency from the internal bus clock or an external clock. config MXC_UART bool "IMX serial port support" @@ -1027,9 +1027,9 @@ config OCTEON_SERIAL_BOOTCMD select SYS_CONSOLE_IS_IN_ENV select CONSOLE_MUX help - This driver supports remote input over the PCIe bus from a host - to U-Boot for entering commands. It is utilized by the host - commands 'oct-remote-load' and 'oct-remote-bootcmd'. + This driver supports remote input over the PCIe bus from a host + to U-Boot for entering commands. It is utilized by the host + commands 'oct-remote-load' and 'oct-remote-bootcmd'. config OCTEON_SERIAL_PCIE_CONSOLE bool "MIPS Octeon PCIe remote console" diff --git a/drivers/serial/serial_lpuart.c b/drivers/serial/serial_lpuart.c index 3f5fadfc80a..955f1c96407 100644 --- a/drivers/serial/serial_lpuart.c +++ b/drivers/serial/serial_lpuart.c @@ -519,8 +519,7 @@ static int lpuart_serial_probe(struct udevice *dev) static int lpuart_serial_of_to_plat(struct udevice *dev) { struct lpuart_serial_plat *plat = dev_get_plat(dev); - const void *blob = gd->fdt_blob; - int node = dev_of_offset(dev); + ofnode node = dev_ofnode(dev); fdt_addr_t addr; addr = dev_read_addr(dev); @@ -530,18 +529,18 @@ static int lpuart_serial_of_to_plat(struct udevice *dev) plat->reg = (void *)addr; plat->flags = dev_get_driver_data(dev); - if (fdtdec_get_bool(blob, node, "little-endian")) + if (ofnode_read_bool(node, "little-endian")) plat->flags &= ~LPUART_FLAG_REGMAP_ENDIAN_BIG; - if (!fdt_node_check_compatible(blob, node, "fsl,ls1021a-lpuart")) + if (ofnode_device_is_compatible(node, "fsl,ls1021a-lpuart")) plat->devtype = DEV_LS1021A; - else if (!fdt_node_check_compatible(blob, node, "fsl,imx7ulp-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imx7ulp-lpuart")) plat->devtype = DEV_MX7ULP; - else if (!fdt_node_check_compatible(blob, node, "fsl,vf610-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,vf610-lpuart")) plat->devtype = DEV_VF610; - else if (!fdt_node_check_compatible(blob, node, "fsl,imx8qm-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imx8qm-lpuart")) plat->devtype = DEV_IMX8; - else if (!fdt_node_check_compatible(blob, node, "fsl,imxrt-lpuart")) + else if (ofnode_device_is_compatible(node, "fsl,imxrt-lpuart")) plat->devtype = DEV_IMXRT; return 0; diff --git a/drivers/smem/Kconfig b/drivers/smem/Kconfig index e5d7dcc81b1..5b68ad5f10f 100644 --- a/drivers/smem/Kconfig +++ b/drivers/smem/Kconfig @@ -4,22 +4,22 @@ menuconfig SMEM if SMEM config SANDBOX_SMEM - bool "Sandbox Shared Memory Manager (SMEM)" - depends on SANDBOX && DM - help - enable SMEM support for sandbox. This is an emulation of a real SMEM - manager. - The sandbox driver allocates a shared memory from the heap and - initialzies it on start. + bool "Sandbox Shared Memory Manager (SMEM)" + depends on SANDBOX && DM + help + enable SMEM support for sandbox. This is an emulation of a real SMEM + manager. + The sandbox driver allocates a shared memory from the heap and + initialzies it on start. config MSM_SMEM - bool "Qualcomm Shared Memory Manager (SMEM)" - depends on DM - depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX - select DEVRES - help - Enable support for the Qualcomm Shared Memory Manager. - The driver provides an interface to items in a heap shared among all - processors in a Qualcomm platform. + bool "Qualcomm Shared Memory Manager (SMEM)" + depends on DM + depends on ARCH_SNAPDRAGON || ARCH_IPQ40XX + select DEVRES + help + Enable support for the Qualcomm Shared Memory Manager. + The driver provides an interface to items in a heap shared among all + processors in a Qualcomm platform. endif # menu "SMEM Support" diff --git a/drivers/soc/soc_xilinx_zynqmp.c b/drivers/soc/soc_xilinx_zynqmp.c index 4abc73013eb..0e13e230914 100644 --- a/drivers/soc/soc_xilinx_zynqmp.c +++ b/drivers/soc/soc_xilinx_zynqmp.c @@ -358,7 +358,9 @@ static int soc_xilinx_zynqmp_detect_machine(struct udevice *dev, u32 idcode, } else if (device->variants & ZYNQMP_VARIANT_DR_SE) { strlcat(priv->machine, "dr_SE", sizeof(priv->machine)); } else if (device->variants & ZYNQMP_VARIANT_TEG) { - strlcat(priv->machine, "teg", sizeof(priv->machine)); + /* Devices with TEG variant might be TEG or TCG family */ + strlcat(priv->machine, (idcode2 & EFUSE_GPU_DIS_MASK) ? + "tcg" : "teg", sizeof(priv->machine)); } return 0; diff --git a/drivers/soc/ti/Kconfig b/drivers/soc/ti/Kconfig index 36129cb72f6..9734bf32cb0 100644 --- a/drivers/soc/ti/Kconfig +++ b/drivers/soc/ti/Kconfig @@ -21,8 +21,8 @@ config TI_KEYSTONE_SERDES bool "Keystone SerDes driver for ethernet" depends on ARCH_KEYSTONE help - SerDes driver for Keystone SoC used for ethernet support on TI - K2 platforms. + SerDes driver for Keystone SoC used for ethernet support on TI + K2 platforms. config TI_PRUSS bool "Support for TI's K3 based Pruss driver" diff --git a/drivers/sound/da7219.c b/drivers/sound/da7219.c index 5b9b3f65263..d1d03ae91d4 100644 --- a/drivers/sound/da7219.c +++ b/drivers/sound/da7219.c @@ -170,7 +170,7 @@ static int da7219_acpi_setup_nhlt(const struct udevice *dev, } #endif -struct acpi_ops da7219_acpi_ops = { +static const struct acpi_ops da7219_acpi_ops = { #ifdef CONFIG_ACPIGEN .fill_ssdt = da7219_acpi_fill_ssdt, #ifdef CONFIG_X86 diff --git a/drivers/sound/max98357a.c b/drivers/sound/max98357a.c index da56ffdd6bb..47978d4fe27 100644 --- a/drivers/sound/max98357a.c +++ b/drivers/sound/max98357a.c @@ -136,7 +136,7 @@ static int max98357a_acpi_setup_nhlt(const struct udevice *dev, } #endif -struct acpi_ops max98357a_acpi_ops = { +static const struct acpi_ops max98357a_acpi_ops = { #ifdef CONFIG_ACPIGEN .fill_ssdt = max98357a_acpi_fill_ssdt, #ifdef CONFIG_X86 diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index cfbedd64c4c..007ad5e7733 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -2,10 +2,10 @@ menuconfig SPI bool "SPI Support" help The "Serial Peripheral Interface" is a low level synchronous - protocol. Chips that support SPI can have data transfer rates - up to several tens of Mbit/sec. Chips are addressed with a - controller and a chipselect. Most SPI slaves don't support - dynamic device discovery; some are even write-only or read-only. + protocol. Chips that support SPI can have data transfer rates + up to several tens of Mbit/sec. Chips are addressed with a + controller and a chipselect. Most SPI slaves don't support + dynamic device discovery; some are even write-only or read-only. SPI is widely used by microcontrollers to talk with sensors, eeprom and flash memory, codecs and various other controller @@ -200,11 +200,11 @@ config CADENCE_XSPI by using the Auto Command work mode. config CF_SPI - bool "ColdFire SPI driver" - depends on M68K - help - Enable the ColdFire SPI driver. This driver can be used on - some m68k SoCs. + bool "ColdFire SPI driver" + depends on M68K + help + Enable the ColdFire SPI driver. This driver can be used on + some m68k SoCs. config CV1800B_SPIF bool "Sophgo cv1800b SPI Flash Controller driver" @@ -352,7 +352,7 @@ config MTK_SNOR select DEVRES help Enable the Mediatek SPINOR controller driver. This driver has - better read/write performance with NOR. + better read/write performance with NOR. config MTK_SNFI_SPI bool "Mediatek SPI memory controller driver" @@ -544,11 +544,11 @@ config SPI_SIFIVE config SOFT_SPI bool "Soft SPI driver" help - Enable Soft SPI driver. This driver is to use GPIO simulate - the SPI protocol. + Enable Soft SPI driver. This driver is to use GPIO simulate + the SPI protocol. config SPI_SN_F_OSPI - tristate "Socionext F_OSPI SPI flash controller" + bool "Socionext F_OSPI SPI flash controller" select SPI_MEM help This enables support for the Socionext F_OSPI controller @@ -673,8 +673,8 @@ config ZYNQMP_GQSPI config SPI_STACKED_PARALLEL bool "Enable support for stacked or parallel memories" help - Enable support for stacked/or parallel memories. This functionality - may appear on Xilinx hardware. By default this is disabled. + Enable support for stacked/or parallel memories. This functionality + may appear on Xilinx hardware. By default this is disabled. endif # if DM_SPI diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c index ca29cfd7c88..0186b01ad9a 100644 --- a/drivers/spi/spi-aspeed-smc.c +++ b/drivers/spi/spi-aspeed-smc.c @@ -53,18 +53,20 @@ struct aspeed_spi_regs { u32 dma_len; /* 0x8c DMA Length Register */ u32 dma_checksum; /* 0x90 Checksum Calculation Result */ u32 timings[ASPEED_SPI_MAX_CS]; /* 0x94 Read Timing Compensation */ + u32 _reserved3[83]; /* 0xA8 - 0x1F0 */ + u32 val_kept_wdt; /* 0x1F4 Value Kept WDT */ }; struct aspeed_spi_plat { u8 max_cs; - void __iomem *ahb_base; /* AHB address base for all flash devices. */ + uintptr_t ahb_base; /* AHB address base for all flash devices. */ fdt_size_t ahb_sz; /* Overall AHB window size for all flash device. */ u32 hclk_rate; /* AHB clock rate */ }; struct aspeed_spi_flash { - void __iomem *ahb_base; - u32 ahb_decoded_sz; + uintptr_t ahb_base; + size_t ahb_decoded_sz; u32 ce_ctrl_user; u32 ce_ctrl_read; u32 max_freq; @@ -84,9 +86,9 @@ struct aspeed_spi_info { u32 min_decoded_sz; u32 clk_ctrl_mask; void (*set_4byte)(struct udevice *bus, u32 cs); - u32 (*segment_start)(struct udevice *bus, u32 reg); - u32 (*segment_end)(struct udevice *bus, u32 reg); - u32 (*segment_reg)(u32 start, u32 end); + uintptr_t (*segment_start)(struct udevice *bus, u32 reg); + uintptr_t (*segment_end)(struct udevice *bus, u32 reg); + u32 (*segment_reg)(uintptr_t start, uintptr_t end); int (*adjust_decoded_sz)(struct udevice *bus); u32 (*get_clk_setting)(struct udevice *dev, uint hz); }; @@ -118,30 +120,30 @@ static u32 aspeed_spi_get_io_mode(u32 bus_width) } } -static u32 ast2400_spi_segment_start(struct udevice *bus, u32 reg) +static uintptr_t ast2400_spi_segment_start(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 start_offset = ((reg >> 16) & 0xff) << 23; + uintptr_t start_offset = ((reg >> 16) & 0xff) << 23; if (start_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + start_offset; + return plat->ahb_base + start_offset; } -static u32 ast2400_spi_segment_end(struct udevice *bus, u32 reg) +static uintptr_t ast2400_spi_segment_end(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 end_offset = ((reg >> 24) & 0xff) << 23; + uintptr_t end_offset = ((reg >> 24) & 0xff) << 23; /* Meaningless end_offset, set to physical ahb base. */ if (end_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + end_offset; + return plat->ahb_base + end_offset; } -static u32 ast2400_spi_segment_reg(u32 start, u32 end) +static u32 ast2400_spi_segment_reg(uintptr_t start, uintptr_t end) { if (start == end) return 0; @@ -206,30 +208,30 @@ static u32 ast2400_get_clk_setting(struct udevice *dev, uint max_hz) return hclk_div; } -static u32 ast2500_spi_segment_start(struct udevice *bus, u32 reg) +static uintptr_t ast2500_spi_segment_start(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 start_offset = ((reg >> 16) & 0xff) << 23; + uintptr_t start_offset = ((reg >> 16) & 0xff) << 23; if (start_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + start_offset; + return plat->ahb_base + start_offset; } -static u32 ast2500_spi_segment_end(struct udevice *bus, u32 reg) +static uintptr_t ast2500_spi_segment_end(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 end_offset = ((reg >> 24) & 0xff) << 23; + uintptr_t end_offset = ((reg >> 24) & 0xff) << 23; /* Meaningless end_offset, set to physical ahb base. */ if (end_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + end_offset; + return plat->ahb_base + end_offset; } -static u32 ast2500_spi_segment_reg(u32 start, u32 end) +static u32 ast2500_spi_segment_reg(uintptr_t start, uintptr_t end) { if (start == end) return 0; @@ -346,30 +348,30 @@ end: return hclk_div; } -static u32 ast2600_spi_segment_start(struct udevice *bus, u32 reg) +static uintptr_t ast2600_spi_segment_start(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 start_offset = (reg << 16) & 0x0ff00000; + uintptr_t start_offset = (reg << 16) & 0x0ff00000; if (start_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + start_offset; + return plat->ahb_base + start_offset; } -static u32 ast2600_spi_segment_end(struct udevice *bus, u32 reg) +static uintptr_t ast2600_spi_segment_end(struct udevice *bus, u32 reg) { struct aspeed_spi_plat *plat = dev_get_plat(bus); - u32 end_offset = reg & 0x0ff00000; + uintptr_t end_offset = reg & 0x0ff00000; /* Meaningless end_offset, set to physical ahb base. */ if (end_offset == 0) - return (u32)plat->ahb_base; + return plat->ahb_base; - return (u32)plat->ahb_base + end_offset + 0x100000; + return plat->ahb_base + end_offset + 0x100000; } -static u32 ast2600_spi_segment_reg(u32 start, u32 end) +static u32 ast2600_spi_segment_reg(uintptr_t start, uintptr_t end) { if (start == end) return 0; @@ -473,6 +475,70 @@ static u32 ast2600_get_clk_setting(struct udevice *dev, uint max_hz) return hclk_div; } +static uintptr_t ast2700_spi_segment_start(struct udevice *bus, u32 reg) +{ + struct aspeed_spi_plat *plat = dev_get_plat(bus); + uintptr_t start_offset = (reg & 0x0000ffff) << 16; + + if (start_offset == 0) + return plat->ahb_base; + + return plat->ahb_base + start_offset; +} + +static uintptr_t ast2700_spi_segment_end(struct udevice *bus, u32 reg) +{ + struct aspeed_spi_plat *plat = dev_get_plat(bus); + uintptr_t end_offset = reg & 0xffff0000; + + /* Meaningless end_offset, set to physical ahb base. */ + if (end_offset == 0) + return plat->ahb_base; + + return plat->ahb_base + end_offset; +} + +static u32 ast2700_spi_segment_reg(uintptr_t start, uintptr_t end) +{ + if (start == end) + return 0; + + return (((start >> 16) & 0x7fff) | ((end + 1) & 0x7fff0000)); +} + +static void ast2700_spi_chip_set_4byte(struct udevice *bus, u32 cs) +{ + struct aspeed_spi_priv *priv = dev_get_priv(bus); + u32 reg_val; + + reg_val = readl(&priv->regs->ctrl); + reg_val |= 0x11 << cs; + writel(reg_val, &priv->regs->ctrl); + + reg_val = readl(&priv->regs->val_kept_wdt); + reg_val |= (0x11 << 4) << cs; + writel(reg_val, &priv->regs->val_kept_wdt); +} + +static int ast2700_adjust_decoded_size(struct udevice *bus) +{ + struct aspeed_spi_plat *plat = dev_get_plat(bus); + struct aspeed_spi_priv *priv = dev_get_priv(bus); + struct aspeed_spi_flash *flashes = &priv->flashes[0]; + int ret; + int cs; + + /* Close unused CS. */ + for (cs = priv->num_cs; cs < plat->max_cs; cs++) + flashes[cs].ahb_decoded_sz = 0; + + ret = aspeed_spi_trim_decoded_size(bus); + if (ret != 0) + return ret; + + return 0; +} + /* * As the flash size grows up, we need to trim some decoded * size if needed for the sake of conforming the maximum @@ -512,12 +578,12 @@ static int aspeed_spi_trim_decoded_size(struct udevice *bus) return 0; } -static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, +static int aspeed_spi_read_from_ahb(uintptr_t ahb_base, void *buf, size_t len) { size_t offset = 0; - if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && + if (IS_ALIGNED(ahb_base, sizeof(uintptr_t)) && IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { readsl(ahb_base, buf, len >> 2); offset = len & ~0x3; @@ -529,12 +595,12 @@ static int aspeed_spi_read_from_ahb(void __iomem *ahb_base, void *buf, return 0; } -static int aspeed_spi_write_to_ahb(void __iomem *ahb_base, const void *buf, +static int aspeed_spi_write_to_ahb(uintptr_t ahb_base, const void *buf, size_t len) { size_t offset = 0; - if (IS_ALIGNED((uintptr_t)ahb_base, sizeof(uintptr_t)) && + if (IS_ALIGNED(ahb_base, sizeof(uintptr_t)) && IS_ALIGNED((uintptr_t)buf, sizeof(uintptr_t))) { writesl(ahb_base, buf, len >> 2); offset = len & ~0x3; @@ -589,7 +655,7 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave, struct aspeed_spi_priv *priv = dev_get_priv(bus); struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(slave->dev); u32 cs = slave_plat->cs[0]; - u32 ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; + uintptr_t ce_ctrl_reg = (uintptr_t)&priv->regs->ce_ctrl[cs]; u32 ce_ctrl_val; struct aspeed_spi_flash *flash = &priv->flashes[cs]; u8 dummy_data[16] = {0}; @@ -602,7 +668,7 @@ static int aspeed_spi_exec_op_user_mode(struct spi_slave *slave, op->data.nbytes, op->data.buswidth); if (priv->info == &ast2400_spi_info) - ce_ctrl_reg = (u32)&priv->regs->ctrl; + ce_ctrl_reg = (uintptr_t)&priv->regs->ctrl; /* * Set controller to 4-byte address mode @@ -670,7 +736,7 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) u32 i; u32 cs = slave_plat->cs[0]; u32 cmd_io_conf; - u32 ce_ctrl_reg; + uintptr_t ce_ctrl_reg; if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) { /* @@ -681,9 +747,9 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) return -EOPNOTSUPP; } - ce_ctrl_reg = (u32)&priv->regs->ce_ctrl[cs]; + ce_ctrl_reg = (uintptr_t)&priv->regs->ce_ctrl[cs]; if (info == &ast2400_spi_info) - ce_ctrl_reg = (u32)&priv->regs->ctrl; + ce_ctrl_reg = (uintptr_t)&priv->regs->ctrl; if (desc->info.length > 0x1000000) priv->info->set_4byte(bus, cs); @@ -693,7 +759,7 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc) priv->flashes[cs].ahb_decoded_sz = desc->info.length; for (i = 0; i < priv->num_cs; i++) { - dev_dbg(dev, "cs: %d, sz: 0x%x\n", i, + dev_dbg(dev, "cs: %d, sz: 0x%zx\n", i, priv->flashes[cs].ahb_decoded_sz); } @@ -728,7 +794,7 @@ static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u32 cs = slave_plat->cs[0]; int ret; - dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%x\n", + dev_dbg(dev, "read op:0x%x, addr:0x%llx, len:0x%zx\n", desc->info.op_tmpl.cmd.opcode, offs, len); if (priv->flashes[cs].ahb_decoded_sz < offs + len || @@ -738,7 +804,10 @@ static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, if (ret != 0) return 0; } else { - memcpy_fromio(buf, priv->flashes[cs].ahb_base + offs, len); + memcpy_fromio(buf, + (void __iomem *)(priv->flashes[cs].ahb_base + + (uintptr_t)offs), + len); } return len; @@ -783,19 +852,19 @@ static void aspeed_spi_decoded_range_set(struct udevice *bus) struct aspeed_spi_plat *plat = dev_get_plat(bus); struct aspeed_spi_priv *priv = dev_get_priv(bus); u32 decoded_reg_val; - u32 start_addr, end_addr; + uintptr_t start_addr, end_addr; u32 cs; for (cs = 0; cs < plat->max_cs; cs++) { - start_addr = (u32)priv->flashes[cs].ahb_base; - end_addr = (u32)priv->flashes[cs].ahb_base + + start_addr = priv->flashes[cs].ahb_base; + end_addr = priv->flashes[cs].ahb_base + priv->flashes[cs].ahb_decoded_sz; decoded_reg_val = priv->info->segment_reg(start_addr, end_addr); writel(decoded_reg_val, &priv->regs->segment_addr[cs]); - dev_dbg(bus, "cs: %d, decoded_reg: 0x%x, start: 0x%x, end: 0x%x\n", + dev_dbg(bus, "cs: %d, decoded_reg: 0x%x, start: 0x%lx, end: 0x%lx\n", cs, decoded_reg_val, start_addr, end_addr); } } @@ -851,13 +920,13 @@ static int aspeed_spi_decoded_ranges_sanity(struct udevice *bus) * address base are monotonic increasing with CE#. */ for (cs = plat->max_cs - 1; cs > 0; cs--) { - if ((u32)priv->flashes[cs].ahb_base != 0 && - (u32)priv->flashes[cs].ahb_base < - (u32)priv->flashes[cs - 1].ahb_base + + if (priv->flashes[cs].ahb_base != 0 && + priv->flashes[cs].ahb_base < + priv->flashes[cs - 1].ahb_base + priv->flashes[cs - 1].ahb_decoded_sz) { - dev_err(bus, "decoded range overlay 0x%08x 0x%08x\n", - (u32)priv->flashes[cs].ahb_base, - (u32)priv->flashes[cs - 1].ahb_base); + dev_err(bus, "decoded range overlay 0x%08lx 0x%08lx\n", + priv->flashes[cs].ahb_base, + priv->flashes[cs - 1].ahb_base); return -EINVAL; } } @@ -895,14 +964,13 @@ static int aspeed_spi_read_fixed_decoded_ranges(struct udevice *bus) return ret; for (i = 0; i < count; i++) { - priv->flashes[ranges[i].cs].ahb_base = - (void __iomem *)ranges[i].ahb_base; + priv->flashes[ranges[i].cs].ahb_base = ranges[i].ahb_base; priv->flashes[ranges[i].cs].ahb_decoded_sz = ranges[i].sz; } for (i = 0; i < plat->max_cs; i++) { - dev_dbg(bus, "ahb_base: 0x%p, size: 0x%08x\n", + dev_dbg(bus, "ahb_base: 0x%lx, size: 0x%08zx\n", priv->flashes[i].ahb_base, priv->flashes[i].ahb_decoded_sz); } @@ -1063,6 +1131,32 @@ static const struct aspeed_spi_info ast2600_spi_info = { .get_clk_setting = ast2600_get_clk_setting, }; +static const struct aspeed_spi_info ast2700_fmc_info = { + .io_mode_mask = 0xf0000000, + .max_bus_width = 4, + .min_decoded_sz = 0x10000, + .clk_ctrl_mask = 0x0f000f00, + .set_4byte = ast2700_spi_chip_set_4byte, + .segment_start = ast2700_spi_segment_start, + .segment_end = ast2700_spi_segment_end, + .segment_reg = ast2700_spi_segment_reg, + .adjust_decoded_sz = ast2700_adjust_decoded_size, + .get_clk_setting = ast2600_get_clk_setting, +}; + +static const struct aspeed_spi_info ast2700_spi_info = { + .io_mode_mask = 0xf0000000, + .max_bus_width = 4, + .min_decoded_sz = 0x10000, + .clk_ctrl_mask = 0x0f000f00, + .set_4byte = ast2700_spi_chip_set_4byte, + .segment_start = ast2700_spi_segment_start, + .segment_end = ast2700_spi_segment_end, + .segment_reg = ast2700_spi_segment_reg, + .adjust_decoded_sz = ast2700_adjust_decoded_size, + .get_clk_setting = ast2600_get_clk_setting, +}; + static int aspeed_spi_claim_bus(struct udevice *dev) { struct udevice *bus = dev->parent; @@ -1129,7 +1223,8 @@ static int apseed_spi_of_to_plat(struct udevice *bus) return -EINVAL; } - plat->ahb_base = devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahb_sz); + plat->ahb_base = + (uintptr_t)devfdt_get_addr_size_index_ptr(bus, 1, &plat->ahb_sz); if (!plat->ahb_base) { dev_err(bus, "wrong AHB base\n"); return -EINVAL; @@ -1147,8 +1242,8 @@ static int apseed_spi_of_to_plat(struct udevice *bus) plat->hclk_rate = clk_get_rate(&hclk); - dev_dbg(bus, "ctrl_base = 0x%x, ahb_base = 0x%p, size = 0x%llx\n", - (u32)priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz); + dev_dbg(bus, "ctrl_base = 0x%p, ahb_base = 0x%lx, size = 0x%llx\n", + priv->regs, plat->ahb_base, (fdt64_t)plat->ahb_sz); dev_dbg(bus, "hclk = %dMHz, max_cs = %d\n", plat->hclk_rate / 1000000, plat->max_cs); @@ -1199,6 +1294,8 @@ static const struct udevice_id aspeed_spi_ids[] = { { .compatible = "aspeed,ast2500-spi", .data = (ulong)&ast2500_spi_info, }, { .compatible = "aspeed,ast2600-fmc", .data = (ulong)&ast2600_fmc_info, }, { .compatible = "aspeed,ast2600-spi", .data = (ulong)&ast2600_spi_info, }, + { .compatible = "aspeed,ast2700-fmc", .data = (ulong)&ast2700_fmc_info, }, + { .compatible = "aspeed,ast2700-spi", .data = (ulong)&ast2700_spi_info, }, { } }; diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig index ab4878ebae4..e28fd9af1d0 100644 --- a/drivers/spmi/Kconfig +++ b/drivers/spmi/Kconfig @@ -3,7 +3,7 @@ menu "SPMI support" config SPMI bool "Enable SPMI bus support" depends on DM - ---help--- + help Select this to enable to support SPMI bus. SPMI (System Power Management Interface) bus is used to connect PMIC devices on various SoCs. @@ -11,13 +11,13 @@ config SPMI config SPMI_MSM bool "Support Qualcomm SPMI bus" depends on SPMI - ---help--- + help Support SPMI bus implementation found on Qualcomm Snapdragon SoCs. config SPMI_SANDBOX bool "Support for Sandbox SPMI bus" depends on SPMI - ---help--- + help Demo SPMI bus implementation. Emulates part of PM8916 as single - slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3. + slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3. endmenu diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 90f740f51d4..16ef434a8d9 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -49,14 +49,6 @@ config SYSRESET_CMD_RESET help Enable sysreset implementation of the reset command. -config SYSRESET_CMD_RESET_ARGS - bool "Enable reset command to take arguments" - help - Pass on the arguments received by the 'reset' command to the - sysreset driver(s). The sysreset driver(s) may make use of the - additional arguments for implementing arch/board specific - functionality. - if CMD_POWEROFF config SYSRESET_CMD_POWEROFF @@ -301,13 +293,6 @@ config SYSRESET_RAA215300 help Add support for the system reboot via the Renesas RAA215300 PMIC. -config SYSRESET_QCOM_PSCI - bool "Support reset to EDL for Qualcomm SoCs via PSCI" - depends on ARM_SMCCC - help - Add support for the reset to EDL (Emergency Download) on Qualcomm - SoCs via PSCI. - config SYSRESET_QCOM_PSHOLD bool "Support sysreset for Qualcomm SoCs via PSHOLD" help diff --git a/drivers/sysreset/Makefile b/drivers/sysreset/Makefile index b5b99235b6e..d18a5d52360 100644 --- a/drivers/sysreset/Makefile +++ b/drivers/sysreset/Makefile @@ -30,7 +30,6 @@ obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o obj-$(CONFIG_$(PHASE_)SYSRESET_AT91) += sysreset_at91.o obj-$(CONFIG_$(PHASE_)SYSRESET_X86) += sysreset_x86.o obj-$(CONFIG_SYSRESET_RAA215300) += sysreset_raa215300.o -obj-$(CONFIG_SYSRESET_QCOM_PSCI) += sysreset_qcom-psci.o obj-$(CONFIG_SYSRESET_QCOM_PSHOLD) += sysreset_qcom-pshold.o obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o obj-$(CONFIG_SYSRESET_QEMU_VIRT_CTRL) += sysreset_qemu_virt_ctrl.o diff --git a/drivers/sysreset/sysreset-uclass.c b/drivers/sysreset/sysreset-uclass.c index f25e09e9cd0..536ac727142 100644 --- a/drivers/sysreset/sysreset-uclass.c +++ b/drivers/sysreset/sysreset-uclass.c @@ -32,18 +32,6 @@ int sysreset_request(struct udevice *dev, enum sysreset_t type) return ops->request(dev, type); } -#if IS_ENABLED(CONFIG_SYSRESET_CMD_RESET_ARGS) -int sysreset_request_arg(struct udevice *dev, int argc, char * const argv[]) -{ - struct sysreset_ops *ops = sysreset_get_ops(dev); - - if (!ops->request_arg) - return -ENOSYS; - - return ops->request_arg(dev, argc, argv); -} -#endif /* CONFIG_SYSRESET_CMD_RESET_ARGS */ - int sysreset_get_status(struct udevice *dev, char *buf, int size) { struct sysreset_ops *ops = sysreset_get_ops(dev); @@ -83,26 +71,6 @@ int sysreset_walk(enum sysreset_t type) return ret; } -#if IS_ENABLED(CONFIG_SYSRESET_CMD_RESET_ARGS) -int sysreset_walk_arg(int argc, char * const argv[]) -{ - struct udevice *dev; - int ret = -ENOSYS; - - while (ret != -EINPROGRESS && ret != -EPROTONOSUPPORT) { - for (uclass_first_device(UCLASS_SYSRESET, &dev); - dev; - uclass_next_device(&dev)) { - ret = sysreset_request_arg(dev, argc, argv); - if (ret == -EINPROGRESS || ret == -EPROTONOSUPPORT) - break; - } - } - - return ret; -} -#endif /* CONFIG_SYSRESET_CMD_RESET_ARGS */ - int sysreset_get_last_walk(void) { struct udevice *dev; @@ -164,11 +132,6 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) printf("resetting ...\n"); mdelay(100); -#if IS_ENABLED(CONFIG_SYSRESET_CMD_RESET_ARGS) - if (argc > 1 && sysreset_walk_arg(argc, argv) == -EINPROGRESS) - return 0; -#endif - sysreset_walk_halt(reset_type); return 0; diff --git a/drivers/sysreset/sysreset_qcom-psci.c b/drivers/sysreset/sysreset_qcom-psci.c deleted file mode 100644 index 3627bbf5c82..00000000000 --- a/drivers/sysreset/sysreset_qcom-psci.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2017 Masahiro Yamada <[email protected]> - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -#include <dm.h> -#include <sysreset.h> -#include <asm/system.h> -#include <linux/errno.h> -#include <linux/psci.h> -#include <asm/psci.h> - -static int qcom_psci_sysreset_get_status(struct udevice *dev, char *buf, int size) -{ - return -EOPNOTSUPP; -} - -static int qcom_psci_sysreset_request_arg(struct udevice *dev, int argc, - char * const argv[]) -{ - if (!strncasecmp(argv[1], "-edl", 4)) { - /* Supported in qcs9100, qcs8300, sc7280, qcs615 */ - if (psci_features(ARM_PSCI_1_1_FN64_SYSTEM_RESET2) == - ARM_PSCI_RET_SUCCESS) { - psci_system_reset2(0, 1); - return -EINPROGRESS; - } - printf("PSCI SYSTEM_RESET2 not supported\n"); - } - - return -EPROTONOSUPPORT; -} - -static struct sysreset_ops qcom_psci_sysreset_ops = { - .request_arg = qcom_psci_sysreset_request_arg, - .get_status = qcom_psci_sysreset_get_status, -}; - -U_BOOT_DRIVER(qcom_psci_sysreset) = { - .name = "qcom_psci-sysreset", - .id = UCLASS_SYSRESET, - .ops = &qcom_psci_sysreset_ops, - .flags = DM_FLAG_PRE_RELOC, -}; diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index 33a82ca3bf1..9ad0d699850 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -13,9 +13,9 @@ config IMX_THERMAL depends on MX6 || MX7 help Support for Temperature Monitor (TEMPMON) found on Freescale i.MX SoCs. - It supports one critical trip point and one passive trip point. The - cpufreq is used as the cooling device to throttle CPUs when the - passive trip is crossed. + It supports one critical trip point and one passive trip point. The + cpufreq is used as the cooling device to throttle CPUs when the + passive trip is crossed. config IMX_SCU_THERMAL bool "Temperature sensor driver for NXP i.MX8" @@ -29,7 +29,7 @@ config IMX_SCU_THERMAL config IMX_TMU bool "Thermal Management Unit driver for NXP i.MX8M / i.MX93 and QorIQ" depends on ARCH_IMX8M || IMX93 || FSL_LAYERSCAPE - help + help Support for the NXP Thermal Management Unit (TMU) sensors on i.MX8M, i.MX93 and on QorIQ/Layerscape SoCs (LX2160A, LS1028A, LS1088A, ...). @@ -45,16 +45,16 @@ config RCAR_GEN3_THERMAL driver into the U-Boot thermal framework. config TI_DRA7_THERMAL - bool "Temperature sensor driver for TI dra7xx SOCs" - help - Enable thermal support for for the Texas Instruments DRA752 SoC family. - The driver supports reading CPU temperature. + bool "Temperature sensor driver for TI dra7xx SOCs" + help + Enable thermal support for the Texas Instruments DRA752 SoC family. + The driver supports reading CPU temperature. config TI_LM74_THERMAL - bool "Temperature sensor driver for TI LM74 chip" - help - Enable thermal support for the Texas Instruments LM74 chip. - The driver supports reading CPU temperature. + bool "Temperature sensor driver for TI LM74 chip" + help + Enable thermal support for the Texas Instruments LM74 chip. + The driver supports reading CPU temperature. config DM_THERMAL_JC42 bool "JEDEC JC-42.4/TSE2004av SPD temperature sensor" diff --git a/drivers/tpm/cr50_i2c.c b/drivers/tpm/cr50_i2c.c index 14a94f8d4a8..46805eaa013 100644 --- a/drivers/tpm/cr50_i2c.c +++ b/drivers/tpm/cr50_i2c.c @@ -889,7 +889,7 @@ static int cr50_i2c_probe(struct udevice *dev) return 0; } -struct acpi_ops cr50_acpi_ops = { +static const struct acpi_ops cr50_acpi_ops = { .fill_ssdt = cr50_acpi_fill_ssdt, }; diff --git a/drivers/ufs/Kconfig b/drivers/ufs/Kconfig index 49472933de3..c1b84bd7559 100644 --- a/drivers/ufs/Kconfig +++ b/drivers/ufs/Kconfig @@ -19,12 +19,12 @@ config UFS_AMD_VERSAL2 config UFS_CADENCE bool "Cadence platform driver for UFS" depends on UFS - help + help This selects the platform driver for the Cadence UFS host controller present on present TI's J721e devices. config UFS_MEDIATEK - tristate "MediaTek UFS Host Controller Driver" + bool "MediaTek UFS Host Controller Driver" depends on UFS && ARCH_MEDIATEK select PHY_MTK_UFS help @@ -51,7 +51,7 @@ config UFS_PCI config UFS_QCOM bool "Qualcomm Host Controller driver for UFS" depends on UFS && ARCH_SNAPDRAGON - help + help This selects the platform driver for the UFS host controller present on Qualcomm Snapdragon SoCs. diff --git a/drivers/ufs/ufs-amd-versal2.c b/drivers/ufs/ufs-amd-versal2.c index 6c949b2ca76..3369d32d924 100644 --- a/drivers/ufs/ufs-amd-versal2.c +++ b/drivers/ufs/ufs-amd-versal2.c @@ -563,4 +563,5 @@ U_BOOT_DRIVER(ufs_versal2_pltfm) = { .id = UCLASS_UFS, .of_match = ufs_versal2_ids, .probe = ufs_versal2_probe, + .priv_auto = sizeof(struct ufs_versal2_priv), }; diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 93c5ee69b25..05ac388ecf2 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -1,7 +1,7 @@ menuconfig USB bool "USB support" select BLK - ---help--- + help Universal Serial Bus (USB) is a specification for a serial bus subsystem which offers higher speeds and more features than the traditional PC serial port. The bus supplies power to peripherals @@ -94,7 +94,7 @@ comment "USB peripherals" config USB_STORAGE bool "USB Mass Storage support" - ---help--- + help Say Y here if you want to connect USB mass storage devices to your board's USB port. @@ -103,7 +103,7 @@ config USB_KEYBOARD depends on DM_USB select DM_KEYBOARD select SYS_STDIO_DEREGISTER - ---help--- + help Say Y here if you want to use a USB keyboard for U-Boot command line input. @@ -111,7 +111,7 @@ config USB_ONBOARD_HUB bool "Onboard USB hub support" depends on DM_USB select DEVRES - ---help--- + help Say Y here if you want to support discrete onboard USB hubs that don't require an additional control bus for initialization, but need some non-trivial form of initialization, such as enabling a @@ -163,17 +163,17 @@ choice prompt "USB keyboard polling" default SYS_USB_EVENT_POLL_VIA_INT_QUEUE if ARCH_SUNXI default SYS_USB_EVENT_POLL - ---help--- + help Enable a polling mechanism for USB keyboard. config SYS_USB_EVENT_POLL - bool "Interrupt polling" + bool "Interrupt polling" config SYS_USB_EVENT_POLL_VIA_INT_QUEUE - bool "Poll via interrupt queue" + bool "Poll via interrupt queue" config SYS_USB_EVENT_POLL_VIA_CONTROL_EP - bool "Poll via control EP" + bool "Poll via control EP" endchoice diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig index 7964f3f41d5..ad0ef8ac2ba 100644 --- a/drivers/usb/cdns3/Kconfig +++ b/drivers/usb/cdns3/Kconfig @@ -1,5 +1,5 @@ config USB_CDNS3 - tristate "Cadence USB3 Dual-Role Controller" + bool "Cadence USB3 Dual-Role Controller" depends on USB_XHCI_HCD || USB_GADGET select DEVRES help @@ -51,14 +51,14 @@ config SPL_USB_CDNS3_HOST standard XHCI driver. config USB_CDNS3_STARFIVE - tristate "Cadence USB3 support on Starfive platforms" + bool "Cadence USB3 support on Starfive platforms" default y if STARFIVE_JH7110 help Say 'Y' here if you are building for Starfive platforms that contain Cadence USB3 controller core. E.g.: JH7110. config USB_CDNS3_TI - tristate "Cadence USB3 support on TI platforms" + bool "Cadence USB3 support on TI platforms" default USB_CDNS3 help Say 'Y' here if you are building for Texas Instruments diff --git a/drivers/usb/eth/Kconfig b/drivers/usb/eth/Kconfig index 2f6bfa8e71b..b9b77f46743 100644 --- a/drivers/usb/eth/Kconfig +++ b/drivers/usb/eth/Kconfig @@ -1,6 +1,6 @@ menuconfig USB_HOST_ETHER bool "USB to Ethernet Controller Drivers" - ---help--- + help Say Y here if you would like to enable support for USB Ethernet adapters. @@ -9,14 +9,14 @@ if USB_HOST_ETHER config USB_ETHER_ASIX bool "ASIX AX8817X (USB 2.0) support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support ASIX AX8817X based USB 2.0 Ethernet Devices. config USB_ETHER_ASIX88179 bool "ASIX AX88179 (USB 3.0) support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support ASIX AX88179 based USB 3.0 Ethernet Devices. @@ -24,7 +24,7 @@ config USB_ETHER_LAN75XX bool "Microchip LAN75XX support" depends on USB_HOST_ETHER depends on PHYLIB - ---help--- + help Say Y here if you would like to support Microchip LAN75XX Hi-Speed USB 2.0 to 10/100/1000 Gigabit Ethernet controller. Supports 10Base-T/ 100Base-TX/1000Base-T. @@ -34,7 +34,7 @@ config USB_ETHER_LAN78XX bool "Microchip LAN78XX support" depends on USB_HOST_ETHER depends on PHYLIB - ---help--- + help Say Y here if you would like to support Microchip LAN78XX USB 3.1 Gen 1 to 10/100/1000 Gigabit Ethernet controller. Supports 10Base-T/ 100Base-TX/1000Base-T. @@ -43,14 +43,14 @@ config USB_ETHER_LAN78XX config USB_ETHER_MCS7830 bool "MOSCHIP MCS7830 (7730/7830/7832) suppport" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support MOSCHIP MCS7830 based (7730/7830/7832) USB 2.0 Ethernet Devices. config USB_ETHER_RTL8152 bool "Realtek RTL8152B/RTL8153 support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support Realtek RTL8152B/RTL8153 base USB Ethernet Devices. This driver also supports compatible devices from Samsung, Lenovo, TP-LINK and Nvidia. @@ -58,7 +58,7 @@ config USB_ETHER_RTL8152 config USB_ETHER_SMSC95XX bool "SMSC LAN95x support" depends on USB_HOST_ETHER - ---help--- + help Say Y here if you would like to support SMSC LAN95xx based USB 2.0 Ethernet Devices. diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 5390878254a..e42d5a43696 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -19,10 +19,10 @@ menuconfig USB_GADGET select DM_USB imply CMD_BIND help - USB is a master/slave protocol, organized with one master - host (such as a PC) controlling up to 127 peripheral devices. - The USB hardware is asymmetric, which makes it easier to set up: - you can't connect a "to-the-host" connector to a peripheral. + USB is a master/slave protocol, organized with one master + host (such as a PC) controlling up to 127 peripheral devices. + The USB hardware is asymmetric, which makes it easier to set up: + you can't connect a "to-the-host" connector to a peripheral. U-Boot can run in the host, or in the peripheral. In both cases you need a low level bus controller driver, and some software @@ -164,10 +164,10 @@ config USB_GADGET_VBUS_DRAW range 2 500 default 2 help - Some devices need to draw power from USB when they are - configured, perhaps to operate circuitry or to recharge - batteries. This is in addition to any local power supply, - such as an AC adapter or batteries. + Some devices need to draw power from USB when they are + configured, perhaps to operate circuitry or to recharge + batteries. This is in addition to any local power supply, + such as an AC adapter or batteries. Enter the maximum power your device draws through USB, in milliAmperes. The permitted range of values is 2 - 500 mA; @@ -350,9 +350,9 @@ config SPL_DFU_RAM bool "RAM device" depends on SPL_DFU && SPL_RAM_SUPPORT help - select RAM/DDR memory device for loading binary images - (u-boot/kernel) to the selected device partition using - DFU and execute the u-boot/kernel from RAM. + select RAM/DDR memory device for loading binary images + (u-boot/kernel) to the selected device partition using + DFU and execute the u-boot/kernel from RAM. endchoice diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c index 71dc58da3f0..87ed25e8bb3 100644 --- a/drivers/usb/gadget/f_mass_storage.c +++ b/drivers/usb/gadget/f_mass_storage.c @@ -2275,6 +2275,17 @@ static int fsg_set_alt(struct usb_function *f, unsigned intf, unsigned alt) static void fsg_disable(struct usb_function *f) { struct fsg_dev *fsg = fsg_from_func(f); + + /* Disable the endpoints */ + if (fsg->bulk_in_enabled) { + usb_ep_disable(fsg->bulk_in); + fsg->bulk_in_enabled = 0; + } + if (fsg->bulk_out_enabled) { + usb_ep_disable(fsg->bulk_out); + fsg->bulk_out_enabled = 0; + } + fsg->common->new_fsg = NULL; raise_exception(fsg->common, FSG_STATE_CONFIG_CHANGE); } diff --git a/drivers/usb/gadget/f_sdp.c b/drivers/usb/gadget/f_sdp.c index f72e27028b7..cd2c282247a 100644 --- a/drivers/usb/gadget/f_sdp.c +++ b/drivers/usb/gadget/f_sdp.c @@ -75,6 +75,7 @@ struct hid_report { #define SDP_HID_PACKET_SIZE_EP1 1024 #define SDP_EXIT 1 +#define SDP_FAIL 2 struct sdp_command { u16 cmd; @@ -840,11 +841,14 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, #ifdef CONFIG_SPL_LOAD_FIT if (image_get_magic(header) == FDT_MAGIC) { struct spl_load_info load; + int ret; debug("Found FIT\n"); spl_load_init(&load, sdp_load_read, header, 1); - spl_load_simple_fit(spl_image, &load, 0, - header); + ret = spl_load_simple_fit(spl_image, &load, 0, + header); + if (ret) + return SDP_FAIL; return SDP_EXIT; } @@ -852,9 +856,13 @@ static int sdp_handle_in_ep(struct spl_image_info *spl_image, if (IS_ENABLED(CONFIG_SPL_LOAD_IMX_CONTAINER) && valid_container_hdr((void *)header)) { struct spl_load_info load; + int ret; spl_load_init(&load, sdp_load_read, header, 1); - spl_load_imx_container(spl_image, &load, 0); + ret = spl_load_imx_container(spl_image, &load, 0); + if (ret) + return SDP_FAIL; + return SDP_EXIT; } @@ -924,6 +932,8 @@ int spl_sdp_handle(struct udevice *udc, struct spl_image_info *spl_image, if (flag == SDP_EXIT) return 0; + else if (flag == SDP_FAIL) + return -EIO; schedule(); dm_usb_gadget_handle_interrupts(udc); diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index d75883e2865..6bbed9cb513 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -24,7 +24,7 @@ config USB_XHCI_HCD bool "xHCI HCD (USB 3.0) support" depends on DM && OF_CONTROL select USB_HOST - ---help--- + help The eXtensible Host Controller Interface (xHCI) is standard for USB 3.0 "SuperSpeed" host controller hardware. @@ -149,7 +149,7 @@ config USB_EHCI_HCD select USB_HOST select EHCI_DESC_BIG_ENDIAN if SYS_BIG_ENDIAN select EHCI_MMIO_BIG_ENDIAN if SYS_BIG_ENDIAN - ---help--- + help The Enhanced Host Controller Interface (EHCI) is standard for USB 2.0 "high speed" (480 Mbit/sec, 60 Mbyte/sec) host controller hardware. If your USB host controller supports USB 2.0, you will likely want to @@ -174,14 +174,14 @@ config USB_EHCI_ATMEL bool "Support for Atmel on-chip EHCI USB controller" depends on ARCH_AT91 default y - ---help--- + help Enables support for the on-chip EHCI controller on Atmel chips. config USB_EHCI_EXYNOS bool "Support for Samsung Exynos EHCI USB controller" depends on ARCH_EXYNOS default y - ---help--- + help Enables support for the on-chip EHCI controller on Samsung Exynos SoCs. @@ -191,7 +191,7 @@ config USB_EHCI_MARVELL default y select USB_EHCI_IS_TDI if !ARM64 select USB_EHCI_IS_TDI if ALLEYCAT_5 - ---help--- + help Enables support for the on-chip EHCI controller on MVEBU SoCs. config USB_EHCI_MX5 @@ -205,7 +205,7 @@ config USB_EHCI_MX6 depends on ARCH_MX6 || ARCH_MX7ULP || ARCH_IMXRT select EHCI_HCD_INIT_AFTER_RESET default y - ---help--- + help Enables support for the on-chip EHCI controller on i.MX6 SoCs. config USB_EHCI_MX7 @@ -215,7 +215,7 @@ config USB_EHCI_MX7 select PHY if IMX8M || IMX9 select NOP_PHY if IMX8M || IMX9 default y - ---help--- + help Enables support for the on-chip EHCI controller on i.MX7/i.MX8M/i.MX9 SoCs. config USB_EHCI_MXS @@ -230,7 +230,7 @@ config USB_EHCI_MXS config USB_EHCI_NPCM bool "Support for Nuvoton NPCM on-chip EHCI USB controller" depends on ARCH_NPCM - ---help--- + help Enables support for the on-chip EHCI controller on Nuvoton NPCM chips. @@ -240,7 +240,7 @@ config USB_EHCI_OMAP select PHY imply NOP_PHY default y - ---help--- + help Enables support for the on-chip EHCI controller on OMAP3 and later SoCs. @@ -255,7 +255,7 @@ if USB_EHCI_MX6 || USB_EHCI_MX7 config MXC_USB_OTG_HACTIVE bool "USB Power pin high active" - ---help--- + help Set the USB Power pin polarity to be high active (PWR_POL) endif @@ -265,7 +265,7 @@ config USB_EHCI_MSM depends on DM_USB select USB_ULPI select MSM8916_USB_PHY - ---help--- + help Enables support for the on-chip EHCI controller on Qualcomm Snapdragon SoCs. @@ -280,7 +280,7 @@ config USB_EHCI_TEGRA bool "Support for NVIDIA Tegra on-chip EHCI USB controller" depends on ARCH_TEGRA select USB_EHCI_IS_TDI - ---help--- + help Enable support for Tegra on-chip EHCI USB controller. If you enable ULPI and your PHY needs a different reference clock than the standard 24 MHz then you have to define CFG_ULPI_REF_CLK to the appropriate @@ -291,14 +291,14 @@ config USB_EHCI_ZYNQ depends on ARCH_ZYNQ default y select USB_EHCI_IS_TDI - ---help--- + help Enable support for Zynq on-chip EHCI USB controller config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on DM_USB default ARCH_SUNXI - ---help--- + help Enables support for generic EHCI controller. config EHCI_HCD_INIT_AFTER_RESET @@ -310,7 +310,7 @@ config USB_EHCI_FSL select EHCI_HCD_INIT_AFTER_RESET select SYS_FSL_USB_INTERNAL_UTMI_PHY if MPC85xx && \ !(ARCH_B4860 || ARCH_B4420 || ARCH_P4080 || ARCH_P1020 || ARCH_P2020) - ---help--- + help Enables support for the on-chip EHCI controller on FSL chips. config SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -340,7 +340,7 @@ config USB_OHCI_HCD depends on DM && OF_CONTROL select USB_HOST select USB_OHCI_NEW - ---help--- + help The Open Host Controller Interface (OHCI) is a standard for accessing USB 1.1 host controller hardware. It does more in hardware than Intel's UHCI specification. If your USB host controller follows the OHCI spec, @@ -361,7 +361,7 @@ config USB_OHCI_PCI config USB_OHCI_GENERIC bool "Support for generic OHCI USB controller" default ARCH_SUNXI - ---help--- + help Enables support for generic OHCI controller. config USB_OHCI_DA8XX @@ -374,7 +374,7 @@ config USB_OHCI_DA8XX config USB_OHCI_NPCM bool "Support for Nuvoton NPCM on-chip OHCI USB controller" depends on ARCH_NPCM - ---help--- + help Enables support for the on-chip OHCI controller on Nuvoton NPCM chips. @@ -391,7 +391,7 @@ config SYS_OHCI_SWAP_REG_ACCESS config USB_UHCI_HCD bool "UHCI HCD (most Intel and VIA) support" select USB_HOST - ---help--- + help The Universal Host Controller Interface is a standard by Intel for accessing the USB hardware in the PC (which is also called the USB host controller). If your USB host controller conforms to this @@ -410,7 +410,7 @@ config USB_DWC2 bool "DesignWare USB2 Core support" depends on DM && OF_CONTROL select USB_HOST - ---help--- + help The DesignWare USB 2.0 controller is compliant with the USB-Implementers Forum (USB-IF) USB 2.0 specifications. Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and Low-Speed (1.5 Mbps) @@ -421,7 +421,7 @@ if USB_DWC2 config USB_DWC2_BUFFER_SIZE int "Data buffer size in kB" default 64 - ---help--- + help By default 64 kB buffer is used but if amount of RAM avaialble on the target is not enough to accommodate allocation of buffer of that size it is possible to shrink it. Smaller sizes should be fine @@ -433,7 +433,7 @@ config USB_R8A66597_HCD bool "Renesas R8A66597 USB Core support" depends on DM && OF_CONTROL select USB_HOST - ---help--- + help This enables support for the on-chip Renesas R8A66597 USB 2.0 controller, present in various RZ and SH SoCs. diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig index f8daaddc657..208e47d8ff5 100644 --- a/drivers/usb/musb-new/Kconfig +++ b/drivers/usb/musb-new/Kconfig @@ -23,11 +23,11 @@ config USB_MUSB_GADGET if USB_MUSB_HOST || USB_MUSB_GADGET config USB_MUSB_SC5XX - bool "Analog Devices MUSB support" - depends on (SC57X || SC58X) + bool "Analog Devices MUSB support" + depends on (SC57X || SC58X) help - Say y here to enable support for the USB controller on - ADI SC57X/SC58X processors. + Say y here to enable support for the USB controller on + ADI SC57X/SC58X processors. config USB_MUSB_DA8XX bool "Enable DA8xx MUSB Controller" @@ -48,7 +48,7 @@ config USB_MUSB_TI silicon IP. config USB_MUSB_OMAP2PLUS - tristate "OMAP2430 and onwards" + bool "OMAP2430 and onwards" depends on ARCH_OMAP2PLUS config USB_MUSB_AM35X @@ -81,9 +81,9 @@ config USB_MUSB_SUNXI depends on PHY_SUN4I_USB select USB_MUSB_PIO_ONLY default y - ---help--- - Say y here to enable support for the sunxi OTG / DRC USB controller - used on almost all sunxi boards. + help + Say y here to enable support for the sunxi OTG / DRC USB controller + used on almost all sunxi boards. config USB_MUSB_UX500 bool "Enable ST-Ericsson Ux500 USB controller" diff --git a/drivers/usb/tcpm/Kconfig b/drivers/usb/tcpm/Kconfig index 9be4b496e82..b1ea7253720 100644 --- a/drivers/usb/tcpm/Kconfig +++ b/drivers/usb/tcpm/Kconfig @@ -1,14 +1,14 @@ # SPDX-License-Identifier: GPL-2.0 config TYPEC_TCPM - tristate "USB Type-C Port Controller Manager" + bool "USB Type-C Port Controller Manager" depends on DM help The Type-C Port Controller Manager provides a USB PD and USB Type-C state machine for use with Type-C Port Controllers. config TYPEC_FUSB302 - tristate "Fairchild FUSB302 Type-C chip driver" + bool "Fairchild FUSB302 Type-C chip driver" depends on DM && DM_I2C && TYPEC_TCPM help The Fairchild FUSB302 Type-C chip driver that works with diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 5a0dfb159c4..15000e21840 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -254,10 +254,10 @@ config SYS_WHITE_ON_BLACK bool "Display console as white on a black background" default y if ARCH_AT91 || ARCH_EXYNOS || ARCH_ROCKCHIP || ARCH_TEGRA || X86 || ARCH_SUNXI help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background. This can be - better in low-light situations or to reduce eye strain in some - cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background. This can be + better in low-light situations or to reduce eye strain in some + cases. config NO_FB_CLEAR bool "Skip framebuffer clear" @@ -515,10 +515,10 @@ config FRAMEBUFFER_VESA_MODE config VIDEO_LCD_ANX9804 bool "ANX9804 bridge chip" - ---help--- - Support for the ANX9804 bridge chip, which can take pixel data coming - from a parallel LCD interface and translate it on the fy into a DP - interface for driving eDP TFT displays. It uses I2C for configuration. + help + Support for the ANX9804 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fy into a DP + interface for driving eDP TFT displays. It uses I2C for configuration. config ATMEL_LCD bool "Atmel LCD panel support" @@ -556,8 +556,8 @@ config VIDEO_LCD_HIMAX_HX8394 depends on PANEL && BACKLIGHT select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Himax HX8394 - dsi 4dl panel. + Say Y here if you want to enable support for Himax HX8394 + dsi 4dl panel. config VIDEO_LCD_ILITEK_ILI9806E bool "Ilitek ILI9806E-based panels" @@ -612,8 +612,8 @@ config VIDEO_LCD_RAYDIUM_RM68200 depends on BACKLIGHT select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for Raydium RM68200 - 720x1280 DSI video mode panel. + Say Y here if you want to enable support for Raydium RM68200 + 720x1280 DSI video mode panel. config VIDEO_LCD_RENESAS_R61307 bool "Renesas R61307 DSI video mode panel" @@ -662,38 +662,38 @@ config VIDEO_LCD_SHARP_LQ101R1SX01 config VIDEO_LCD_SSD2828 bool "SSD2828 bridge chip" - ---help--- - Support for the SSD2828 bridge chip, which can take pixel data coming - from a parallel LCD interface and translate it on the fly into MIPI DSI - interface for driving a MIPI compatible LCD panel. It uses SPI for - configuration. + help + Support for the SSD2828 bridge chip, which can take pixel data coming + from a parallel LCD interface and translate it on the fly into MIPI DSI + interface for driving a MIPI compatible LCD panel. It uses SPI for + configuration. config VIDEO_LCD_SSD2828_TX_CLK int "SSD2828 TX_CLK frequency (in MHz)" depends on VIDEO_LCD_SSD2828 default 0 - ---help--- - The frequency of the crystal, which is clocking SSD2828. It may be - anything in the 8MHz-30MHz range and the exact value should be - retrieved from the board schematics. Or in the case of Allwinner - hardware, it can be usually found as 'lcd_xtal_freq' variable in - FEX files. It can be also set to 0 for selecting PCLK from the - parallel LCD interface instead of TX_CLK as the PLL clock source. + help + The frequency of the crystal, which is clocking SSD2828. It may be + anything in the 8MHz-30MHz range and the exact value should be + retrieved from the board schematics. Or in the case of Allwinner + hardware, it can be usually found as 'lcd_xtal_freq' variable in + FEX files. It can be also set to 0 for selecting PCLK from the + parallel LCD interface instead of TX_CLK as the PLL clock source. config VIDEO_LCD_SSD2828_RESET string "RESET pin of SSD2828" depends on VIDEO_LCD_SSD2828 default "" - ---help--- - The reset pin of SSD2828 chip. This takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + The reset pin of SSD2828 chip. This takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_TDO_TL070WSH30 bool "TDO TL070WSH30 DSI LCD panel support" select VIDEO_MIPI_DSI help - Say Y here if you want to enable support for TDO TL070WSH30 - 1024x600 DSI video mode panel. + Say Y here if you want to enable support for TDO TL070WSH30 + 1024x600 DSI video mode panel. config VIDEO_LCD_HITACHI_TX10D07VM0BAA bool "Hitachi TX10D07VM0BAA 480x800 MIPI DSI video mode panel" @@ -705,10 +705,10 @@ config VIDEO_LCD_HITACHI_TX10D07VM0BAA config VIDEO_LCD_HITACHI_TX18D42VM bool "Hitachi tx18d42vm LVDS LCD panel support" - ---help--- - Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a - lcd controller which needs to be initialized over SPI, once that is - done they work like a regular LVDS panel. + help + Support for Hitachi tx18d42vm LVDS LCD panels, these panels have a + lcd controller which needs to be initialized over SPI, once that is + done they work like a regular LVDS panel. config VIDEO_LCD_SONY_L4F00430T01 bool "Sony L4F00430T01 480x800 LCD panel support" @@ -731,44 +731,44 @@ config VIDEO_LCD_SPI_CS string "SPI CS pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_SCLK string "SPI SCLK pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_MOSI string "SPI MOSI pin for LCD related config job" depends on VIDEO_LCD_SSD2828 || VIDEO_LCD_HITACHI_TX18D42VM default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. The option takes a string in the format - understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. The option takes a string in the format + understood by 'sunxi_name_to_gpio' function, e.g. PH1 for pin 1 of port H. config VIDEO_LCD_SPI_MISO string "SPI MISO pin for LCD related config job (optional)" depends on VIDEO_LCD_SSD2828 default "" - ---help--- - This is one of the SPI communication pins, involved in setting up a - working LCD configuration. The exact role of SPI may differ for - different hardware setups. If wired up, this pin may provide additional - useful functionality. Such as bi-directional communication with the - hardware and LCD panel id retrieval (if the panel can report it). The - option takes a string in the format understood by 'sunxi_name_to_gpio' - function, e.g. PH1 for pin 1 of port H. + help + This is one of the SPI communication pins, involved in setting up a + working LCD configuration. The exact role of SPI may differ for + different hardware setups. If wired up, this pin may provide additional + useful functionality. Such as bi-directional communication with the + hardware and LCD panel id retrieval (if the panel can report it). The + option takes a string in the format understood by 'sunxi_name_to_gpio' + function, e.g. PH1 for pin 1 of port H. source "drivers/video/meson/Kconfig" @@ -776,9 +776,9 @@ config VIDEO_MVEBU bool "Armada XP LCD controller" depends on ARCH_MVEBU imply VIDEO_DAMAGE - ---help--- - Support for the LCD controller integrated in the Marvell - Armada XP SoC. + help + Support for the LCD controller integrated in the Marvell + Armada XP SoC. config VIDEO_OMAP3 bool "Enable OMAP3+ DSS Support" @@ -789,23 +789,23 @@ config VIDEO_OMAP3 config I2C_EDID bool "Enable EDID library" help - This enables library for accessing EDID data from an LCD panel. + This enables library for accessing EDID data from an LCD panel. config I2C_EDID_STANDARD bool "Enable standard timings EDID library expansion" depends on I2C_EDID help - This enables standard timings expansion for EDID data from an LCD panel. + This enables standard timings expansion for EDID data from an LCD panel. config DISPLAY bool "Enable Display support" depends on DM select I2C_EDID help - This supports drivers that provide a display, such as eDP (Embedded - DisplayPort) and HDMI (High Definition Multimedia Interface). - The devices provide a simple interface to start up the display, - read display information and enable it. + This supports drivers that provide a display, such as eDP (Embedded + DisplayPort) and HDMI (High Definition Multimedia Interface). + The devices provide a simple interface to start up the display, + read display information and enable it. config NXP_TDA19988 bool "Enable NXP TDA19988 support" @@ -819,7 +819,7 @@ config ATMEL_HLCD depends on ARCH_AT91 imply VIDEO_DAMAGE help - HLCDC supports video output to an attached LCD panel. + HLCDC supports video output to an attached LCD panel. config BACKLIGHT_AAT2870 bool "Backlight Driver for AAT2870" @@ -938,9 +938,9 @@ config VIDEO_NX bool "Enable video support on Nexell SoC" depends on ARCH_S5P6818 || ARCH_S5P4418 help - Nexell SoC supports many video output options including eDP and - HDMI. This option enables this support which can be used on devices - which have an eDP display connected. + Nexell SoC supports many video output options including eDP and + HDMI. This option enables this support which can be used on devices + which have an eDP display connected. config VIDEO_SEPS525 bool "Enable video support for Seps525" @@ -1026,9 +1026,9 @@ config OSD bool "Enable OSD support" depends on DM help - This supports drivers that provide a OSD (on-screen display), which - is a (usually text-oriented) graphics buffer to show information on - a display. + This supports drivers that provide a OSD (on-screen display), which + is a (usually text-oriented) graphics buffer to show information on + a display. config SANDBOX_OSD bool "Enable sandbox OSD" @@ -1221,10 +1221,10 @@ config SPL_SPLASH_SCREEN config SPL_SYS_WHITE_ON_BLACK bool "Display console as white on a black background at SPL" help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background at spl stage. - This can be better in low-light situations or to reduce eye strain in - some cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background at spl stage. + This can be better in low-light situations or to reduce eye strain in + some cases. config SPL_VIDEO_PCI_DEFAULT_FB_SIZE hex "Default framebuffer size to use if no drivers request it at SPL" @@ -1287,10 +1287,10 @@ config SPL_SIMPLE_PANEL config SPL_SYS_WHITE_ON_BLACK bool "Display console as white on a black background at SPL" help - Normally the display is black on a white background, Enable this - option to invert this, i.e. white on a black background at spl stage. - This can be better in low-light situations or to reduce eye strain in - some cases. + Normally the display is black on a white background, Enable this + option to invert this, i.e. white on a black background at spl stage. + This can be better in low-light situations or to reduce eye strain in + some cases. config SPL_VIDEO_REMOVE bool "Remove video driver after SPL stage" @@ -1416,13 +1416,13 @@ config SPL_VIDEO_BPP32 will be empty. config SPL_HIDE_LOGO_VERSION - bool "Hide the version information on the splash screen at SPL" - help - Normally the U-Boot version string is shown on the display when the - splash screen is enabled. This information is not otherwise visible - since video starts up after U-Boot has displayed the initial banner. + bool "Hide the version information on the splash screen at SPL" + help + Normally the U-Boot version string is shown on the display when the + splash screen is enabled. This information is not otherwise visible + since video starts up after U-Boot has displayed the initial banner. - Enable this option to hide this information. + Enable this option to hide this information. endif endmenu diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig index 5322a002928..81261c61005 100644 --- a/drivers/video/bridge/Kconfig +++ b/drivers/video/bridge/Kconfig @@ -41,8 +41,8 @@ config VIDEO_BRIDGE_ANALOGIX_ANX6345 depends on VIDEO_BRIDGE select DM_I2C help - The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD - panel to be connected to an parallel LCD interface. + The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD + panel to be connected to an parallel LCD interface. config VIDEO_BRIDGE_SOLOMON_SSD2825 bool "Solomon SSD2825 bridge driver" diff --git a/drivers/video/imx/Kconfig b/drivers/video/imx/Kconfig index c25f209629e..0c386595559 100644 --- a/drivers/video/imx/Kconfig +++ b/drivers/video/imx/Kconfig @@ -20,7 +20,7 @@ config IPU_CLK_LEGACY depends on VIDEO_IPUV3 && !CLK default y help - Use legacy clock management instead of Common Clock Framework. + Use legacy clock management instead of Common Clock Framework. config IMX_LDB bool "Freescale i.MX8MP LDB bridge" diff --git a/drivers/video/imx/ipu.h b/drivers/video/imx/ipu.h index ae40e20bc28..aecb6adffce 100644 --- a/drivers/video/imx/ipu.h +++ b/drivers/video/imx/ipu.h @@ -136,7 +136,6 @@ struct ipu_ctx { struct clk *ipu_clk; struct clk *ldb_clk; - unsigned char ipu_clk_enabled; struct clk *di_clk[2]; struct clk *pixel_clk[2]; diff --git a/drivers/video/imx/ipu_common.c b/drivers/video/imx/ipu_common.c index 8630374a055..d3b52605731 100644 --- a/drivers/video/imx/ipu_common.c +++ b/drivers/video/imx/ipu_common.c @@ -299,9 +299,9 @@ struct ipu_ctx *ipu_probe(struct udevice *dev) #if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) clk_set_parent(ctx->pixel_clk[0], ctx->ipu_clk); clk_set_parent(ctx->pixel_clk[1], ctx->ipu_clk); +#endif clk_enable(ctx->ipu_clk); -#endif for (int i = 0; i <= 1; i++) { ret = ipu_di_clk_init(ctx, i); @@ -384,10 +384,8 @@ int32_t ipu_init_channel(struct ipu_ctx *ctx, ipu_channel_t channel, debug("init channel = %d\n", IPU_CHAN_ID(channel)); - if (ctx->ipu_clk_enabled == 0) { - ctx->ipu_clk_enabled = 1; + if (!ipu_clk_enabled(ctx)) clk_enable(ipu_clk); - } if (*channel_init_mask & (1L << IPU_CHAN_ID(channel))) { printf("Warning: channel already initialized %d\n", @@ -543,7 +541,6 @@ void ipu_uninit_channel(struct ipu_ctx *ctx, ipu_channel_t channel) if (ipu_conf == 0) { clk_disable(ctx->ipu_clk); - ctx->ipu_clk_enabled = 0; } } @@ -1045,5 +1042,9 @@ ipu_color_space_t format_to_colorspace(u32 fmt) bool ipu_clk_enabled(struct ipu_ctx *ctx) { - return ctx->ipu_clk_enabled; +#if CONFIG_IS_ENABLED(IPU_CLK_LEGACY) + return clk_get_usecount(ctx->ipu_clk); +#else + return ctx->ipu_clk->enable_count; +#endif } diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig index 96af6d28ef0..41d249cb90c 100644 --- a/drivers/video/rockchip/Kconfig +++ b/drivers/video/rockchip/Kconfig @@ -21,7 +21,7 @@ menuconfig VIDEO_ROCKCHIP Rockchip RK3288 and RK3399. config VIDEO_ROCKCHIP_MAX_XRES - int "Maximum horizontal resolution (for memory allocation purposes)" + int "Maximum horizontal resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP default 3840 if DISPLAY_ROCKCHIP_HDMI default 1920 @@ -31,7 +31,7 @@ config VIDEO_ROCKCHIP_MAX_XRES framebuffer during device-model binding/probing. config VIDEO_ROCKCHIP_MAX_YRES - int "Maximum vertical resolution (for memory allocation purposes)" + int "Maximum vertical resolution (for memory allocation purposes)" depends on VIDEO_ROCKCHIP default 2160 if DISPLAY_ROCKCHIP_HDMI default 1080 diff --git a/drivers/video/tegra/Kconfig b/drivers/video/tegra/Kconfig index 8bc29f2838b..125504024fc 100644 --- a/drivers/video/tegra/Kconfig +++ b/drivers/video/tegra/Kconfig @@ -9,13 +9,13 @@ config VIDEO_TEGRA depends on OF_CONTROL && ARCH_TEGRA select HOST1X_TEGRA help - Enable support for Display Controller found in Tegra SoC. The - Display Controller Complex integrates two independent display - controllers. Each display controller is capable of interfacing - to an external display device, which can be a parallel interface - or SPI LCD, DVI, an HDMI HDTV, RGB monitor or a MIPI DSI LCD. - Direct interface is supported directly to most LCD displays with - TFT or TFT-like interface. + Enable support for Display Controller found in Tegra SoC. The + Display Controller Complex integrates two independent display + controllers. Each display controller is capable of interfacing + to an external display device, which can be a parallel interface + or SPI LCD, DVI, an HDMI HDTV, RGB monitor or a MIPI DSI LCD. + Direct interface is supported directly to most LCD displays with + TFT or TFT-like interface. config VIDEO_DSI_TEGRA bool "Enable DSI controller support on Tegra devices" @@ -23,9 +23,9 @@ config VIDEO_DSI_TEGRA select VIDEO_TEGRA select VIDEO_MIPI_DSI help - Enable support for the Display Serial Interface (DSI) found in - Tegra SoC. It is a MIPI standard serial bitstream, intended to - provide a low pin count interface to a display panel. + Enable support for the Display Serial Interface (DSI) found in + Tegra SoC. It is a MIPI standard serial bitstream, intended to + provide a low pin count interface to a display panel. config VIDEO_HDMI_TEGRA bool "Enable HDMI support on Tegra devices" @@ -33,31 +33,31 @@ config VIDEO_HDMI_TEGRA select I2C_EDID select VIDEO_TEGRA help - Enable support for the High-Definition Multimedia Interface (HDMI) - found in Tegra SoC. + Enable support for the High-Definition Multimedia Interface (HDMI) + found in Tegra SoC. config TEGRA_BACKLIGHT_PWM bool "Enable Tegra DC PWM backlight support" depends on BACKLIGHT && VIDEO_TEGRA help - Enable support for the Display Controller dependent PWM backlight - found in the Tegra SoC and usually used with DSI panels. + Enable support for the Display Controller dependent PWM backlight + found in the Tegra SoC and usually used with DSI panels. config TEGRA_8BIT_CPU_BRIDGE bool "Enable 8 bit panel communication protocol for Tegra 20/30" depends on VIDEO_BRIDGE && DM_GPIO && VIDEO_TEGRA select VIDEO_MIPI_DSI help - Tegra 20 and Tegra 30 feature 8 bit CPU driver panel control - protocol. This option allows use it as a MIPI DSI bridge to - set up and control compatible panel. + Tegra 20 and Tegra 30 feature 8 bit CPU driver panel control + protocol. This option allows use it as a MIPI DSI bridge to + set up and control compatible panel. config VIDEO_TEGRA124 bool "Enable video support on Tegra124" depends on ARCH_TEGRA imply VIDEO_DAMAGE help - Tegra124 supports many video output options including eDP and - HDMI. At present only eDP is supported by U-Boot. This option - enables this support which can be used on devices which - have an eDP display connected. + Tegra124 supports many video output options including eDP and + HDMI. At present only eDP is supported by U-Boot. This option + enables this support which can be used on devices which + have an eDP display connected. diff --git a/drivers/video/ti/Kconfig b/drivers/video/ti/Kconfig index 0483f760ea1..a3cbefef0de 100644 --- a/drivers/video/ti/Kconfig +++ b/drivers/video/ti/Kconfig @@ -6,4 +6,4 @@ config AM335X_LCD bool "Enable AM335x video support" depends on ARCH_OMAP2PLUS help - Supports video output to an attached LCD panel. + Supports video output to an attached LCD panel. diff --git a/drivers/video/zynqmp/Kconfig b/drivers/video/zynqmp/Kconfig index b35cd1fb342..2c737710639 100644 --- a/drivers/video/zynqmp/Kconfig +++ b/drivers/video/zynqmp/Kconfig @@ -3,6 +3,6 @@ config VIDEO_ZYNQMP_DPSUB bool "Enable video support for ZynqMP Display Port" depends on ZYNQMP_POWER_DOMAIN help - Enable support for Xilinx ZynqMP Display Port. Currently this file - is used as placeholder for driver. The main reason is to record - compatible string and calling power domain driver. + Enable support for Xilinx ZynqMP Display Port. Currently this file + is used as placeholder for driver. The main reason is to record + compatible string and calling power domain driver. diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig index 0e6e6830fc8..b91727e1265 100644 --- a/drivers/watchdog/Kconfig +++ b/drivers/watchdog/Kconfig @@ -384,10 +384,10 @@ config WDT_SBSA bool "SBSA watchdog timer support" depends on WDT help - Select this to enable SBSA watchdog timer. - This driver can operate ARM SBSA Generic Watchdog as a single stage. - In the single stage mode, when the timeout is reached, your system - will be reset by WS1. The first signal (WS0) is ignored. + Select this to enable SBSA watchdog timer. + This driver can operate ARM SBSA Generic Watchdog as a single stage. + In the single stage mode, when the timeout is reached, your system + will be reset by WS1. The first signal (WS0) is ignored. config WDT_SIEMENS_PMIC bool "Enable PMIC Watchdog Timer support for Siemens platforms" diff --git a/drivers/watchdog/renesas_wwdt.c b/drivers/watchdog/renesas_wwdt.c index f6f508c95c2..60f2ac466bf 100644 --- a/drivers/watchdog/renesas_wwdt.c +++ b/drivers/watchdog/renesas_wwdt.c @@ -13,8 +13,6 @@ #include <syscon.h> #include <wdt.h> -#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask)) - #define RSIP_CTL_CFG4 0xc0 #define RSIP_CTL_CFG4_OPWDEN BIT(3) #define RSIP_CTL_CFG4_OPWDVAC BIT(5) diff --git a/dts/Kconfig b/dts/Kconfig index 6b501c2239e..dcabe33c1c1 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -224,7 +224,7 @@ config DEFAULT_DEVICE_TREE $ make DEVICE_TREE=<device-tree-name> config DEVICE_TREE_INCLUDES - string "Extra .dtsi files to include when building DT control" + string "Extra .dtsi files to include when building DT control" depends on OF_CONTROL help U-Boot's control .dtb is usually built from an in-tree .dts @@ -297,27 +297,27 @@ config MULTI_DTB_FIT_UNCOMPRESS_SZ hex "Size of memory reserved to uncompress the DTBs" default 0x8000 help - This is the size of this area where the DTBs are uncompressed. - If this area is dynamically allocated, make sure that - SYS_MALLOC_F_LEN is big enough to contain it. + This is the size of this area where the DTBs are uncompressed. + If this area is dynamically allocated, make sure that + SYS_MALLOC_F_LEN is big enough to contain it. config MULTI_DTB_FIT_USER_DEF_ADDR hex "Address of memory where dtbs are uncompressed" depends on MULTI_DTB_FIT_USER_DEFINED_AREA help - the FIT image containing the DTBs is uncompressed in an area defined - at compilation time. This is the address of this area. It must be - aligned on 2-byte boundary. + the FIT image containing the DTBs is uncompressed in an area defined + at compilation time. This is the address of this area. It must be + aligned on 2-byte boundary. config DTB_RESELECT bool "Support swapping dtbs at a later point in boot" depends on !COMPILE_TEST depends on MULTI_DTB_FIT help - It is possible during initial boot you may need to use a generic - dtb until you can fully determine the board your running on. This - config allows boards to implement a function at a later point - during boot to switch to the "correct" dtb. + It is possible during initial boot you may need to use a generic dtb + until you can fully determine the board you are running on. This + config allows boards to implement a function at a later point during + boot to switch to the "correct" dtb. config MULTI_DTB_FIT bool "Support embedding several DTBs in a FIT image for u-boot" @@ -398,17 +398,17 @@ config SPL_MULTI_DTB_FIT_UNCOMPRESS_SZ depends on (SPL_MULTI_DTB_FIT_GZIP || SPL_MULTI_DTB_FIT_LZO) default 0x8000 help - This is the size of this area where the DTBs are uncompressed. - If this area is dynamically allocated, make sure that - SPL_SYS_MALLOC_F_LEN is big enough to contain it. + This is the size of this area where the DTBs are uncompressed. + If this area is dynamically allocated, make sure that + SPL_SYS_MALLOC_F_LEN is big enough to contain it. config SPL_MULTI_DTB_FIT_USER_DEF_ADDR hex "Address of memory where dtbs are uncompressed" depends on SPL_MULTI_DTB_FIT_USER_DEFINED_AREA help - the FIT image containing the DTBs is uncompressed in an area defined - at compilation time. This is the address of this area. It must be - aligned on 2-byte boundary. + the FIT image containing the DTBs is uncompressed in an area defined + at compilation time. This is the address of this area. It must be + aligned on 2-byte boundary. config OF_SPL_REMOVE_PROPS string "List of device tree properties to drop for SPL" diff --git a/dts/upstream/src/arm64/mediatek/mt6359.dtsi b/dts/upstream/src/arm64/mediatek/mt6359.dtsi index 467d8a4c2aa..45ad69ee49e 100644 --- a/dts/upstream/src/arm64/mediatek/mt6359.dtsi +++ b/dts/upstream/src/arm64/mediatek/mt6359.dtsi @@ -205,7 +205,7 @@ regulator-max-microvolt = <1700000>; }; mt6359_vrfck_1_ldo_reg: ldo_vrfck_1 { - regulator-name = "vrfck"; + regulator-name = "vrfck_1"; regulator-min-microvolt = <1240000>; regulator-max-microvolt = <1600000>; }; @@ -227,7 +227,7 @@ regulator-max-microvolt = <3300000>; }; mt6359_vemc_1_ldo_reg: ldo_vemc_1 { - regulator-name = "vemc"; + regulator-name = "vemc_1"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; }; diff --git a/env/Kconfig b/env/Kconfig index 3c9aaeb1f16..bbd657682d7 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -739,6 +739,26 @@ config ENV_UBI_VOLUME_REDUND help Name of the redundant volume that you want to store the environment in. +config ENV_UBI_VOLUME_CREATE + bool "Create UBI volume if it does not exist" + depends on ENV_IS_IN_UBI + help + This option is useful if U-Boot will be booted from a fresh device + where the environment volume has not been created. + This is a common case where factory UBI image contains only volumes + with valid data. + By enabling this option, any missing environment volumes will be + created before loading. + If ENV_UBI_VOLUME_REDUND is also enabled, both volumes will be + created. + +config ENV_UBI_VOLUME_STATIC + bool "Create static UBI volume" + depends on ENV_UBI_VOLUME_CREATE + help + By default environment volume will be dynamic. + Enable this option to create static volume. + config ENV_UBI_VID_OFFSET int "ubi environment VID offset" depends on ENV_IS_IN_UBI diff --git a/env/env.c b/env/env.c index 7a9c96b4078..404e8b7a26c 100644 --- a/env/env.c +++ b/env/env.c @@ -189,7 +189,7 @@ int env_load(void) if (!env_has_inited(drv->location)) continue; - printf("Loading Environment from %s... ", drv->name); + printf("Loading Environment from %s...\r", drv->name); /* * In error case, the error message must be printed during * drv->load() in some underlying API, and it must be exactly @@ -197,7 +197,7 @@ int env_load(void) */ ret = drv->load(); if (!ret) { - printf("OK\n"); + printf("Loading Environment from %s... OK\n", drv->name); gd->env_load_prio = prio; return 0; @@ -206,7 +206,7 @@ int env_load(void) if (best_prio == -1) best_prio = prio; } else { - debug("Failed (%d)\n", ret); + debug("Loading Environment from %s... Failed (%d)\n", drv->name, ret); } } diff --git a/env/ubi.c b/env/ubi.c index e9865b45ebc..810faaf7744 100644 --- a/env/ubi.c +++ b/env/ubi.c @@ -103,12 +103,30 @@ static int env_ubi_save(void) } #endif /* CONFIG_ENV_REDUNDANT */ +static int env_ubi_volume_create(const char *volume) +{ + bool dynamic = !IS_ENABLED(CONFIG_ENV_UBI_VOLUME_STATIC); + struct ubi_volume *vol; + int ret; + + vol = ubi_find_volume(volume); + if (vol) + return 0; + + ret = ubi_create_vol(volume, CONFIG_ENV_SIZE, dynamic, UBI_VOL_NUM_AUTO, + false); + if (ret) + printf("Failed to create environment volume '%s'\n", volume); + + return ret; +} + #ifdef CONFIG_ENV_REDUNDANT static int env_ubi_load(void) { ALLOC_CACHE_ALIGN_BUFFER(char, env1_buf, CONFIG_ENV_SIZE); ALLOC_CACHE_ALIGN_BUFFER(char, env2_buf, CONFIG_ENV_SIZE); - int read1_fail, read2_fail; + int read1_fail, read2_fail, create1_fail = 0, create2_fail = 0; env_t *tmp_env1, *tmp_env2; /* @@ -132,17 +150,35 @@ static int env_ubi_load(void) return -EIO; } - read1_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)tmp_env1, 0, - CONFIG_ENV_SIZE); - if (read1_fail) - printf("\n** Unable to read env from %s:%s **\n", - CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); + if (IS_ENABLED(CONFIG_ENV_UBI_VOLUME_CREATE)) { + create1_fail = env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME); + create2_fail = env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME_REDUND); + if (create1_fail && create2_fail) { + env_set_default(NULL, 0); + return -ENODEV; + } + } - read2_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME_REDUND, - (void *)tmp_env2, 0, CONFIG_ENV_SIZE); - if (read2_fail) - printf("\n** Unable to read redundant env from %s:%s **\n", - CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME_REDUND); + if (!create1_fail) { + read1_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME, tmp_env1, 0, + CONFIG_ENV_SIZE); + if (read1_fail) + printf("\n** Unable to read env from %s:%s **\n", + CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); + } else { + read1_fail = create1_fail; + } + + if (!create2_fail) { + read2_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME_REDUND, + tmp_env2, 0, CONFIG_ENV_SIZE); + if (read2_fail) + printf("\n** Unable to read redundant env from %s:%s **\n", + CONFIG_ENV_UBI_PART, + CONFIG_ENV_UBI_VOLUME_REDUND); + } else { + read2_fail = create2_fail; + } return env_import_redund((char *)tmp_env1, read1_fail, (char *)tmp_env2, read2_fail, H_EXTERNAL); @@ -169,6 +205,13 @@ static int env_ubi_load(void) return -EIO; } + if (IS_ENABLED(CONFIG_ENV_UBI_VOLUME_CREATE)) { + if (env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME)) { + env_set_default(NULL, 0); + return -ENODEV; + } + } + if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, buf, 0, CONFIG_ENV_SIZE)) { printf("\n** Unable to read env from %s:%s **\n", CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); diff --git a/fs/fat/Kconfig b/fs/fat/Kconfig index 9606fa48bbe..aa121844844 100644 --- a/fs/fat/Kconfig +++ b/fs/fat/Kconfig @@ -36,4 +36,4 @@ config FS_FAT_HANDLE_SECTOR_SIZE_MISMATCH depends on FS_FAT help Handle filesystems on media where the hardware block size and - the sector size in the FAT metadata do not match. + the sector size in the FAT metadata do not match. diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c index b6004b88f4e..9c8974a97a5 100644 --- a/fs/ubifs/super.c +++ b/fs/ubifs/super.c @@ -2694,7 +2694,7 @@ MODULE_VERSION(__stringify(UBIFS_VERSION)); MODULE_AUTHOR("Artem Bityutskiy, Adrian Hunter"); MODULE_DESCRIPTION("UBIFS - UBI File System"); #else -int uboot_ubifs_mount(char *vol_name) +int uboot_ubifs_mount(const char *vol_name) { struct dentry *ret; int flags; diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 3f2e2037745..6121fb0b135 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -544,7 +544,7 @@ static unsigned long ubifs_findfile(struct super_block *sb, char *filename) *(next++) = '\0'; } ret = ubifs_finddir(sb, name, root_inum, &inum); - if (!ret) { + if (ret <= 0) { kfree(buf); return 0; } @@ -991,7 +991,7 @@ void ubifs_close(void) } /* Compat wrappers for common/cmd_ubifs.c */ -int ubifs_load(char *filename, unsigned long addr, u32 size) +int ubifs_load(const char *filename, unsigned long addr, u32 size) { loff_t actread; int err; diff --git a/include/configs/aquila-imx95.h b/include/configs/aquila-imx95.h new file mode 100644 index 00000000000..07d09d138cb --- /dev/null +++ b/include/configs/aquila-imx95.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copyright (c) Toradex */ + +#ifndef __AQUILA_IMX95_H +#define __AQUILA_IMX95_H + +#include <linux/sizes.h> +#include <asm/arch/imx-regs.h> + +#define CFG_SYS_UBOOT_BASE \ + (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512) + +/* module has 8GB, 2GB from 0x80000000..0xffffffff, 6GB above */ +#define SZ_6G _AC(0x180000000, ULL) + +/* first 256MB reserved for firmware */ +#define CFG_SYS_INIT_RAM_ADDR 0x90000000 +#define CFG_SYS_INIT_RAM_SIZE SZ_2M + +#define CFG_SYS_SDRAM_BASE 0x90000000 +#define PHYS_SDRAM 0x90000000 +#define PHYS_SDRAM_SIZE (SZ_2G - SZ_256M) +#define PHYS_SDRAM_2_SIZE SZ_6G + +#define CFG_SYS_SECURE_SDRAM_BASE 0x8A000000 /* Secure DDR region for A55, SPL could use first 2MB */ +#define CFG_SYS_SECURE_SDRAM_SIZE 0x06000000 + +#endif diff --git a/include/configs/evb_ast2700.h b/include/configs/evb_ast2700.h new file mode 100644 index 00000000000..6b73eddc1af --- /dev/null +++ b/include/configs/evb_ast2700.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) ASPEED Technology Inc. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/aspeed-common.h> + +/* Extra ENV for Boot Command */ +#define STR_HELPER(n) #n +#define STR(n) STR_HELPER(n) + +#define CFG_SYS_UBOOT_BASE CONFIG_TEXT_BASE + +#define CFG_EXTRA_ENV_SETTINGS \ + "bootspi=fdt addr ${fdtspiaddr} && " \ + "fdt header get fitsize totalsize && " \ + "cp.b ${fdtspiaddr} ${loadaddr} ${fitsize} && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "loadaddr=" STR(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootside=a\0" \ + "rootfs=rofs-a\0" \ + "setmmcargs=setenv bootargs ${bootargs} " \ + "rootwait root=PARTLABEL=${rootfs}\0" \ + "boota=setenv bootpart 2; setenv rootfs rofs-a; " \ + "run setmmcargs; " \ + "ext4load mmc 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "bootb=setenv bootpart 3; setenv rootfs rofs-b; " \ + "run setmmcargs; " \ + "ext4load mmc 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "bootmmc=if test \"${bootside}\" = \"b\"; " \ + "then run bootb; run boota; " \ + "else run boota; run bootb; fi\0" \ + "setufsargs=setenv bootargs ${bootargs} " \ + "rootwait root=PARTLABEL=${rootfs}\0" \ + "ufsboota=setenv bootpart 2; setenv rootfs rofs-a; " \ + "run setufsargs; " \ + "ext4load scsi 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "ufsbootb=setenv bootpart 3; setenv rootfs rofs-b; " \ + "run setufsargs; " \ + "ext4load scsi 0:${bootpart} ${loadaddr} fitImage && " \ + "bootm ${loadaddr}; " \ + "echo Error loading kernel FIT image\0" \ + "bootufs=if test \"${bootside}\" = \"b\"; " \ + "then run ufsbootb; run ufsboota; " \ + "else run ufsboota; run ufsbootb; fi\0" \ + "verify=no\0" \ + "" +#endif /* __CONFIG_H */ diff --git a/include/configs/ls1028ardb.h b/include/configs/ls1028ardb.h index 613abc50567..1811825baeb 100644 --- a/include/configs/ls1028ardb.h +++ b/include/configs/ls1028ardb.h @@ -50,85 +50,26 @@ /* Initial environment variables */ #ifndef SPL_NO_ENV #undef CFG_EXTRA_ENV_SETTINGS -#define CFG_EXTRA_ENV_SETTINGS \ - "board=ls1028ardb\0" \ - "hwconfig=fsl_ddr:bank_intlv=auto\0" \ - "fdtfile=fsl-ls1028a-rdb.dtb\0" \ - "image=Image\0" \ - "extra_bootargs=iommu.passthrough=1 arm-smmu.disable_bypass=0\0" \ - "othbootargs=video=1920x1080-32@60 cma=640M\0" \ - "ramdisk_addr=0x800000\0" \ - "ramdisk_size=0x2000000\0" \ - "bootm_size=0x10000000\0" \ - "kernel_addr=0x01000000\0" \ - "scriptaddr=0x80000000\0" \ - "scripthdraddr=0x80080000\0" \ - "fdtheader_addr_r=0x80100000\0" \ - "kernelheader_addr_r=0x80200000\0" \ - "load_addr=0xa0000000\0" \ - "kernel_addr_r=0x81000000\0" \ - "fdt_addr_r=0x90000000\0" \ - "ramdisk_addr_r=0xa0000000\0" \ - "kernel_start=0x1000000\0" \ - "kernelheader_start=0x600000\0" \ - "kernel_load=0xa0000000\0" \ - "kernel_size=0x2800000\0" \ - "kernelheader_size=0x40000\0" \ - "kernel_addr_sd=0x8000\0" \ - "kernel_size_sd=0x14000\0" \ - "kernelhdr_addr_sd=0x3000\0" \ - "kernelhdr_size_sd=0x20\0" \ - "console=ttyS0,115200\0" \ - "console_dbg=earlycon=uart8250,mmio,0x21c0500\0" \ - BOOTENV \ - "boot_scripts=ls1028ardb_boot.scr\0" \ - "boot_script_hdr=hdr_ls1028ardb_bs.out\0" \ - "scan_dev_for_boot_part=" \ - "part list ${devtype} ${devnum} devplist; " \ - "env exists devplist || setenv devplist 1; " \ - "for distro_bootpart in ${devplist}; do " \ - "if fstype ${devtype} " \ - "${devnum}:${distro_bootpart} " \ - "bootfstype; then " \ - "run scan_dev_for_boot; " \ - "fi; " \ - "done\0" \ - "boot_a_script=" \ - "load ${devtype} ${devnum}:${distro_bootpart} " \ - "${scriptaddr} ${prefix}${script}; " \ - "env exists secureboot && load ${devtype} " \ - "${devnum}:${distro_bootpart} " \ +#define CFG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "boot_scripts=ls1028ardb_boot.scr\0" \ + "scan_dev_for_boot_part=" \ + "part list ${devtype} ${devnum} devplist; " \ + "env exists devplist || setenv devplist 1; " \ + "for distro_bootpart in ${devplist}; do " \ + "if fstype ${devtype} " \ + "${devnum}:${distro_bootpart} " \ + "bootfstype; then " \ + "run scan_dev_for_boot; " \ + "fi; " \ + "done\0" \ + "boot_a_script=" \ + "load ${devtype} ${devnum}:${distro_bootpart} " \ + "${scriptaddr} ${prefix}${script}; " \ + "env exists secureboot && load ${devtype} " \ + "${devnum}:${distro_bootpart} " \ "${scripthdraddr} ${prefix}${boot_script_hdr} " \ - "&& esbc_validate ${scripthdraddr};" \ - "source ${scriptaddr}\0" \ - "xspi_bootcmd=echo Trying load from FlexSPI flash ...;" \ - "sf probe 0:0 && sf read $load_addr " \ - "$kernel_start $kernel_size ; env exists secureboot &&" \ - "sf read $kernelheader_addr_r $kernelheader_start " \ - "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\ - " bootm $load_addr#$board\0" \ - "xspi_hdploadcmd=echo Trying load HDP firmware from FlexSPI...;" \ - "sf probe 0:0 && sf read $load_addr 0x940000 0x30000 " \ - "&& hdp load $load_addr 0x2000\0" \ - "sd_bootcmd=echo Trying load from SD ...;" \ - "mmc dev 0;mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" \ - "sd_hdploadcmd=echo Trying load HDP firmware from SD..;" \ - "mmc dev 0;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ - "&& hdp load $load_addr 0x2000\0" \ - "emmc_bootcmd=echo Trying load from EMMC ..;" \ - "mmc dev 1;mmcinfo; mmc read $load_addr " \ - "$kernel_addr_sd $kernel_size_sd && " \ - "env exists secureboot && mmc read $kernelheader_addr_r " \ - "$kernelhdr_addr_sd $kernelhdr_size_sd " \ - " && esbc_validate ${kernelheader_addr_r};" \ - "bootm $load_addr#$board\0" \ - "emmc_hdploadcmd=echo Trying load HDP firmware from EMMC..;" \ - "mmc dev 1;mmcinfo;mmc read $load_addr 0x4a00 0x200 " \ - "&& hdp load $load_addr 0x2000\0" + "&& esbc_validate ${scripthdraddr};" \ + "source ${scriptaddr}\0" #endif #endif /* __LS1028A_RDB_H */ diff --git a/include/configs/mt7987.h b/include/configs/mt7987.h deleted file mode 100644 index 18ed3c7a55b..00000000000 --- a/include/configs/mt7987.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Configuration for MediaTek MT7987 SoC - * - * Copyright (C) 2025 MediaTek Inc. - * Author: Sam Shih <[email protected]> - */ - -#ifndef __MT7987_H -#define __MT7987_H - -#define CFG_MAX_MEM_MAPPED 0xC0000000 - -#endif diff --git a/include/configs/mt7988.h b/include/configs/mt7988.h deleted file mode 100644 index e63825a5a19..00000000000 --- a/include/configs/mt7988.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Configuration for MediaTek MT7988 SoC - * - * Copyright (C) 2022 MediaTek Inc. - * Author: Sam Shih <[email protected]> - */ - -#ifndef __MT7988_H -#define __MT7988_H - -#define CFG_MAX_MEM_MAPPED 0xC0000000 - -#endif diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index ef2848b71f3..d3a57a10a16 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -8,133 +8,11 @@ #ifndef __MX6QSABRE_COMMON_CONFIG_H #define __MX6QSABRE_COMMON_CONFIG_H -#include <linux/stringify.h> - #include "mx6_common.h" /* MMC Configs */ #define CFG_SYS_FSL_ESDHC_ADDR 0 -#ifdef CONFIG_SUPPORT_EMMC_BOOT -#define EMMC_ENV \ - "emmcdev=2\0" \ - "update_emmc_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "if mmc dev ${emmcdev} 1; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" -#else -#define EMMC_ENV "" -#endif - -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "fdtfile=undefined\0" \ - "fdt_addr=0x18000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "console=" CONSOLE_DEV "\0" \ - "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ - "dfu_alt_info_spl=spl raw 0x400\0" \ - "dfu_alt_info_img=u-boot raw 0x10000\0" \ - "dfu_alt_info=spl raw 0x400\0" \ - "initrd_high=0xffffffff\0" \ - "splashimage=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "mmcdev=" __stringify(CONFIG_ENV_MMC_DEVICE_INDEX) "\0" \ - "mmcpart=1\0" \ - "finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \ - "update_sd_firmware=" \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "if mmc dev ${mmcdev}; then " \ - "if ${get_cmd} ${update_sd_firmware_filename}; then " \ - "setexpr fw_sz ${filesize} / 0x200; " \ - "setexpr fw_sz ${fw_sz} + 1; " \ - "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ - "fi; " \ - "fi\0" \ - EMMC_ENV \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=PARTUUID=${uuid} rootwait rw\0" \ - "loadbootscript=" \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || " \ - "load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \ - "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || " \ - "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run finduuid; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $fdtfile = undefined; then " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabreauto.dtb; fi; " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabreauto.dtb; fi; " \ - "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabreauto.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \ - "setenv fdtfile imx6qp-sabresd.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \ - "setenv fdtfile imx6q-sabresd.dtb; fi; " \ - "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \ - "setenv fdtfile imx6dl-sabresd.dtb; fi; " \ - "if test $fdtfile = undefined; then " \ - "echo WARNING: Could not determine dtb to use; fi; " \ - "fi;\0" \ - /* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index e491af3e927..b5602def87d 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -9,7 +9,6 @@ #define __MX6SABREAUTO_CONFIG_H #define CFG_MXC_UART_BASE UART4_BASE -#define CONSOLE_DEV "ttymxc3" #define CFG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} } diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index e34947c94d0..1ea08f835dd 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -9,7 +9,6 @@ #define __MX6SABRESD_CONFIG_H #define CFG_MXC_UART_BASE UART1_BASE -#define CONSOLE_DEV "ttymxc0" #include "mx6sabre_common.h" diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 88b535e1bd0..a535163fd19 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -9,7 +9,6 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h> -#include <linux/stringify.h> #include "mx6_common.h" #include <asm/mach-imx/gpio.h> @@ -23,78 +22,6 @@ #define CFG_SYS_FSL_USDHC_NUM 2 #endif -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttymxc0\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=undefined\0" \ - "fdt_addr=0x83000000\0" \ - "boot_fdt=try\0" \ - "ip_dyn=yes\0" \ - "videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "findfdt="\ - "if test $fdt_file = undefined; then " \ - "if test $board_name = ULZ-EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ulz-14x14-evk.dtb; fi; " \ - "if test $board_name = EVK && test $board_rev = 14X14; then " \ - "setenv fdt_file imx6ull-14x14-evk.dtb; fi; " \ - "if test $fdt_file = undefined; then " \ - "echo WARNING: Could not determine dtb to use; " \ - "fi; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - /* Miscellaneous configurable options */ /* Physical Memory Map */ diff --git a/include/configs/mx7ulp_evk.h b/include/configs/mx7ulp_evk.h index 21dbec837f0..f36265f13e6 100644 --- a/include/configs/mx7ulp_evk.h +++ b/include/configs/mx7ulp_evk.h @@ -24,69 +24,6 @@ #define PHYS_SDRAM_SIZE SZ_1G #define CFG_SYS_SDRAM_BASE PHYS_SDRAM -#define CFG_EXTRA_ENV_SETTINGS \ - "script=boot.scr\0" \ - "image=zImage\0" \ - "console=ttyLP0\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_file=imx7ulp-evk.dtb\0" \ - "fdt_addr=0x63000000\0" \ - "boot_fdt=try\0" \ - "earlycon=lpuart32,0x402D0010\0" \ - "ip_dyn=yes\0" \ - "mmcdev="__stringify(CONFIG_ENV_MMC_DEVICE_INDEX)"\0" \ - "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ - "mmcautodetect=yes\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "loadbootscript=" \ - "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ - "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - "netargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/nfs " \ - "ip=:::::eth0:dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ - "netboot=echo Booting from net ...; " \ - "run netargs; " \ - "if test ${ip_dyn} = yes; then " \ - "setenv get_cmd dhcp; " \ - "else " \ - "setenv get_cmd tftp; " \ - "fi; " \ - "usb start; "\ - "${get_cmd} ${image}; " \ - "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ - "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ - "else " \ - "if test ${boot_fdt} = try; then " \ - "bootz; " \ - "else " \ - "echo WARN: Cannot load the DT; " \ - "fi; " \ - "fi; " \ - "else " \ - "bootz; " \ - "fi;\0" \ - #define CFG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CFG_SYS_INIT_RAM_SIZE SZ_256K diff --git a/include/cros_ec.h b/include/cros_ec.h index 4ef34815e35..6e5153ceb6a 100644 --- a/include/cros_ec.h +++ b/include/cros_ec.h @@ -12,6 +12,7 @@ #include <ec_commands.h> #include <cros_ec_message.h> #include <asm/gpio.h> +#include <dm/device.h> #include <dm/of_extra.h> /* @@ -316,8 +317,10 @@ struct dm_cros_ec_ops { int (*get_switches)(struct udevice *dev); }; -#define dm_cros_ec_get_ops(dev) \ - ((struct dm_cros_ec_ops *)(dev)->driver->ops) +static inline const struct dm_cros_ec_ops *dm_cros_ec_get_ops(struct udevice *dev) +{ + return (const struct dm_cros_ec_ops *)(dev->driver->ops); +} int cros_ec_register(struct udevice *dev); diff --git a/include/dm/device.h b/include/dm/device.h index 7bcf6df2892..5d700888503 100644 --- a/include/dm/device.h +++ b/include/dm/device.h @@ -388,7 +388,7 @@ struct driver { const void *ops; /* driver-specific operations */ uint32_t flags; #if CONFIG_IS_ENABLED(ACPIGEN) - struct acpi_ops *acpi_ops; + const struct acpi_ops *acpi_ops; #endif }; diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h index e41baea6200..36db47802c7 100644 --- a/include/dm/pinctrl.h +++ b/include/dm/pinctrl.h @@ -481,6 +481,34 @@ enum pin_config_param { PIN_CONFIG_MAX = 255, /* 0xFF */ }; +/* + * Helpful configuration macro to be used in tables etc. + */ +#define PIN_CONF_PACKED(p, a) ((a << 8) | ((unsigned long) p & 0xffUL)) + +/* + * The following inlines stuffs a configuration parameter and data value + * into and out of an unsigned long argument, as used by the generic pin config + * system. We put the parameter in the lower 8 bits and the argument in the + * upper 24 bits. + */ + +static inline enum pin_config_param pinconf_to_config_param(unsigned long config) +{ + return (enum pin_config_param) (config & 0xffUL); +} + +static inline u32 pinconf_to_config_argument(unsigned long config) +{ + return (u32) ((config >> 8) & 0xffffffUL); +} + +static inline unsigned long pinconf_to_config_packed(enum pin_config_param param, + u32 argument) +{ + return PIN_CONF_PACKED(param, argument); +} + #if CONFIG_IS_ENABLED(PINCTRL_GENERIC) /** * pinctrl_generic_set_state() - Generic set_state operation diff --git a/include/env/nxp/mx6sabre_common.env b/include/env/nxp/mx6sabre_common.env new file mode 100644 index 00000000000..5346cd4e953 --- /dev/null +++ b/include/env/nxp/mx6sabre_common.env @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ + +script=boot.scr +image=zImage +fdtfile=undefined +fdt_addr=0x18000000 +boot_fdt=try +ip_dyn=yes +dfuspi=dfu 0 sf 0:0:10000000:0 +dfu_alt_info_spl=spl raw 0x400 +dfu_alt_info_img=u-boot raw 0x10000 +dfu_alt_info=spl raw 0x400 +initrd_high=0xffffffff +splashimage=CONFIG_SYS_LOAD_ADDR +mmcdev=CONFIG_ENV_MMC_DEVICE_INDEX +mmcpart=1 +finduuid=part uuid mmc ${mmcdev}:2 uuid +update_sd_firmware=if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if mmc dev ${mmcdev}; then + if ${get_cmd} ${update_sd_firmware_filename}; then + setexpr fw_sz ${filesize} / 0x200; + setexpr fw_sz ${fw_sz} + 1; + mmc write ${loadaddr} 0x2 ${fw_sz}; + fi; + fi +#ifdef CONFIG_SUPPORT_EMMC_BOOT +emmcdev=2 +update_emmc_firmware=if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + if ${get_cmd} ${update_sd_firmware_filename}; then + if mmc dev ${emmcdev} 1; then + setexpr fw_sz ${filesize} / 0x200; + setexpr fw_sz ${fw_sz} + 1; + mmc write ${loadaddr} 0x2 ${fw_sz}; + fi; + fi +#endif +mmcargs=setenv bootargs console=${console},${baudrate} root=PARTUUID=${uuid} rootwait rw +loadbootscript=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || + load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script}; +bootscript=echo Running bootscript from mmc ...; source +loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || + load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image} +loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || + load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile} +mmcboot=echo Booting from mmc ...; + run finduuid; + run mmcargs; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if run loadfdt; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +netargs=setenv bootargs console=${console},${baudrate} root=/dev/nfs + ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp +netboot=echo Booting from net ...; + run netargs; + if test ${ip_dyn} = yes; then + setenv get_cmd dhcp; + else + setenv get_cmd tftp; + fi; + ${get_cmd} ${image}; + if test ${boot_fdt} = yes || test ${boot_fdt} = try; then + if ${get_cmd} ${fdt_addr} ${fdtfile}; then + bootz ${loadaddr} - ${fdt_addr}; + else + if test ${boot_fdt} = try; then + bootz; + else + echo WARN: Cannot load the DT; + fi; + fi; + else + bootz; + fi; +findfdt=if test $fdtfile = undefined; then + if test $board_name = SABREAUTO && test $board_rev = MX6QP; then + setenv fdtfile imx6qp-sabreauto.dtb; + fi; + if test $board_name = SABREAUTO && test $board_rev = MX6Q; then + setenv fdtfile imx6q-sabreauto.dtb; + fi; + if test $board_name = SABREAUTO && test $board_rev = MX6DL; then + setenv fdtfile imx6dl-sabreauto.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6QP; then + setenv fdtfile imx6qp-sabresd.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6Q; then + setenv fdtfile imx6q-sabresd.dtb; + fi; + if test $board_name = SABRESD && test $board_rev = MX6DL; then + setenv fdtfile imx6dl-sabresd.dtb; + fi; + if test $fdtfile = undefined; then + echo WARNING: Could not determine dtb to use; + fi; + fi; diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h index 63928f17322..18cf57aeb2c 100644 --- a/include/linux/bitfield.h +++ b/include/linux/bitfield.h @@ -16,6 +16,7 @@ * FIELD_{GET,PREP} macros take as first parameter shifted mask * from which they extract the base mask and shift amount. * Mask must be a compilation time constant. + * field_{get,prep} are variants that take a non-const mask. * * Example: * @@ -60,7 +61,7 @@ #define __bf_cast_unsigned(type, x) ((__unsigned_scalar_typeof(type))(x)) -#define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \ +#define __BF_FIELD_CHECK_MASK(_mask, _val, _pfx) \ ({ \ BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \ _pfx "mask is not constant"); \ @@ -69,13 +70,33 @@ ~((_mask) >> __bf_shf(_mask)) & \ (0 + (_val)) : 0, \ _pfx "value too large for the field"); \ - BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \ - __bf_cast_unsigned(_reg, ~0ull), \ - _pfx "type of reg too small for mask"); \ __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \ (1ULL << __bf_shf(_mask))); \ }) +#define __BF_FIELD_CHECK_REG(mask, reg, pfx) \ + BUILD_BUG_ON_MSG(__bf_cast_unsigned(mask, mask) > \ + __bf_cast_unsigned(reg, ~0ull), \ + pfx "type of reg too small for mask") + +#define __BF_FIELD_CHECK(mask, reg, val, pfx) \ + ({ \ + __BF_FIELD_CHECK_MASK(mask, val, pfx); \ + __BF_FIELD_CHECK_REG(mask, reg, pfx); \ + }) + +#define __FIELD_PREP(mask, val, pfx) \ + ({ \ + __BF_FIELD_CHECK_MASK(mask, val, pfx); \ + ((typeof(mask))(val) << __bf_shf(mask)) & (mask); \ + }) + +#define __FIELD_GET(mask, reg, pfx) \ + ({ \ + __BF_FIELD_CHECK_MASK(mask, 0U, pfx); \ + (typeof(mask))(((reg) & (mask)) >> __bf_shf(mask)); \ + }) + /** * FIELD_MAX() - produce the maximum value representable by a field * @_mask: shifted mask defining the field's length and position @@ -112,8 +133,8 @@ */ #define FIELD_PREP(_mask, _val) \ ({ \ - __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ - ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ + __BF_FIELD_CHECK_REG(_mask, 0ULL, "FIELD_PREP: "); \ + __FIELD_PREP(_mask, _val, "FIELD_PREP: "); \ }) #define __BF_CHECK_POW2(n) BUILD_BUG_ON_ZERO(((n) & ((n) - 1)) != 0) @@ -152,8 +173,8 @@ */ #define FIELD_GET(_mask, _reg) \ ({ \ - __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \ - (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + __BF_FIELD_CHECK_REG(_mask, _reg, "FIELD_GET: "); \ + __FIELD_GET(_mask, _reg, "FIELD_GET: "); \ }) extern void __compiletime_error("value doesn't fit into mask") @@ -203,4 +224,62 @@ __MAKE_OP(64) #undef __MAKE_OP #undef ____MAKE_OP +#define __field_prep(mask, val) \ + ({ \ + __auto_type __mask = (mask); \ + typeof(__mask) __val = (val); \ + unsigned int __shift = BITS_PER_TYPE(__mask) <= 32 ? \ + __ffs(__mask) : __ffs64(__mask); \ + (__val << __shift) & __mask; \ + }) + +#define __field_get(mask, reg) \ + ({ \ + __auto_type __mask = (mask); \ + typeof(__mask) __reg = (reg); \ + unsigned int __shift = BITS_PER_TYPE(__mask) <= 32 ? \ + __ffs(__mask) : __ffs64(__mask); \ + (__reg & __mask) >> __shift; \ + }) + +/** + * field_prep() - prepare a bitfield element + * @mask: shifted mask defining the field's length and position, must be + * non-zero + * @val: value to put in the field + * + * Return: field value masked and shifted to its final destination + * + * field_prep() masks and shifts up the value. The result should be + * combined with other fields of the bitfield using logical OR. + * Unlike FIELD_PREP(), @mask is not limited to a compile-time constant. + * Typical usage patterns are a value stored in a table, or calculated by + * shifting a constant by a variable number of bits. + * If you want to ensure that @mask is a compile-time constant, please use + * FIELD_PREP() directly instead. + */ +#define field_prep(mask, val) \ + (__builtin_constant_p(mask) ? __FIELD_PREP(mask, val, "field_prep: ") \ + : __field_prep(mask, val)) + +/** + * field_get() - extract a bitfield element + * @mask: shifted mask defining the field's length and position, must be + * non-zero + * @reg: value of entire bitfield + * + * Return: extracted field value + * + * field_get() extracts the field specified by @mask from the + * bitfield passed in as @reg by masking and shifting it down. + * Unlike FIELD_GET(), @mask is not limited to a compile-time constant. + * Typical usage patterns are a value stored in a table, or calculated by + * shifting a constant by a variable number of bits. + * If you want to ensure that @mask is a compile-time constant, please use + * FIELD_GET() directly instead. + */ +#define field_get(mask, reg) \ + (__builtin_constant_p(mask) ? __FIELD_GET(mask, reg, "field_get: ") \ + : __field_get(mask, reg)) + #endif diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 29e0da48de8..52eea4f8380 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -15,6 +15,7 @@ #define BIT_ULL_MASK(nr) (1ULL << ((nr) % BITS_PER_LONG_LONG)) #define BIT_ULL_WORD(nr) ((nr) / BITS_PER_LONG_LONG) #define BITS_PER_BYTE 8 +#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long)) #endif diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 2d754fa4287..366f2d968a3 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -246,6 +246,11 @@ struct clk *clk_register_fixed_factor(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk *clk_register_divider_table(struct udevice *dev, const char *name, + const char *parent_name, unsigned long flags, + void __iomem *reg, u8 shift, u8 width, + u8 clk_divider_flags, const struct clk_div_table *table); + struct clk *clk_register_divider(struct udevice *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h new file mode 100644 index 00000000000..32b56e0ab18 --- /dev/null +++ b/include/linux/pinctrl/pinctrl.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __LINUX_PINCTRL_PINCTRL_H +#define __LINUX_PINCTRL_PINCTRL_H + +#include <linux/types.h> + +/** + * struct pingroup - provides information on pingroup + * @name: a name for pingroup + * @pins: an array of pins in the pingroup + * @npins: number of pins in the pingroup + */ +struct pingroup { + const char *name; + const unsigned int *pins; + size_t npins; +}; + +/* Convenience macro to define a single named or anonymous pingroup */ +#define PINCTRL_PINGROUP(_name, _pins, _npins) \ +(struct pingroup) { \ + .name = _name, \ + .pins = _pins, \ + .npins = _npins, \ +} + +/** + * struct pinctrl_pin_desc - boards/machines provide information on their + * pins, pads or other muxable units in this struct + * @number: unique pin number from the global pin number space + * @name: a name for this pin + * @drv_data: driver-defined per-pin data. pinctrl core does not touch this + */ +struct pinctrl_pin_desc { + unsigned int number; + const char *name; + void *drv_data; +}; + +/* Convenience macro to define a single named or anonymous pin descriptor */ +#define PINCTRL_PIN(_number, _name) \ +(struct pinctrl_pin_desc) { \ + .number = _number, \ + .name = _name, \ +} + +#define PINCTRL_PIN_ANON(_number) \ +(struct pinctrl_pin_desc) { \ + .number = _number, \ +} + +/** + * struct pinfunction - Description about a function + * @name: Name of the function + * @groups: An array of groups for this function + * @ngroups: Number of groups in @groups + * @flags: Additional pin function flags + */ +struct pinfunction { + const char *name; + const char * const *groups; + size_t ngroups; +}; + +/* Convenience macro to define a single named pinfunction */ +#define PINCTRL_PINFUNCTION(_name, _groups, _ngroups) \ +(struct pinfunction) { \ + .name = (_name), \ + .groups = (_groups), \ + .ngroups = (_ngroups), \ +} + +#endif /* __LINUX_PINCTRL_PINCTRL_H */ diff --git a/include/net-lwip.h b/include/net-lwip.h index 20cb0992cce..5d0627eb271 100644 --- a/include/net-lwip.h +++ b/include/net-lwip.h @@ -35,6 +35,7 @@ int eth_init_state_only(void); /* Set active state */ int net_lwip_dns_init(void); int net_lwip_eth_start(void); +void net_lwip_eth_stop(void); struct netif *net_lwip_new_netif(struct udevice *udev); struct netif *net_lwip_new_netif_noip(struct udevice *udev); void net_lwip_remove_netif(struct netif *netif); diff --git a/include/sandbox_host.h b/include/sandbox_host.h index f7a5fc67230..1330358ef7a 100644 --- a/include/sandbox_host.h +++ b/include/sandbox_host.h @@ -9,16 +9,25 @@ #define __SANDBOX_HOST__ /** + * Device flags. + */ +enum host_platform_flags { + HOST_FLAG_BROKEN = BIT(0), /** Simulate broken device */ +}; + +/** * struct host_sb_plat - platform data for a host device * * @label: Label for this device (allocated) * @filename: Name of file this is attached to, or NULL (allocated) * @fd: File descriptor of file, or 0 for none (file is not open) + * @flags: Device flags (e.g. for unit tests). */ struct host_sb_plat { char *label; char *filename; int fd; + unsigned int flags; }; /** @@ -122,4 +131,13 @@ struct udevice *host_get_cur_dev(void); */ void host_set_cur_dev(struct udevice *dev); +/** + * host_set_flags_by_label() - Set the host device test flags + * + * @label: Label of the attachment, e.g. "test1" + * @flags: Device flags + * Returns: 0 if OK, -ve on error + */ +int host_set_flags_by_label(const char *label, unsigned int flags); + #endif /* __SANDBOX_HOST__ */ diff --git a/include/sysreset.h b/include/sysreset.h index d1cc9ebc542..ff20abdeed3 100644 --- a/include/sysreset.h +++ b/include/sysreset.h @@ -43,24 +43,6 @@ struct sysreset_ops { * (in which case this method will not actually return) */ int (*request)(struct udevice *dev, enum sysreset_t type); - - /** - * @request_arg: Reset handler implementations that might need to process - * arguments given to the 'reset' command. - * - * Note that this function may return before the reset takes effect. - * - * @dev: Device to be used for system reset - * @argc: No. of items in @argv - * @argv: Arguments given to 'reset' command - * Return: - * -EINPROGRESS if the reset has started and will complete soon - * -EPROTONOSUPPORT if not supported by this device - * 0 if the reset has already happened - * (in which case this method will not actually return) - */ - int (*request_arg)(struct udevice *dev, int argc, char * const argv[]); - /** * @get_status: get printable reset status information * diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h index ea0db69c72a..bdf5645de3d 100644 --- a/include/ubi_uboot.h +++ b/include/ubi_uboot.h @@ -44,15 +44,107 @@ #endif /* functions */ -extern int ubi_mtd_param_parse(const char *val, struct kernel_param *kp); -extern int ubi_init(void); -extern void ubi_exit(void); -extern int ubi_part(char *part_name, const char *vid_header_offset); -extern int ubi_volume_write(char *volume, void *buf, loff_t offset, size_t size); -extern int ubi_volume_read(char *volume, char *buf, loff_t offset, size_t size); +int ubi_mtd_param_parse(const char *val, struct kernel_param *kp); +int ubi_init(void); +void ubi_exit(void); + +/** + * ubi_detach() - detach UBI from MTD partition + * + * This function performs the cleanup of the UBI subsystem to make sure the + * MTD partition can be safely used for another purpose, or be attached again + * with ubi_part(). + * + * Any mounted UBIFS will be unmounted automatically. + * + * Return: 0 + */ +int ubi_detach(void); + +/** + * ubi_part() - attach UBI to MTD partition + * @part_name: name of the MTD partition to attach + * @vid_header_offset: VID header offset (string) + * + * This function detaches any existing UBI device, then probes for the + * specified MTD partition, and then scans it to initialize UBI. + * + * @vid_header_offset is optional and is usually set to NULL. + * + * Return: 0 on success, or -ve on error. + */ +int ubi_part(const char *part_name, const char *vid_header_offset); + +/** + * ubi_volume_write() - write data to UBI volume + * @volume: name of the volume to write to + * @buf: data buffer to be written + * @offset: start offset for writing + * @size: number of bytes to write + * + * This function writes data to the specific UBI volume. If the offset is zero, + * it initiates a full volume update. Otherwise, it performs an offset-based + * write using LEB changes. + * + * Return: 0 on success, or -ve on error. + */ +int ubi_volume_write(const char *volume, const void *buf, loff_t offset, + size_t size); + +/** + * ubi_volume_read() - read data from UBI volume + * @volume: name of the volume to read from + * @buf: buffer to hold the read data + * @offset: start offset for reading + * @size: number of bytes to read + * + * This function reads data from the specified UBI volume. If @size is zero, + * the function reads the entire volume content starting from @offset. + * + * Return: 0 on success, or -ve on error. + */ +int ubi_volume_read(const char *volume, void *buf, loff_t offset, size_t size); + +/** + * ubi_create_vol() - create UBI volume + * @volume: name of the volume to create + * @size: size of the volume in bytes + * @dynamic: create dynamic volume if set to true + * @vol_id: volume ID + * @skipcheck: skip CRC check on this volume if set to true + * + * This function creates a new UBI volume with the specified parameters. + * If @size is negative, all available space will be used. + * For volume ID auto assignment, pass %UBI_VOL_NUM_AUTO to @vol_id. + * + * Return: 0 on success, or -ve on error. + */ +int ubi_create_vol(const char *volume, int64_t size, bool dynamic, int vol_id, + bool skipcheck); + +/** + * ubi_find_volume() - find UBI volume by name + * @volume: name of the volume to find + * + * This function searches for a UBI volume with the specified name in the + * current UBI device. + * + * Return: pointer to the UBI volume structure, or %NULL if not found. + */ +struct ubi_volume *ubi_find_volume(const char *volume); + +/** + * ubi_remove_vol() - remove UBI volume + * @volume: name of the volume to remove + * + * This function removes an existing UBI volume from the current UBI device. + * + * Return: 0 on success, or -ve on error. + */ +int ubi_remove_vol(const char *volume); extern struct ubi_device *ubi_devices[]; -int cmd_ubifs_mount(char *vol_name); +int cmd_ubifs_mount(const char *vol_name); int cmd_ubifs_umount(void); #if IS_ENABLED(CONFIG_UBI_BLOCK) diff --git a/include/ubifs_uboot.h b/include/ubifs_uboot.h index db8a29e9bbd..0877dd84f99 100644 --- a/include/ubifs_uboot.h +++ b/include/ubifs_uboot.h @@ -18,10 +18,10 @@ struct blk_desc; struct disk_partition; int ubifs_init(void); -int uboot_ubifs_mount(char *vol_name); +int uboot_ubifs_mount(const char *vol_name); void uboot_ubifs_umount(void); int ubifs_is_mounted(void); -int ubifs_load(char *filename, unsigned long addr, u32 size); +int ubifs_load(const char *filename, unsigned long addr, u32 size); int ubifs_set_blk_dev(struct blk_desc *rbdd, struct disk_partition *info); int ubifs_ls(const char *dir_name); diff --git a/lib/efi_selftest/efi_selftest.c b/lib/efi_selftest/efi_selftest.c index 2b95713afb4..b284132c0a2 100644 --- a/lib/efi_selftest/efi_selftest.c +++ b/lib/efi_selftest/efi_selftest.c @@ -284,7 +284,7 @@ efi_status_t EFIAPI efi_selftest(efi_handle_t image_handle, * implemented we should call * st_boottime->exit(image_handle, EFI_SUCCESS, 0, NULL); * here, cf. - * https://lists.denx.de/pipermail/u-boot/2017-October/308720.html + * https://patch.msgid.link/[email protected]/ */ return EFI_SUCCESS; } diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig index 12a71c3df6f..deaad0bba02 100644 --- a/lib/rsa/Kconfig +++ b/lib/rsa/Kconfig @@ -94,14 +94,14 @@ config RSA_FREESCALE_EXP bool "Enable RSA Modular Exponentiation with FSL crypto accelerator" depends on DM && FSL_CAAM && !ARCH_MX7 && !ARCH_MX7ULP && !ARCH_MX6 && !ARCH_MX5 help - Enables driver for RSA modular exponentiation using Freescale cryptographic - accelerator - CAAM. + Enables driver for RSA modular exponentiation using Freescale cryptographic + accelerator - CAAM. config RSA_ASPEED_EXP bool "Enable RSA Modular Exponentiation with ASPEED crypto accelerator" depends on DM && ASPEED_ACRY help - Enables driver for RSA modular exponentiation using ASPEED cryptographic - accelerator - ACRY + Enables driver for RSA modular exponentiation using ASPEED cryptographic + accelerator - ACRY endif diff --git a/net/Kconfig b/net/Kconfig index 6be392c1564..386376ce884 100644 --- a/net/Kconfig +++ b/net/Kconfig @@ -114,15 +114,15 @@ config SERVERIP_FROM_PROXYDHCP bool "Get serverip value from Proxy DHCP response" help Allows bootfile config to be fetched from Proxy DHCP server - while IP is obtained from main DHCP server. + while IP is obtained from main DHCP server. config SERVERIP_FROM_PROXYDHCP_DELAY_MS int "# of additional milliseconds to wait for ProxyDHCP response" default 100 help Amount of additional time to wait for ProxyDHCP response after - receiving response from main DHCP server. Has no effect if - SERVERIP_FROM_PROXYDHCP is false. + receiving response from main DHCP server. Has no effect if + SERVERIP_FROM_PROXYDHCP is false. config KEEP_SERVERADDR bool "Write the server's MAC address to 'serveraddr'" diff --git a/net/cdp.c b/net/cdp.c index 6e404981d4a..300b3d5c409 100644 --- a/net/cdp.c +++ b/net/cdp.c @@ -276,7 +276,13 @@ void cdp_receive(const uchar *pkt, unsigned len) ss = (const ushort *)pkt; type = ntohs(ss[0]); tlen = ntohs(ss[1]); - if (tlen > len) + /* + * tlen includes the 4-byte TLV header, so it must be at + * least 4. Without this check a crafted tlen < 4 makes the + * "tlen -= 4" below underflow (tlen is a ushort), and a tlen + * of 0 also fails to advance pkt/len, hanging the loop. + */ + if (tlen < 4 || tlen > len) goto pkt_short; pkt += tlen; diff --git a/net/lwip/Kconfig b/net/lwip/Kconfig index 0cfd3eb2684..3beaf48ff2a 100644 --- a/net/lwip/Kconfig +++ b/net/lwip/Kconfig @@ -18,7 +18,7 @@ config LWIP_DEBUG bool "Enable debug traces in the lwIP library" help Prints messages to the console regarding network packets that go in - and out of the lwIP library. + and out of the lwIP library. config LWIP_DEBUG_RXTX bool "Dump packets sent and received by lwIP" diff --git a/net/lwip/dhcp.c b/net/lwip/dhcp.c index acdf601d7eb..18dc36ae7ca 100644 --- a/net/lwip/dhcp.c +++ b/net/lwip/dhcp.c @@ -138,18 +138,25 @@ int do_dhcp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) dev = eth_get_dev(); if (!dev) { log_err("No network device\n"); - return CMD_RET_FAILURE; + ret = CMD_RET_FAILURE; + goto out; } ret = dhcp_loop(dev); if (ret) - return ret; + goto out; if (argc > 1) { struct cmd_tbl cmdtp = {}; - return do_tftpb(&cmdtp, 0, argc, argv); + ret = do_tftpb(&cmdtp, 0, argc, argv); + goto out; } - return CMD_RET_SUCCESS; + ret = CMD_RET_SUCCESS; + +out: + net_lwip_eth_stop(); + + return ret; } diff --git a/net/lwip/dns.c b/net/lwip/dns.c index 8b7b3b7f970..b620b0611d6 100644 --- a/net/lwip/dns.c +++ b/net/lwip/dns.c @@ -91,6 +91,7 @@ int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { char *name; char *var = NULL; + int ret; if (argc == 1 || argc > 3) return CMD_RET_USAGE; @@ -103,5 +104,9 @@ int do_dns(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) if (net_lwip_eth_start() < 0) return CMD_RET_FAILURE; - return dns_loop(eth_get_dev(), name, var); + ret = dns_loop(eth_get_dev(), name, var); + + net_lwip_eth_stop(); + + return ret; } diff --git a/net/lwip/net-lwip.c b/net/lwip/net-lwip.c index 0c83c004cab..cfe5a6a640d 100644 --- a/net/lwip/net-lwip.c +++ b/net/lwip/net-lwip.c @@ -31,6 +31,7 @@ void (*push_packet)(void *, int len) = 0; int net_try_count; static int net_restarted; int net_restart_wrap; +static int net_lwip_eth_started; static uchar net_pkt_buf[(PKTBUFSRX) * PKTSIZE_ALIGN + PKTALIGN] __aligned(PKTALIGN); const u8 net_bcast_ethaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; @@ -180,11 +181,15 @@ int net_lwip_eth_start(void) { int ret; + if (net_lwip_eth_started++ > 0) + return 0; + net_init(); eth_halt(); eth_set_current(); ret = eth_init(); if (ret < 0) { + net_lwip_eth_started--; eth_halt(); return ret; } @@ -192,6 +197,17 @@ int net_lwip_eth_start(void) return 0; } +void net_lwip_eth_stop(void) +{ + if (!net_lwip_eth_started) + return; + + if (--net_lwip_eth_started) + return; + + eth_halt(); +} + static struct netif *new_netif(struct udevice *udev, bool with_ip) { unsigned char enetaddr[ARP_HLEN]; diff --git a/net/lwip/nfs.c b/net/lwip/nfs.c index 9e6b801e465..4cc36373fdd 100644 --- a/net/lwip/nfs.c +++ b/net/lwip/nfs.c @@ -187,6 +187,7 @@ static int nfs_loop(struct udevice *udev, ulong addr, char *fname, int do_nfs(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { int ret = CMD_RET_SUCCESS; + bool started = false; char *arg = NULL; char *words[2] = { }; char *fname = NULL; @@ -281,10 +282,13 @@ int do_nfs(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ret = CMD_RET_FAILURE; goto out; } + started = true; if (nfs_loop(eth_get_dev(), laddr, fname, srvip) < 0) ret = CMD_RET_FAILURE; out: + if (started) + net_lwip_eth_stop(); if (arg != net_boot_file_name) free(arg); return ret; diff --git a/net/lwip/tftp.c b/net/lwip/tftp.c index 7f3b28b8507..571c38172f9 100644 --- a/net/lwip/tftp.c +++ b/net/lwip/tftp.c @@ -261,6 +261,7 @@ static int tftp_loop(struct udevice *udev, ulong addr, char *fname, int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { int ret = CMD_RET_SUCCESS; + bool started = false; char *arg = NULL; char *words[3] = { }; char *fname = NULL; @@ -365,12 +366,15 @@ int do_tftpb(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) ret = CMD_RET_FAILURE; goto out; } + started = true; if (tftp_loop(eth_get_dev(), laddr, fname, srvip, port) < 0) ret = CMD_RET_FAILURE; else image_load_addr = laddr; out: + if (started) + net_lwip_eth_stop(); if (arg != net_boot_file_name) free(arg); return ret; diff --git a/net/lwip/wget.c b/net/lwip/wget.c index 502c0faebb2..247ece18e2b 100644 --- a/net/lwip/wget.c +++ b/net/lwip/wget.c @@ -292,46 +292,22 @@ static err_t httpc_headers_done_cb(httpc_state_t *connection, void *arg, struct #if CONFIG_IS_ENABLED(WGET_CACERT) #endif -int wget_do_request(ulong dst_addr, char *uri) +static int wget_handle_request(struct wget_ctx *ctx, bool is_https, + struct udevice *udev, struct netif *netif) { #if CONFIG_IS_ENABLED(WGET_HTTPS) altcp_allocator_t tls_allocator; #endif httpc_connection_t conn; httpc_state_t *state; - struct udevice *udev; - struct netif *netif; - struct wget_ctx ctx; - char *path; - bool is_https; - - ctx.daddr = dst_addr; - ctx.saved_daddr = dst_addr; - ctx.done = NOT_DONE; - ctx.size = 0; - ctx.prevsize = 0; - ctx.start_time = 0; - ctx.content_len = 0; - ctx.hash_count = 0; - - if (parse_url(uri, ctx.server_name, &ctx.port, &path, &is_https)) - return CMD_RET_USAGE; - - if (net_lwip_eth_start() < 0) - return CMD_RET_FAILURE; - - if (!wget_info) - wget_info = &default_wget_info; - - udev = eth_get_dev(); - - netif = net_lwip_new_netif(udev); - if (!netif) - return -1; + int ret; /* if URL with hostname init dns */ - if (!ipaddr_aton(ctx.server_name, NULL) && net_lwip_dns_init()) - return CMD_RET_FAILURE; + if (!ipaddr_aton(ctx->server_name, NULL)) { + ret = net_lwip_dns_init(); + if (ret) + return ret; + } memset(&conn, 0, sizeof(conn)); #if CONFIG_IS_ENABLED(WGET_HTTPS) @@ -353,7 +329,7 @@ int wget_do_request(ulong dst_addr, char *uri) printf("Error: cacert authentication " "mode is 'required' but no CA " "certificates given\n"); - return CMD_RET_FAILURE; + return -EINVAL; } } else if (cacert_auth_mode == AUTH_NONE) { ca = NULL; @@ -374,12 +350,11 @@ int wget_do_request(ulong dst_addr, char *uri) tls_allocator.alloc = &altcp_tls_alloc; tls_allocator.arg = altcp_tls_create_config_client(ca, ca_sz, - ctx.server_name); + ctx->server_name); if (!tls_allocator.arg) { log_err("error: Cannot create a TLS connection\n"); - net_lwip_remove_netif(netif); - return -1; + return -ENODEV; } conn.altcp_allocator = &tls_allocator; @@ -388,30 +363,70 @@ int wget_do_request(ulong dst_addr, char *uri) conn.result_fn = httpc_result_cb; conn.headers_done_fn = httpc_headers_done_cb; - ctx.path = path; - if (httpc_get_file_dns(ctx.server_name, ctx.port, path, &conn, httpc_recv_cb, - &ctx, &state)) { - net_lwip_remove_netif(netif); - return CMD_RET_FAILURE; + if (httpc_get_file_dns(ctx->server_name, ctx->port, ctx->path, &conn, + httpc_recv_cb, ctx, &state)) { + return -ENODEV; } errno = 0; - while (!ctx.done) { + while (!ctx->done) { net_lwip_rx(udev, netif); if (ctrlc()) break; } - net_lwip_remove_netif(netif); - - if (ctx.done == SUCCESS) + if (ctx->done == SUCCESS) return 0; if (errno == EPERM && !wget_info->silent) printf("Certificate verification failed\n"); - return -1; + return -errno ?: -EIO; +} + +int wget_do_request(ulong dst_addr, char *uri) +{ + struct udevice *udev; + struct wget_ctx ctx; + struct netif *netif; + bool is_https; + int ret; + + ctx.daddr = dst_addr; + ctx.saved_daddr = dst_addr; + ctx.done = NOT_DONE; + ctx.size = 0; + ctx.prevsize = 0; + ctx.start_time = 0; + ctx.content_len = 0; + ctx.hash_count = 0; + + ret = parse_url(uri, ctx.server_name, &ctx.port, &ctx.path, &is_https); + if (ret) + return ret; + + ret = net_lwip_eth_start(); + if (ret) + return ret; + + if (!wget_info) + wget_info = &default_wget_info; + + udev = eth_get_dev(); + + netif = net_lwip_new_netif(udev); + if (!netif) { + net_lwip_eth_stop(); + return -ENODEV; + } + + ret = wget_handle_request(&ctx, is_https, udev, netif); + + net_lwip_remove_netif(netif); + net_lwip_eth_stop(); + + return ret; } /** diff --git a/net/net.c b/net/net.c index ae3b977781f..61c5a6ef6c4 100644 --- a/net/net.c +++ b/net/net.c @@ -1103,6 +1103,15 @@ static struct ip_udp_hdr *__net_defragment(struct ip_udp_hdr *ip, int *lenp) *lenp = total_len + IP_HDR_SIZE; localip->ip_len = htons(*lenp); + + /* + * Mark the reassembly state empty so that any further + * fragment goes through the normal re-init path and + * rebuilds a clean hole list + */ + total_len = 0; + first_hole = 0; + return localip; } diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index d66f1ed13b1..122c8e78204 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -674,12 +674,12 @@ cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \ # The output is typically a much smaller device tree file. ifeq ($(CONFIG_VPL_BUILD),y) -fdtgrep_props := -b bootph-all -b bootph-verify $(migrate_vpl) +fdtgrep_props := -b bootph-all -b bootph-verify else ifeq ($(CONFIG_TPL_BUILD),y) -fdtgrep_props := -b bootph-all -b bootph-pre-sram $(migrate_tpl) +fdtgrep_props := -b bootph-all -b bootph-pre-sram else -fdtgrep_props := -b bootph-all -b bootph-pre-ram $(migrate_spl) +fdtgrep_props := -b bootph-all -b bootph-pre-ram endif endif @@ -699,7 +699,6 @@ quiet_cmd_fdtgrep = FDTGREP $@ $(objtree)/tools/fdtgrep -r -O dtb - -o $@ \ -P bootph-all -P bootph-pre-ram -P bootph-pre-sram \ -P bootph-verify -P bootph-some-ram \ - $(migrate_all) \ $(addprefix -P ,$(subst $\",,$(CONFIG_OF_SPL_REMOVE_PROPS))) # fdt_rm_props diff --git a/scripts/make_pip.sh b/scripts/make_pip.sh index 33ad51ada70..ffe22db199c 100755 --- a/scripts/make_pip.sh +++ b/scripts/make_pip.sh @@ -5,7 +5,7 @@ # # Usage: make_pip.sh <tool_name> [--real] # -# Where tool_name is one of patman, buildman, dtoc, binman, u_boot_pylib +# Where tool_name is one of buildman, dtoc, binman, u_boot_pylib # # and --real means to upload to the real server (otherwise the test one is used) # @@ -36,10 +36,10 @@ tool="$1" shift flags="$*" -if [[ "${tool}" =~ ^(patman|buildman|dtoc|binman|u_boot_pylib)$ ]]; then +if [[ "${tool}" =~ ^(buildman|dtoc|binman|u_boot_pylib)$ ]]; then echo "Building dist package for tool ${tool}" else - echo "Unknown tool ${tool}: use u_boot_pylib, patman, buildman, dtoc or binman" + echo "Unknown tool ${tool}: use u_boot_pylib, buildman, dtoc or binman" exit 1 fi @@ -61,8 +61,8 @@ if [ -n "${upload}" ]; then fi fi -if [[ "${tool}" =~ ^(patman|u_boot_pylib)$ ]]; then - # Leave test_util.py and patman test files alone +if [[ "${tool}" =~ ^(u_boot_pylib)$ ]]; then + # Leave test_util.py and the u_boot_pylib test files alone delete_testfiles= fi diff --git a/test/boot/bootdev.c b/test/boot/bootdev.c index 0820bf10ee0..c2eaf0b2c55 100644 --- a/test/boot/bootdev.c +++ b/test/boot/bootdev.c @@ -384,19 +384,19 @@ static int bootdev_test_hunter(struct unit_test_state *uts) ut_assert_nextline(" 2 mmc mmc_bootdev"); ut_assert_nextline(" 4 nvme nvme_bootdev"); ut_assert_nextline(" 4 qfw qfw_bootdev"); + ut_assert_nextline(" 4 host sandbox_bootdev"); ut_assert_nextline(" 4 scsi scsi_bootdev"); ut_assert_nextline(" 4 spi_flash sf_bootdev"); ut_assert_nextline(" 5 usb usb_bootdev"); ut_assert_nextline(" 4 virtio virtio_bootdev"); - ut_assert_nextline("(total hunters: 9)"); + ut_assert_nextline("(total hunters: 10)"); ut_assert_console_end(); ut_assertok(bootdev_hunt("usb1", false)); ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found"); ut_assert_console_end(); - /* USB is 8th in the list, so bit 7 */ - ut_asserteq(BIT(7), std->hunters_used); + ut_asserteq(BIT(USB_HUNTER), std->hunters_used); return 0; } @@ -417,7 +417,7 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assert_nextline("Prio Used Uclass Hunter"); ut_assert_nextlinen("----"); ut_assert_nextline(" 6 ethernet eth_bootdev"); - ut_assert_skip_to_line("(total hunters: 9)"); + ut_assert_skip_to_line("(total hunters: 10)"); ut_assert_console_end(); /* Use the MMC hunter and see that it updates */ @@ -425,7 +425,7 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assertok(run_command("bootdev hunt -l", 0)); ut_assert_skip_to_line(" 5 ide ide_bootdev"); ut_assert_nextline(" 2 * mmc mmc_bootdev"); - ut_assert_skip_to_line("(total hunters: 9)"); + ut_assert_skip_to_line("(total hunters: 10)"); ut_assert_console_end(); /* Scan all hunters */ @@ -441,6 +441,7 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assert_nextline("Hunting with: nvme"); ut_assert_nextline("Hunting with: qfw"); + ut_assert_nextline("Hunting with: host"); ut_assert_nextline("Hunting with: scsi"); ut_assert_nextline("scanning bus for devices..."); ut_assert_skip_to_line("Hunting with: spi_flash"); @@ -458,11 +459,12 @@ static int bootdev_test_cmd_hunt(struct unit_test_state *uts) ut_assert_nextline(" 2 * mmc mmc_bootdev"); ut_assert_nextline(" 4 * nvme nvme_bootdev"); ut_assert_nextline(" 4 * qfw qfw_bootdev"); + ut_assert_nextline(" 4 * host sandbox_bootdev"); ut_assert_nextline(" 4 * scsi scsi_bootdev"); ut_assert_nextline(" 4 * spi_flash sf_bootdev"); ut_assert_nextline(" 5 * usb usb_bootdev"); ut_assert_nextline(" 4 * virtio virtio_bootdev"); - ut_assert_nextline("(total hunters: 9)"); + ut_assert_nextline("(total hunters: 10)"); ut_assert_console_end(); ut_asserteq(GENMASK(MAX_HUNTER, 0), std->hunters_used); @@ -646,8 +648,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) ut_asserteq_str("scsi.id0lun0.bootdev", dev->name); ut_asserteq(BOOTFLOW_METHF_SINGLE_UCLASS, mflags); - /* SCSI is 6th in the list, so bit 5 */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER), std->hunters_used); ut_assertok(bootdev_next_label(&iter, &dev, &mflags)); ut_assert_console_end(); @@ -657,7 +658,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) mflags); /* dhcp: Ethernet is first so bit 0 */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5) | BIT(0), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER) | BIT(0), std->hunters_used); ut_assertok(bootdev_next_label(&iter, &dev, &mflags)); ut_assert_console_end(); @@ -667,7 +668,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) mflags); /* pxe: Ethernet is first so bit 0 */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5) | BIT(0), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER) | BIT(0), std->hunters_used); mflags = 123; ut_asserteq(-ENODEV, bootdev_next_label(&iter, &dev, &mflags)); @@ -675,7 +676,7 @@ static int bootdev_test_next_label(struct unit_test_state *uts) ut_assert_console_end(); /* no change */ - ut_asserteq(BIT(MMC_HUNTER) | BIT(5) | BIT(0), std->hunters_used); + ut_asserteq(BIT(MMC_HUNTER) | BIT(SCSI_HUNTER) | BIT(0), std->hunters_used); return 0; } diff --git a/test/boot/bootflow.c b/test/boot/bootflow.c index 56ee1952357..1cc137c9700 100644 --- a/test/boot/bootflow.c +++ b/test/boot/bootflow.c @@ -19,6 +19,8 @@ #include <mapmem.h> #ifdef CONFIG_SANDBOX #include <asm/test.h> +#include <sandbox_host.h> +#include <os.h> #endif #include <dm/device-internal.h> #include <dm/lists.h> @@ -1532,3 +1534,48 @@ static int bootstd_images(struct unit_test_state *uts) return 0; } BOOTSTD_TEST(bootstd_images, UTF_CONSOLE); + +#if defined(CONFIG_SANDBOX) && defined(CONFIG_BOOTMETH_GLOBAL) +/* + * Check that bootdev scanning does not stop if higher-priority bootdevs + * are failed to be hunted. + */ +static int bootdev_hunt_fallthrough(struct unit_test_state *uts) +{ + struct bootstd_priv *std; + struct udevice *dev; + + ut_assertok(bootstd_get_priv(&std)); + bootstd_test_drop_bootdev_order(uts); + test_set_skip_delays(true); + bootstd_reset_usb(); + console_record_reset_enable(); + + /* + * Create a sandbox block device (BOOTDEVP_4_SCAN_FAST) and mark it as + * broken so that bootdev_hunt_prio() returns an error. + */ + ut_asserteq(0, uclass_id_count(UCLASS_HOST)); + ut_assertok(host_create_device("test", true, DEFAULT_BLKSZ, &dev)); + ut_assertok(host_set_flags_by_label("test", HOST_FLAG_BROKEN)); + ut_asserteq(1, uclass_id_count(UCLASS_HOST)); + + /* + * Scan with hunting. + * The sandbox hunter at priority 4 must fail, but the USB hunter at + * priority 5 must still be reached. + */ + ut_assertok(run_command("bootflow scan -l", 0)); + + ut_assert(!(std->hunters_used & BIT(HOST_HUNTER))); + ut_assert_skip_to_line("Hunting with: host"); + + /* USB was hunted despite the sandbox hunter failure */ + ut_assert(std->hunters_used & BIT(USB_HUNTER)); + ut_assert_skip_to_line("Bus usb@1: 5 USB Device(s) found"); + + return 0; +} +BOOTSTD_TEST(bootdev_hunt_fallthrough, + UTF_DM | UTF_SCAN_FDT | UTF_SF_BOOTDEV | UTF_CONSOLE); +#endif /* CONFIG_SANDBOX */ diff --git a/test/boot/bootstd_common.h b/test/boot/bootstd_common.h index dd769313a84..672917454a3 100644 --- a/test/boot/bootstd_common.h +++ b/test/boot/bootstd_common.h @@ -21,8 +21,11 @@ #define TEST_VERNUM 0x00010002 enum { - MAX_HUNTER = 8, MMC_HUNTER = 2, /* ID of MMC hunter */ + HOST_HUNTER = 5, + SCSI_HUNTER = 6, + USB_HUNTER = 8, + MAX_HUNTER = 9, }; struct unit_test_state; diff --git a/test/dm/Makefile b/test/dm/Makefile index d69b0e08d66..0e3c63568dd 100644 --- a/test/dm/Makefile +++ b/test/dm/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_MULTIPLEXER) += mux-emul.o obj-$(CONFIG_MUX_MMIO) += mux-mmio.o obj-y += fdtdec.o obj-$(CONFIG_MTD_RAW_NAND) += nand.o +obj-$(CONFIG_IP_DEFRAG) += net_defrag.o obj-$(CONFIG_UT_DM) += nop.o obj-y += ofnode.o obj-y += ofread.o diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 2de7983f9ae..293ea0274b5 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -136,7 +136,7 @@ static int testacpi_inject_dsdt(const struct udevice *dev, struct acpi_ctx *ctx) return 0; } -struct acpi_ops testacpi_ops = { +static const struct acpi_ops testacpi_ops = { .get_name = testacpi_get_name, .write_tables = testacpi_write_tables, .fill_madt = testacpi_fill_madt, diff --git a/test/dm/net_defrag.c b/test/dm/net_defrag.c new file mode 100644 index 00000000000..3fd40de90cd --- /dev/null +++ b/test/dm/net_defrag.c @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Regression test for IP fragment reassembly. + * + * The test drives the real RX path via net_process_received_packet(). Final IP + * fragment (MF=0) is duplicated, crafted payload triggers redelivery of the datagram, + * which fails the test for the unfixed code. + */ + +#include <net.h> +#include <string.h> +#include <test/ut.h> +#include <dm/test.h> + +#define FRAG_LEN (8) +#define PAYLOAD_OFFSET (ETHER_HDR_SIZE + IP_HDR_SIZE) +#define FRAME_LEN (PAYLOAD_OFFSET + FRAG_LEN) + +static int udp_rx_count; + +static void defrag_udp_handler(uchar *pkt, unsigned int dport, + struct in_addr sip, unsigned int sport, + unsigned int len) +{ + udp_rx_count++; +} + +static int build_frag(uchar *buf, u16 off_flags, const u16 *payload) +{ + struct ethernet_hdr *et = (struct ethernet_hdr *)buf; + struct ip_udp_hdr *ip = (struct ip_udp_hdr *)(buf + ETHER_HDR_SIZE); + + memset(buf, 0, FRAME_LEN); + et->et_protlen = htons(PROT_IP); + + ip->ip_hl_v = 0x45; + ip->ip_len = htons(IP_HDR_SIZE + FRAG_LEN); + ip->ip_id = htons(0x4321); + ip->ip_off = htons(off_flags); + ip->ip_ttl = 64; + ip->ip_p = IPPROTO_UDP; + /* Broadcast destination is accepted regardless of net_ip. */ + ip->ip_dst.s_addr = 0xffffffff; + ip->ip_sum = compute_ip_checksum(ip, IP_HDR_SIZE); + + memcpy(buf + PAYLOAD_OFFSET, payload, FRAG_LEN); + + return FRAME_LEN; +} + +static int dm_test_net_ip_defrag_dup_last(struct unit_test_state *uts) +{ + rxhand_f *saved_handler = net_get_udp_handler(); + uchar frame[FRAME_LEN]; + /* UDP header, carried by first fragment. */ + u16 udp_hdr[4] = { htons(5000), htons(5001), + htons(UDP_HDR_SIZE + FRAG_LEN), 0 }; + /* + * Second fragment's payload doubles as a fake hole + * {last_byte >= FRAG_LEN, next_hole = 0, prev_hole = 0}, so that the + * buggy code re-reading it on a duplicate re-delivers the datagram. + */ + u16 frag_b[4] = { 2 * FRAG_LEN, 0, 0, 0 }; + + udp_rx_count = 0; + net_set_udp_handler(defrag_udp_handler); + + /* UDP header, offset 0, MF=1; then data, offset 1, MF=0 */ + net_process_received_packet(frame, build_frag(frame, IP_FLAGS_MFRAG, udp_hdr)); + net_process_received_packet(frame, build_frag(frame, 1, frag_b)); + ut_asserteq(1, udp_rx_count); + + /* Duplicate the final fragment: UDP datagram must not be delivered again. */ + net_process_received_packet(frame, build_frag(frame, 1, frag_b)); + ut_asserteq(1, udp_rx_count); + + net_set_udp_handler(saved_handler); + + return 0; +} + +DM_TEST(dm_test_net_ip_defrag_dup_last, 0); @@ -80,7 +80,6 @@ export DTC=${DTC_DIR}/dtc TOOLS_DIR=build-sandbox_spl/tools run_test "binman" ./tools/binman/binman --toolpath ${TOOLS_DIR} test -run_test "patman" ./tools/patman/patman test run_test "u_boot_pylib" ./tools/u_boot_pylib/u_boot_pylib run_test "buildman" ./tools/buildman/buildman -t ${skip} diff --git a/tools/binman/etype/nxp_imx9image.py b/tools/binman/etype/nxp_imx9image.py index e0e806f2b7f..138563ba33a 100644 --- a/tools/binman/etype/nxp_imx9image.py +++ b/tools/binman/etype/nxp_imx9image.py @@ -36,7 +36,8 @@ class Entry_nxp_imx9image(Entry_mkimage): 'append', 'boot-from', 'cntr-version', 'container', 'dummy-ddr', 'dummy-v2x', 'hold', 'image', 'soc-type' ] - external_files = ['oei-m33-tcm.bin', 'm33_image.bin', 'bl31.bin'] + external_files = ['oei-m33-tcm.bin', 'm33_image.bin', 'bl31.bin', + 'tee.bin'] with open(self.config_filename, 'w', encoding='utf-8') as f: for prop in self._node.props.values(): diff --git a/tools/binman/pyproject.toml b/tools/binman/pyproject.toml index 2f17588e9df..fd43a71b02b 100644 --- a/tools/binman/pyproject.toml +++ b/tools/binman/pyproject.toml @@ -26,4 +26,4 @@ classifiers = [ binman = "binman.main:start_binman" [tool.setuptools.package-data] -patman = ["*.rst"] +binman = ["*.rst"] diff --git a/tools/docker/Dockerfile b/tools/docker/Dockerfile index 73bf6cdd2c5..a91a1060cc4 100644 --- a/tools/docker/Dockerfile +++ b/tools/docker/Dockerfile @@ -362,7 +362,6 @@ RUN wget -O /tmp/pytest-requirements.txt https://source.denx.de/u-boot/u-boot/-/ RUN wget -O /tmp/sphinx-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/doc/sphinx/requirements.txt RUN wget -O /tmp/binman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/binman/requirements.txt RUN wget -O /tmp/buildman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/buildman/requirements.txt -RUN wget -O /tmp/patman-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/patman/requirements.txt RUN wget -O /tmp/u_boot_pylib-requirements.txt https://source.denx.de/u-boot/u-boot/-/raw/master/tools/u_boot_pylib/requirements.txt RUN python3 -m venv /tmp/venv && \ . /tmp/venv/bin/activate && \ @@ -370,7 +369,6 @@ RUN python3 -m venv /tmp/venv && \ -r /tmp/sphinx-requirements.txt \ -r /tmp/binman-requirements.txt \ -r /tmp/buildman-requirements.txt \ - -r /tmp/patman-requirements.txt \ -r /tmp/u_boot_pylib-requirements.txt \ setuptools pytest-azurepipelines && \ deactivate && \ diff --git a/tools/patman/README.rst b/tools/patman/README.rst deleted file mode 120000 index 76368b95980..00000000000 --- a/tools/patman/README.rst +++ /dev/null @@ -1 +0,0 @@ -patman.rst
\ No newline at end of file diff --git a/tools/patman/__init__.py b/tools/patman/__init__.py index 0cca6f42435..bfe0f1fe946 100644 --- a/tools/patman/__init__.py +++ b/tools/patman/__init__.py @@ -1,8 +1,5 @@ # SPDX-License-Identifier: GPL-2.0+ __all__ = [ - 'checkpatch', 'cmdline', 'commit', 'control', 'cser_helper', 'cseries', - 'database', 'func_test', 'get_maintainer', '__main__', 'patchstream', - 'patchwork', 'project', 'send', 'series', 'settings', 'setup', 'status', - 'test_checkpatch', 'test_common', 'test_cseries', 'test_settings' + 'commit', 'get_maintainer', 'patchstream', 'series', 'settings', ] diff --git a/tools/patman/__main__.py b/tools/patman/__main__.py index edfb1b5927c..a497f6ced7e 100755 --- a/tools/patman/__main__.py +++ b/tools/patman/__main__.py @@ -4,56 +4,30 @@ # Copyright (c) 2011 The Chromium OS Authors. # -"""See README for more information""" +"""Stub for the former in-tree patman tool -import os -import sys - -# Allow 'from patman import xxx to work' -# pylint: disable=C0413 -our_path = os.path.dirname(os.path.realpath(__file__)) -sys.path.append(os.path.join(our_path, '..')) - -# Our modules -from u_boot_pylib import test_util -from u_boot_pylib import tout -from patman import cmdline -from patman import control - - -def run_patman(): - """Run patamn +patman is now maintained as a standalone 'patch-manager' package, rather +than living in the U-Boot tree. This stub just tells the user how to get +it. +""" - This is the main program. It collects arguments and runs either the tests or - the control module. - """ - args = cmdline.parse_args() - - if not args.debug: - sys.tracebacklimit = 0 - - tout.init(tout.INFO if args.verbose else tout.WARNING) - - # Run our reasonably good tests - if args.cmd == 'test': - # pylint: disable=C0415 - from patman import func_test - from patman import test_checkpatch - from patman import test_cseries +import sys - to_run = args.testname if args.testname not in [None, 'test'] else None - result = test_util.run_test_suites( - 'patman', False, args.verbose, args.no_capture, - args.test_preserve_dirs, None, to_run, None, - [test_checkpatch.TestPatch, func_test.TestFunctional, 'settings', - test_cseries.TestCseries]) - sys.exit(0 if result.wasSuccessful() else 1) - # Process commits, produce patches files, check them, email them - else: - exit_code = control.do_patman(args) - sys.exit(exit_code) +def main(): + """Print instructions for installing the patch-manager package""" + print( + 'patman is no longer part of U-Boot. It is now maintained as a\n' + "separate package called 'patch-manager'.\n" + '\n' + 'Install it with:\n' + '\n' + ' pip install patch-manager\n' + '\n' + 'Documentation: https://deinde.dev/patman\n', + file=sys.stderr) + return 1 -if __name__ == "__main__": - sys.exit(run_patman()) +if __name__ == '__main__': + sys.exit(main()) diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py deleted file mode 100644 index f9204a907ef..00000000000 --- a/tools/patman/checkpatch.py +++ /dev/null @@ -1,287 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# Copyright (c) 2011 The Chromium OS Authors. -# - -import collections -import concurrent.futures -import os -import re -import sys - -from u_boot_pylib import command -from u_boot_pylib import gitutil -from u_boot_pylib import terminal - -EMACS_PREFIX = r'(?:[0-9]{4}.*\.patch:[0-9]+: )?' -TYPE_NAME = r'([A-Z_]+:)?' -RE_ERROR = re.compile(r'ERROR:%s (.*)' % TYPE_NAME) -RE_WARNING = re.compile(EMACS_PREFIX + r'WARNING:%s (.*)' % TYPE_NAME) -RE_CHECK = re.compile(r'CHECK:%s (.*)' % TYPE_NAME) -RE_FILE = re.compile(r'#(\d+): (FILE: ([^:]*):(\d+):)?') -RE_NOTE = re.compile(r'NOTE: (.*)') - - -def find_check_patch(): - top_level = gitutil.get_top_level() or '' - try_list = [ - os.getcwd(), - os.path.join(os.getcwd(), '..', '..'), - os.path.join(top_level, 'tools'), - os.path.join(top_level, 'scripts'), - '%s/bin' % os.getenv('HOME'), - ] - # Look in current dir - for path in try_list: - fname = os.path.join(path, 'checkpatch.pl') - if os.path.isfile(fname): - return fname - - # Look upwwards for a Chrome OS tree - while not os.path.ismount(path): - fname = os.path.join(path, 'src', 'third_party', 'kernel', 'files', - 'scripts', 'checkpatch.pl') - if os.path.isfile(fname): - return fname - path = os.path.dirname(path) - - sys.exit('Cannot find checkpatch.pl - please put it in your ' + - '~/bin directory or use --no-check') - - -def check_patch_parse_one_message(message): - """Parse one checkpatch message - - Args: - message: string to parse - - Returns: - dict: - 'type'; error or warning - 'msg': text message - 'file' : filename - 'line': line number - """ - - if RE_NOTE.match(message): - return {} - - item = {} - - err_match = RE_ERROR.match(message) - warn_match = RE_WARNING.match(message) - check_match = RE_CHECK.match(message) - if err_match: - item['cptype'] = err_match.group(1) - item['msg'] = err_match.group(2) - item['type'] = 'error' - elif warn_match: - item['cptype'] = warn_match.group(1) - item['msg'] = warn_match.group(2) - item['type'] = 'warning' - elif check_match: - item['cptype'] = check_match.group(1) - item['msg'] = check_match.group(2) - item['type'] = 'check' - else: - message_indent = ' ' - print('patman: failed to parse checkpatch message:\n%s' % - (message_indent + message.replace('\n', '\n' + message_indent)), - file=sys.stderr) - return {} - - file_match = RE_FILE.search(message) - # some messages have no file, catch those here - no_file_match = any(s in message for s in [ - '\nSubject:', 'Missing Signed-off-by: line(s)', - 'does MAINTAINERS need updating' - ]) - - if file_match: - err_fname = file_match.group(3) - if err_fname: - item['file'] = err_fname - item['line'] = int(file_match.group(4)) - else: - item['file'] = '<patch>' - item['line'] = int(file_match.group(1)) - elif no_file_match: - item['file'] = '<patch>' - else: - message_indent = ' ' - print('patman: failed to find file / line information:\n%s' % - (message_indent + message.replace('\n', '\n' + message_indent)), - file=sys.stderr) - - return item - - -def check_patch_parse(checkpatch_output, verbose=False): - """Parse checkpatch.pl output - - Args: - checkpatch_output: string to parse - verbose: True to print out every line of the checkpatch output as it is - parsed - - Returns: - namedtuple containing: - ok: False=failure, True=ok - problems (list of problems): each a dict: - 'type'; error or warning - 'msg': text message - 'file' : filename - 'line': line number - errors: Number of errors - warnings: Number of warnings - checks: Number of checks - lines: Number of lines - stdout: checkpatch_output - """ - fields = ['ok', 'problems', 'errors', 'warnings', 'checks', 'lines', - 'stdout'] - result = collections.namedtuple('CheckPatchResult', fields) - result.stdout = checkpatch_output - result.ok = False - result.errors, result.warnings, result.checks = 0, 0, 0 - result.lines = 0 - result.problems = [] - - # total: 0 errors, 0 warnings, 159 lines checked - # or: - # total: 0 errors, 2 warnings, 7 checks, 473 lines checked - emacs_stats = r'(?:[0-9]{4}.*\.patch )?' - re_stats = re.compile(emacs_stats + - r'total: (\d+) errors, (\d+) warnings, (\d+)') - re_stats_full = re.compile(emacs_stats + - r'total: (\d+) errors, (\d+) warnings, (\d+)' - r' checks, (\d+)') - re_ok = re.compile(r'.*has no obvious style problems') - re_bad = re.compile(r'.*has style problems, please review') - - # A blank line indicates the end of a message - for message in result.stdout.split('\n\n'): - if verbose: - print(message) - - # either find stats, the verdict, or delegate - match = re_stats_full.match(message) - if not match: - match = re_stats.match(message) - if match: - result.errors = int(match.group(1)) - result.warnings = int(match.group(2)) - if len(match.groups()) == 4: - result.checks = int(match.group(3)) - result.lines = int(match.group(4)) - else: - result.lines = int(match.group(3)) - elif re_ok.match(message): - result.ok = True - elif re_bad.match(message): - result.ok = False - else: - problem = check_patch_parse_one_message(message) - if problem: - result.problems.append(problem) - - return result - - -def check_patch(fname, verbose=False, show_types=False, use_tree=False, - cwd=None): - """Run checkpatch.pl on a file and parse the results. - - Args: - fname: Filename to check - verbose: True to print out every line of the checkpatch output as it is - parsed - show_types: Tell checkpatch to show the type (number) of each message - use_tree (bool): If False we'll pass '--no-tree' to checkpatch. - cwd (str): Path to use for patch files (None to use current dir) - - Returns: - namedtuple containing: - ok: False=failure, True=ok - problems: List of problems, each a dict: - 'type'; error or warning - 'msg': text message - 'file' : filename - 'line': line number - errors: Number of errors - warnings: Number of warnings - checks: Number of checks - lines: Number of lines - stdout: Full output of checkpatch - """ - chk = find_check_patch() - args = [chk] - if not use_tree: - args.append('--no-tree') - if show_types: - args.append('--show-types') - output = command.output( - *args, os.path.join(cwd or '', fname), raise_on_error=False, - capture_stderr=not use_tree) - - return check_patch_parse(output, verbose) - - -def get_warning_msg(col, msg_type, fname, line, msg): - '''Create a message for a given file/line - - Args: - msg_type: Message type ('error' or 'warning') - fname: Filename which reports the problem - line: Line number where it was noticed - msg: Message to report - ''' - if msg_type == 'warning': - msg_type = col.build(col.YELLOW, msg_type) - elif msg_type == 'error': - msg_type = col.build(col.RED, msg_type) - elif msg_type == 'check': - msg_type = col.build(col.MAGENTA, msg_type) - line_str = '' if line is None else '%d' % line - return '%s:%s: %s: %s\n' % (fname, line_str, msg_type, msg) - -def check_patches(verbose, args, use_tree, cwd): - '''Run the checkpatch.pl script on each patch''' - error_count, warning_count, check_count = 0, 0, 0 - col = terminal.Color() - - with concurrent.futures.ThreadPoolExecutor(max_workers=16) as executor: - futures = [] - for fname in args: - f = executor.submit(check_patch, fname, verbose, use_tree=use_tree, - cwd=cwd) - futures.append(f) - - for fname, f in zip(args, futures): - result = f.result() - if not result.ok: - error_count += result.errors - warning_count += result.warnings - check_count += result.checks - print('%d errors, %d warnings, %d checks for %s:' % (result.errors, - result.warnings, result.checks, col.build(col.BLUE, fname))) - if (len(result.problems) != result.errors + result.warnings + - result.checks): - print("Internal error: some problems lost") - # Python seems to get confused by this - # pylint: disable=E1133 - for item in result.problems: - sys.stderr.write( - get_warning_msg(col, item.get('type', '<unknown>'), - item.get('file', '<unknown>'), - item.get('line', 0), item.get('msg', 'message'))) - print - if error_count or warning_count or check_count: - str = 'checkpatch.pl found %d error(s), %d warning(s), %d checks(s)' - color = col.GREEN - if warning_count: - color = col.YELLOW - if error_count: - color = col.RED - print(col.build(color, str % (error_count, warning_count, check_count))) - return False - return True diff --git a/tools/patman/cmdline.py b/tools/patman/cmdline.py deleted file mode 100644 index 924f0ad4e42..00000000000 --- a/tools/patman/cmdline.py +++ /dev/null @@ -1,516 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2023 Google LLC -# - -"""Handles parsing of buildman arguments - -This creates the argument parser and uses it to parse the arguments passed in -""" - -import argparse -import os -import pathlib -import sys - -from u_boot_pylib import gitutil -from patman import project -from patman import settings - -PATMAN_DIR = pathlib.Path(__file__).parent -HAS_TESTS = os.path.exists(PATMAN_DIR / "func_test.py") - -# Aliases for subcommands -ALIASES = { - 'series': ['s', 'ser'], - 'status': ['st'], - 'patchwork': ['pw'], - 'upstream': ['us'], - - # Series aliases - 'archive': ['ar'], - 'autolink': ['au'], - 'gather': ['g'], - 'open': ['o'], - 'progress': ['p', 'pr', 'prog'], - 'rm-version': ['rmv'], - 'unarchive': ['unar'], - } - - -class ErrorCatchingArgumentParser(argparse.ArgumentParser): - def __init__(self, **kwargs): - self.exit_state = None - self.catch_error = False - super().__init__(**kwargs) - - def error(self, message): - if self.catch_error: - self.message = message - else: - super().error(message) - - def exit(self, status=0, message=None): - if self.catch_error: - self.exit_state = True - else: - super().exit(status, message) - - -def add_send_args(par): - """Add arguments for the 'send' command - - Arguments: - par (ArgumentParser): Parser to add to - """ - par.add_argument( - '-c', '--count', dest='count', type=int, default=-1, - help='Automatically create patches from top n commits') - par.add_argument( - '-e', '--end', type=int, default=0, - help='Commits to skip at end of patch list') - par.add_argument( - '-i', '--ignore-errors', action='store_true', - dest='ignore_errors', default=False, - help='Send patches email even if patch errors are found') - par.add_argument( - '-l', '--limit-cc', dest='limit', type=int, default=None, - help='Limit the cc list to LIMIT entries [default: %(default)s]') - par.add_argument( - '-m', '--no-maintainers', action='store_false', - dest='add_maintainers', default=True, - help="Don't cc the file maintainers automatically") - default_arg = None - top_level = gitutil.get_top_level() - if top_level: - default_arg = os.path.join(top_level, 'scripts', - 'get_maintainer.pl') + ' --norolestats' - par.add_argument( - '--get-maintainer-script', dest='get_maintainer_script', type=str, - action='store', - default=default_arg, - help='File name of the get_maintainer.pl (or compatible) script.') - par.add_argument( - '-r', '--in-reply-to', type=str, action='store', - help="Message ID that this series is in reply to") - par.add_argument( - '-s', '--start', dest='start', type=int, default=0, - help='Commit to start creating patches from (0 = HEAD)') - par.add_argument( - '-t', '--ignore-bad-tags', action='store_true', default=False, - help='Ignore bad tags / aliases (default=warn)') - par.add_argument( - '--no-binary', action='store_true', dest='ignore_binary', - default=False, - help="Do not output contents of changes in binary files") - par.add_argument( - '--no-check', action='store_false', dest='check_patch', default=True, - help="Don't check for patch compliance") - par.add_argument( - '--tree', dest='check_patch_use_tree', default=False, - action='store_true', - help=("Set `tree` to True. If `tree` is False then we'll pass " - "'--no-tree' to checkpatch (default: tree=%(default)s)")) - par.add_argument( - '--no-tree', dest='check_patch_use_tree', action='store_false', - help="Set `tree` to False") - par.add_argument( - '--no-tags', action='store_false', dest='process_tags', default=True, - help="Don't process subject tags as aliases") - par.add_argument( - '--no-signoff', action='store_false', dest='add_signoff', - default=True, help="Don't add Signed-off-by to patches") - par.add_argument( - '--smtp-server', type=str, - help="Specify the SMTP server to 'git send-email'") - par.add_argument( - '--keep-change-id', action='store_true', - help='Preserve Change-Id tags in patches to send.') - - -def _add_show_comments(parser): - parser.add_argument('-c', '--show-comments', action='store_true', - help='Show comments from each patch') - - -def _add_show_cover_comments(parser): - parser.add_argument('-C', '--show-cover-comments', action='store_true', - help='Show comments from the cover letter') - - -def add_patchwork_subparser(subparsers): - """Add the 'patchwork' subparser - - Args: - subparsers (argparse action): Subparser parent - - Return: - ArgumentParser: patchwork subparser - """ - patchwork = subparsers.add_parser( - 'patchwork', aliases=ALIASES['patchwork'], - help='Manage patchwork connection') - patchwork.defaults_cmds = [ - ['set-project', 'U-Boot'], - ] - patchwork_subparsers = patchwork.add_subparsers(dest='subcmd') - patchwork_subparsers.add_parser('get-project') - uset = patchwork_subparsers.add_parser('set-project') - uset.add_argument( - 'project_name', help="Patchwork project name, e.g. 'U-Boot'") - return patchwork - - -def add_series_subparser(subparsers): - """Add the 'series' subparser - - Args: - subparsers (argparse action): Subparser parent - - Return: - ArgumentParser: series subparser - """ - def _add_allow_unmarked(parser): - parser.add_argument('-M', '--allow-unmarked', action='store_true', - default=False, - help="Don't require commits to be marked") - - def _add_mark(parser): - parser.add_argument( - '-m', '--mark', action='store_true', - help='Mark unmarked commits with a Change-Id field') - - def _add_update(parser): - parser.add_argument('-u', '--update', action='store_true', - help='Update the branch commit') - - def _add_wait(parser, default_s): - """Add a -w option to a parser - - Args: - parser (ArgumentParser): Parser to adjust - default_s (int): Default value to use, in seconds - """ - parser.add_argument( - '-w', '--autolink-wait', type=int, default=default_s, - help='Seconds to wait for patchwork to get a sent series') - - def _upstream_add(parser): - parser.add_argument('-U', '--upstream', help='Commit to end before') - - def _add_gather(parser): - parser.add_argument( - '-G', '--no-gather-tags', dest='gather_tags', default=True, - action='store_false', - help="Don't gather review/test tags / update local series") - - series = subparsers.add_parser('series', aliases=ALIASES['series'], - help='Manage series of patches') - series.defaults_cmds = [ - ['set-link', 'fred'], - ] - series.add_argument( - '-n', '--dry-run', action='store_true', dest='dry_run', default=False, - help="Do a dry run (create but don't email patches)") - series.add_argument('-s', '--series', help='Name of series') - series.add_argument('-V', '--version', type=int, - help='Version number to link') - series_subparsers = series.add_subparsers(dest='subcmd') - - # This causes problem at present, perhaps due to the 'defaults' handling in - # settings - # series_subparsers.required = True - - add = series_subparsers.add_parser('add') - add.add_argument('-D', '--desc', - help='Series description / cover-letter title') - add.add_argument( - '-f', '--force-version', action='store_true', - help='Change the Series-version on a series to match its branch') - _add_mark(add) - _add_allow_unmarked(add) - _upstream_add(add) - - series_subparsers.add_parser('archive', aliases=ALIASES['archive']) - - auto = series_subparsers.add_parser('autolink', - aliases=ALIASES['autolink']) - _add_update(auto) - _add_wait(auto, 0) - - aall = series_subparsers.add_parser('autolink-all') - aall.add_argument('-a', '--link-all-versions', action='store_true', - help='Link all series versions, not just the latest') - aall.add_argument('-r', '--replace-existing', action='store_true', - help='Replace existing links') - _add_update(aall) - - series_subparsers.add_parser('dec') - - gat = series_subparsers.add_parser('gather', aliases=ALIASES['gather']) - _add_gather(gat) - _add_show_comments(gat) - _add_show_cover_comments(gat) - - sall = series_subparsers.add_parser('gather-all') - sall.add_argument( - '-a', '--gather-all-versions', action='store_true', - help='Gather tags from all series versions, not just the latest') - _add_gather(sall) - _add_show_comments(sall) - _add_show_cover_comments(sall) - - series_subparsers.add_parser('get-link') - series_subparsers.add_parser('inc') - series_subparsers.add_parser('ls') - - mar = series_subparsers.add_parser('mark') - mar.add_argument('-m', '--allow-marked', action='store_true', - default=False, - help="Don't require commits to be unmarked") - - series_subparsers.add_parser('open', aliases=ALIASES['open']) - pat = series_subparsers.add_parser( - 'patches', epilog='Show a list of patches and optional details') - pat.add_argument('-t', '--commit', action='store_true', - help='Show the commit and diffstat') - pat.add_argument('-p', '--patch', action='store_true', - help='Show the patch body') - - prog = series_subparsers.add_parser('progress', - aliases=ALIASES['progress']) - prog.add_argument('-a', '--show-all-versions', action='store_true', - help='Show all series versions, not just the latest') - prog.add_argument('-l', '--list-patches', action='store_true', - help='List patch subject and status') - - ren = series_subparsers.add_parser('rename') - ren.add_argument('-N', '--new-name', help='New name for the series') - - series_subparsers.add_parser('rm') - series_subparsers.add_parser('rm-version', aliases=ALIASES['rm-version']) - - scan = series_subparsers.add_parser('scan') - _add_mark(scan) - _add_allow_unmarked(scan) - _upstream_add(scan) - - ssend = series_subparsers.add_parser('send') - add_send_args(ssend) - ssend.add_argument( - '--no-autolink', action='store_false', default=True, dest='autolink', - help='Monitor patchwork after sending so the series can be autolinked') - _add_wait(ssend, 120) - - setl = series_subparsers.add_parser('set-link') - _add_update(setl) - - setl.add_argument( - 'link', help='Link to use, i.e. patchwork series number (e.g. 452329)') - stat = series_subparsers.add_parser('status', aliases=ALIASES['status']) - _add_show_comments(stat) - _add_show_cover_comments(stat) - - series_subparsers.add_parser('summary') - - series_subparsers.add_parser('unarchive', aliases=ALIASES['unarchive']) - - unm = series_subparsers.add_parser('unmark') - _add_allow_unmarked(unm) - - ver = series_subparsers.add_parser( - 'version-change', help='Change a version to a different version') - ver.add_argument('--new-version', type=int, - help='New version number to change this one too') - - return series - - -def add_send_subparser(subparsers): - """Add the 'send' subparser - - Args: - subparsers (argparse action): Subparser parent - - Return: - ArgumentParser: send subparser - """ - send = subparsers.add_parser( - 'send', help='Format, check and email patches (default command)') - send.add_argument( - '-b', '--branch', type=str, - help="Branch to process (by default, the current branch)") - send.add_argument( - '-n', '--dry-run', action='store_true', dest='dry_run', - default=False, help="Do a dry run (create but don't email patches)") - send.add_argument( - '--cc-cmd', dest='cc_cmd', type=str, action='store', - default=None, help='Output cc list for patch file (used by git)') - add_send_args(send) - send.add_argument('patchfiles', nargs='*') - return send - - -def add_status_subparser(subparsers): - """Add the 'status' subparser - - Args: - subparsers (argparse action): Subparser parent - - Return: - ArgumentParser: status subparser - """ - status = subparsers.add_parser('status', aliases=ALIASES['status'], - help='Check status of patches in patchwork') - _add_show_comments(status) - status.add_argument( - '-d', '--dest-branch', type=str, - help='Name of branch to create with collected responses') - status.add_argument('-f', '--force', action='store_true', - help='Force overwriting an existing branch') - status.add_argument('-T', '--single-thread', action='store_true', - help='Disable multithreading when reading patchwork') - return status - - -def add_upstream_subparser(subparsers): - """Add the 'status' subparser - - Args: - subparsers (argparse action): Subparser parent - - Return: - ArgumentParser: status subparser - """ - upstream = subparsers.add_parser('upstream', aliases=ALIASES['upstream'], - help='Manage upstream destinations') - upstream.defaults_cmds = [ - ['add', 'us', 'http://fred'], - ['delete', 'us'], - ] - upstream_subparsers = upstream.add_subparsers(dest='subcmd') - uadd = upstream_subparsers.add_parser('add') - uadd.add_argument('remote_name', - help="Git remote name used for this upstream, e.g. 'us'") - uadd.add_argument( - 'url', help='URL to use for this upstream, e.g. ' - "'https://gitlab.denx.de/u-boot/u-boot.git'") - udel = upstream_subparsers.add_parser('delete') - udel.add_argument( - 'remote_name', - help="Git remote name used for this upstream, e.g. 'us'") - upstream_subparsers.add_parser('list') - udef = upstream_subparsers.add_parser('default') - udef.add_argument('-u', '--unset', action='store_true', - help='Unset the default upstream') - udef.add_argument('remote_name', nargs='?', - help="Git remote name used for this upstream, e.g. 'us'") - return upstream - - -def setup_parser(): - """Set up command-line parser - - Returns: - argparse.Parser object - """ - epilog = '''Create patches from commits in a branch, check them and email - them as specified by tags you place in the commits. Use -n to do a dry - run first.''' - - parser = ErrorCatchingArgumentParser(epilog=epilog) - parser.add_argument( - '-D', '--debug', action='store_true', - help='Enabling debugging (provides a full traceback on error)') - parser.add_argument( - '-N', '--no-capture', action='store_true', - help='Disable capturing of console output in tests') - parser.add_argument('-p', '--project', default=project.detect_project(), - help="Project name; affects default option values and " - "aliases [default: %(default)s]") - parser.add_argument('-P', '--patchwork-url', - default='https://patchwork.ozlabs.org', - help='URL of patchwork server [default: %(default)s]') - parser.add_argument( - '-T', '--thread', action='store_true', dest='thread', - default=False, help='Create patches as a single thread') - parser.add_argument( - '-v', '--verbose', action='store_true', dest='verbose', default=False, - help='Verbose output of errors and warnings') - parser.add_argument( - '-X', '--test-preserve-dirs', action='store_true', - help='Preserve and display test-created directories') - parser.add_argument( - '-H', '--full-help', action='store_true', dest='full_help', - default=False, help='Display the README file') - - subparsers = parser.add_subparsers(dest='cmd') - add_send_subparser(subparsers) - patchwork = add_patchwork_subparser(subparsers) - series = add_series_subparser(subparsers) - add_status_subparser(subparsers) - upstream = add_upstream_subparser(subparsers) - - # Only add the 'test' action if the test data files are available. - if HAS_TESTS: - test_parser = subparsers.add_parser('test', help='Run tests') - test_parser.add_argument('testname', type=str, default=None, nargs='?', - help="Specify the test to run") - - parsers = { - 'main': parser, - 'series': series, - 'patchwork': patchwork, - 'upstream': upstream, - } - return parsers - - -def parse_args(argv=None, config_fname=None, parsers=None): - """Parse command line arguments from sys.argv[] - - Args: - argv (str or None): Arguments to process, or None to use sys.argv[1:] - config_fname (str): Config file to read, or None for default, or False - for an empty config - - Returns: - tuple containing: - options: command line options - args: command lin arguments - """ - if not parsers: - parsers = setup_parser() - parser = parsers['main'] - - # Parse options twice: first to get the project and second to handle - # defaults properly (which depends on project) - # Use parse_known_args() in case 'cmd' is omitted - if not argv: - argv = sys.argv[1:] - - args, rest = parser.parse_known_args(argv) - if hasattr(args, 'project'): - settings.Setup(parser, args.project, argv, config_fname) - args, rest = parser.parse_known_args(argv) - - # If we have a command, it is safe to parse all arguments - if args.cmd: - args = parser.parse_args(argv) - elif not args.full_help: - # No command, so insert it after the known arguments and before the ones - # that presumably relate to the 'send' subcommand - nargs = len(rest) - argv = argv[:-nargs] + ['send'] + rest - args = parser.parse_args(argv) - - # Resolve aliases - for full, aliases in ALIASES.items(): - if args.cmd in aliases: - args.cmd = full - if 'subcmd' in args and args.subcmd in aliases: - args.subcmd = full - if args.cmd in ['series', 'upstream', 'patchwork'] and not args.subcmd: - parser.parse_args([args.cmd, '--help']) - - return args diff --git a/tools/patman/control.py b/tools/patman/control.py deleted file mode 100644 index 3e09b16e87b..00000000000 --- a/tools/patman/control.py +++ /dev/null @@ -1,333 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2020 Google LLC -# -"""Handles the main control logic of patman - -This module provides various functions called by the main program to implement -the features of patman. -""" - -import re -import traceback - -try: - from importlib import resources -except ImportError: - # for Python 3.6 - import importlib_resources as resources - -from u_boot_pylib import gitutil -from u_boot_pylib import terminal -from u_boot_pylib import tools -from u_boot_pylib import tout -from patman import cseries -from patman import cser_helper -from patman import patchstream -from patman.patchwork import Patchwork -from patman import send -from patman import settings - - -def setup(): - """Do required setup before doing anything""" - gitutil.setup() - alias_fname = gitutil.get_alias_file() - if alias_fname: - settings.ReadGitAliases(alias_fname) - - -def do_send(args): - """Create, check and send patches by email - - Args: - args (argparse.Namespace): Arguments to patman - """ - setup() - send.send(args) - - -def patchwork_status(branch, count, start, end, dest_branch, force, - show_comments, url, single_thread=False): - """Check the status of patches in patchwork - - This finds the series in patchwork using the Series-link tag, checks for new - comments and review tags, displays then and creates a new branch with the - review tags. - - Args: - branch (str): Branch to create patches from (None = current) - count (int): Number of patches to produce, or -1 to produce patches for - the current branch back to the upstream commit - start (int): Start partch to use (0=first / top of branch) - end (int): End patch to use (0=last one in series, 1=one before that, - etc.) - dest_branch (str): Name of new branch to create with the updated tags - (None to not create a branch) - force (bool): With dest_branch, force overwriting an existing branch - show_comments (bool): True to display snippets from the comments - provided by reviewers - url (str): URL of patchwork server, e.g. 'https://patchwork.ozlabs.org'. - This is ignored if the series provides a Series-patchwork-url tag. - - Raises: - ValueError: if the branch has no Series-link value - """ - if not branch: - branch = gitutil.get_branch() - if count == -1: - # Work out how many patches to send if we can - count = gitutil.count_commits_to_branch(branch) - start - - series = patchstream.get_metadata(branch, start, count - end) - warnings = 0 - for cmt in series.commits: - if cmt.warn: - print('%d warnings for %s:' % (len(cmt.warn), cmt.hash)) - for warn in cmt.warn: - print('\t', warn) - warnings += 1 - print - if warnings: - raise ValueError('Please fix warnings before running status') - links = series.get('links') - if not links: - raise ValueError("Branch has no Series-links value") - - _, version = cser_helper.split_name_version(branch) - link = series.get_link_for_version(version, links) - if not link: - raise ValueError('Series-links has no link for v{version}') - tout.debug(f"Link '{link}") - - # Allow the series to override the URL - if 'patchwork_url' in series: - url = series.patchwork_url - pwork = Patchwork(url, single_thread=single_thread) - - # Import this here to avoid failing on other commands if the dependencies - # are not present - from patman import status - pwork = Patchwork(url) - status.check_and_show_status(series, link, branch, dest_branch, force, - show_comments, False, pwork) - - -def do_series(args, test_db=None, pwork=None, cser=None): - """Process a series subcommand - - Args: - args (Namespace): Arguments to process - test_db (str or None): Directory containing the test database, None to - use the normal one - pwork (Patchwork): Patchwork object to use, None to create one if - needed - cser (Cseries): Cseries object to use, None to create one - """ - if not cser: - cser = cseries.Cseries(test_db) - needs_patchwork = [ - 'autolink', 'autolink-all', 'open', 'send', 'status', 'gather', - 'gather-all' - ] - try: - cser.open_database() - if args.subcmd in needs_patchwork: - if not pwork: - pwork = Patchwork(args.patchwork_url) - proj = cser.project_get() - if not proj: - raise ValueError( - "Please set project ID with 'patman patchwork set-project'") - _, proj_id, link_name = cser.project_get() - pwork.project_set(proj_id, link_name) - elif pwork and pwork is not True: - raise ValueError( - f"Internal error: command '{args.subcmd}' should not have patchwork") - if args.subcmd == 'add': - cser.add(args.series, args.desc, mark=args.mark, - allow_unmarked=args.allow_unmarked, end=args.upstream, - dry_run=args.dry_run) - elif args.subcmd == 'archive': - cser.archive(args.series) - elif args.subcmd == 'autolink': - cser.link_auto(pwork, args.series, args.version, args.update, - args.autolink_wait) - elif args.subcmd == 'autolink-all': - cser.link_auto_all(pwork, update_commit=args.update, - link_all_versions=args.link_all_versions, - replace_existing=args.replace_existing, - dry_run=args.dry_run, show_summary=True) - elif args.subcmd == 'dec': - cser.decrement(args.series, args.dry_run) - elif args.subcmd == 'gather': - cser.gather(pwork, args.series, args.version, args.show_comments, - args.show_cover_comments, args.gather_tags, - dry_run=args.dry_run) - elif args.subcmd == 'gather-all': - cser.gather_all( - pwork, args.show_comments, args.show_cover_comments, - args.gather_all_versions, args.gather_tags, args.dry_run) - elif args.subcmd == 'get-link': - link = cser.link_get(args.series, args.version) - print(link) - elif args.subcmd == 'inc': - cser.increment(args.series, args.dry_run) - elif args.subcmd == 'ls': - cser.series_list() - elif args.subcmd == 'open': - cser.open(pwork, args.series, args.version) - elif args.subcmd == 'mark': - cser.mark(args.series, args.allow_marked, dry_run=args.dry_run) - elif args.subcmd == 'patches': - cser.list_patches(args.series, args.version, args.commit, - args.patch) - elif args.subcmd == 'progress': - cser.progress(args.series, args.show_all_versions, - args.list_patches) - elif args.subcmd == 'rm': - cser.remove(args.series, dry_run=args.dry_run) - elif args.subcmd == 'rm-version': - cser.version_remove(args.series, args.version, dry_run=args.dry_run) - elif args.subcmd == 'rename': - cser.rename(args.series, args.new_name, dry_run=args.dry_run) - elif args.subcmd == 'scan': - cser.scan(args.series, mark=args.mark, - allow_unmarked=args.allow_unmarked, end=args.upstream, - dry_run=args.dry_run) - elif args.subcmd == 'send': - cser.send(pwork, args.series, args.autolink, args.autolink_wait, - args) - elif args.subcmd == 'set-link': - cser.link_set(args.series, args.version, args.link, args.update) - elif args.subcmd == 'status': - cser.status(pwork, args.series, args.version, args.show_comments, - args.show_cover_comments) - elif args.subcmd == 'summary': - cser.summary(args.series) - elif args.subcmd == 'unarchive': - cser.unarchive(args.series) - elif args.subcmd == 'unmark': - cser.unmark(args.series, args.allow_unmarked, dry_run=args.dry_run) - elif args.subcmd == 'version-change': - cser.version_change(args.series, args.version, args.new_version, - dry_run=args.dry_run) - else: - raise ValueError(f"Unknown series subcommand '{args.subcmd}'") - finally: - cser.close_database() - - -def upstream(args, test_db=None): - """Process an 'upstream' subcommand - - Args: - args (Namespace): Arguments to process - test_db (str or None): Directory containing the test database, None to - use the normal one - """ - cser = cseries.Cseries(test_db) - try: - cser.open_database() - if args.subcmd == 'add': - cser.upstream_add(args.remote_name, args.url) - elif args.subcmd == 'default': - if args.unset: - cser.upstream_set_default(None) - elif args.remote_name: - cser.upstream_set_default(args.remote_name) - else: - result = cser.upstream_get_default() - print(result if result else 'unset') - elif args.subcmd == 'delete': - cser.upstream_delete(args.remote_name) - elif args.subcmd == 'list': - cser.upstream_list() - else: - raise ValueError(f"Unknown upstream subcommand '{args.subcmd}'") - finally: - cser.close_database() - - -def patchwork(args, test_db=None, pwork=None): - """Process a 'patchwork' subcommand - Args: - args (Namespace): Arguments to process - test_db (str or None): Directory containing the test database, None to - use the normal one - pwork (Patchwork): Patchwork object to use - """ - cser = cseries.Cseries(test_db) - try: - cser.open_database() - if args.subcmd == 'set-project': - if not pwork: - pwork = Patchwork(args.patchwork_url) - cser.project_set(pwork, args.project_name) - elif args.subcmd == 'get-project': - info = cser.project_get() - if not info: - raise ValueError("Project has not been set; use 'patman patchwork set-project'") - name, pwid, link_name = info - print(f"Project '{name}' patchwork-ID {pwid} link-name {link_name}") - else: - raise ValueError(f"Unknown patchwork subcommand '{args.subcmd}'") - finally: - cser.close_database() - -def do_patman(args, test_db=None, pwork=None, cser=None): - """Process a patman command - - Args: - args (Namespace): Arguments to process - test_db (str or None): Directory containing the test database, None to - use the normal one - pwork (Patchwork): Patchwork object to use, or None to create one - cser (Cseries): Cseries object to use when executing the command, - or None to create one - """ - if args.full_help: - with resources.path('patman', 'README.rst') as readme: - tools.print_full_help(str(readme)) - return 0 - if args.cmd == 'send': - # Called from git with a patch filename as argument - # Printout a list of additional CC recipients for this patch - if args.cc_cmd: - re_line = re.compile(r'(\S*) (.*)') - with open(args.cc_cmd, 'r', encoding='utf-8') as inf: - for line in inf.readlines(): - match = re_line.match(line) - if match and match.group(1) == args.patchfiles[0]: - for cca in match.group(2).split('\0'): - cca = cca.strip() - if cca: - print(cca) - else: - # If we are not processing tags, no need to warning about bad ones - if not args.process_tags: - args.ignore_bad_tags = True - do_send(args) - return 0 - - ret_code = 0 - try: - # Check status of patches in patchwork - if args.cmd == 'status': - patchwork_status(args.branch, args.count, args.start, args.end, - args.dest_branch, args.force, args.show_comments, - args.patchwork_url) - elif args.cmd == 'series': - do_series(args, test_db, pwork, cser) - elif args.cmd == 'upstream': - upstream(args, test_db) - elif args.cmd == 'patchwork': - patchwork(args, test_db, pwork) - except Exception as exc: - terminal.tprint(f'patman: {type(exc).__name__}: {exc}', - colour=terminal.Color.RED) - if args.debug: - print() - traceback.print_exc() - ret_code = 1 - return ret_code diff --git a/tools/patman/cser_helper.py b/tools/patman/cser_helper.py deleted file mode 100644 index 81ad212daee..00000000000 --- a/tools/patman/cser_helper.py +++ /dev/null @@ -1,1524 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2025 Simon Glass <[email protected]> -# -"""Helper functions for handling the 'series' subcommand -""" - -import asyncio -from collections import OrderedDict, defaultdict, namedtuple -from datetime import datetime -import hashlib -import os -import re -import sys -import time -from types import SimpleNamespace - -import aiohttp -import pygit2 -from pygit2.enums import CheckoutStrategy - -from u_boot_pylib import gitutil -from u_boot_pylib import terminal -from u_boot_pylib import tout - -from patman import patchstream -from patman.database import Database, Pcommit, SerVer -from patman import patchwork -from patman.series import Series -from patman import status - - -# Tag to use for Change IDs -CHANGE_ID_TAG = 'Change-Id' - -# Length of hash to display -HASH_LEN = 10 - -# Shorter version of some states, to save horizontal space -SHORTEN_STATE = { - 'handled-elsewhere': 'elsewhere', - 'awaiting-upstream': 'awaiting', - 'not-applicable': 'n/a', - 'changes-requested': 'changes', -} - -# Summary info returned from Cseries.link_auto_all() -AUTOLINK = namedtuple('autolink', 'name,version,link,desc,result') - - -def oid(oid_val): - """Convert a hash string into a shortened hash - - The number of hex digits git uses for showing hashes depends on the size of - the repo. For the purposes of showing hashes to the user in lists, we use a - fixed value for now - - Args: - str or Pygit2.oid: Hash value to shorten - - Return: - str: Shortened hash - """ - return str(oid_val)[:HASH_LEN] - - -def split_name_version(in_name): - """Split a branch name into its series name and its version - - For example: - 'series' returns ('series', 1) - 'series3' returns ('series', 3) - Args: - in_name (str): Name to parse - - Return: - tuple: - str: series name - int: series version, or None if there is none in in_name - """ - m_ver = re.match(r'([^0-9]*)(\d*)', in_name) - version = None - if m_ver: - name = m_ver.group(1) - if m_ver.group(2): - version = int(m_ver.group(2)) - else: - name = in_name - return name, version - - -class CseriesHelper: - """Helper functions for Cseries - - This class handles database read/write as well as operations in a git - directory to update series information. - """ - def __init__(self, topdir=None, colour=terminal.COLOR_IF_TERMINAL): - """Set up a new CseriesHelper - - Args: - topdir (str): Top-level directory of the repo - colour (terminal.enum): Whether to enable ANSI colour or not - - Properties: - gitdir (str): Git directory (typically topdir + '/.git') - db (Database): Database handler - col (terminal.Colour): Colour object - _fake_time (float): Holds the current fake time for tests, in - seconds - _fake_sleep (func): Function provided by a test; called to fake a - 'time.sleep()' call and take whatever action it wants to take. - The only argument is the (Float) time to sleep for; it returns - nothing - loop (asyncio event loop): Loop used for Patchwork operations - """ - self.topdir = topdir - self.gitdir = None - self.db = None - self.col = terminal.Color(colour) - self._fake_time = None - self._fake_sleep = None - self.fake_now = None - self.loop = asyncio.get_event_loop() - - def open_database(self): - """Open the database ready for use""" - if not self.topdir: - self.topdir = gitutil.get_top_level() - if not self.topdir: - raise ValueError('No git repo detected in current directory') - self.gitdir = os.path.join(self.topdir, '.git') - fname = f'{self.topdir}/.patman.db' - - # For the first instance, start it up with the expected schema - self.db, is_new = Database.get_instance(fname) - if is_new: - self.db.start() - else: - # If a previous test has already checked the schema, just open it - self.db.open_it() - - def close_database(self): - """Close the database""" - if self.db: - self.db.close() - - def commit(self): - """Commit changes to the database""" - self.db.commit() - - def rollback(self): - """Roll back changes to the database""" - self.db.rollback() - - def set_fake_time(self, fake_sleep): - """Setup the fake timer - - Args: - fake_sleep (func(float)): Function to call to fake a sleep - """ - self._fake_time = 0 - self._fake_sleep = fake_sleep - - def inc_fake_time(self, inc_s): - """Increment the fake time - - Args: - inc_s (float): Amount to increment the fake time by - """ - self._fake_time += inc_s - - def get_time(self): - """Get the current time, fake or real - - This function should always be used to read the time so that faking the - time works correctly in tests. - - Return: - float: Fake time, if time is being faked, else real time - """ - if self._fake_time is not None: - return self._fake_time - return time.monotonic() - - def sleep(self, time_s): - """Sleep for a while - - This function should always be used to sleep so that faking the time - works correctly in tests. - - Args: - time_s (float): Amount of seconds to sleep for - """ - print(f'Sleeping for {time_s} seconds') - if self._fake_time is not None: - self._fake_sleep(time_s) - else: - time.sleep(time_s) - - def get_now(self): - """Get the time now - - This function should always be used to read the datetime, so that - faking the time works correctly in tests - - Return: - DateTime object - """ - if self.fake_now: - return self.fake_now - return datetime.now() - - def get_ser_ver_list(self): - """Get a list of patchwork entries from the database - - Return: - list of SER_VER - """ - return self.db.ser_ver_get_list() - - def get_ser_ver_dict(self): - """Get a dict of patchwork entries from the database - - Return: dict contain all records: - key (int): ser_ver id - value (SER_VER): Information about one ser_ver record - """ - svlist = self.get_ser_ver_list() - svdict = {} - for sver in svlist: - svdict[sver.idnum] = sver - return svdict - - def get_upstream_dict(self): - """Get a list of upstream entries from the database - - Return: - OrderedDict: - key (str): upstream name - value (str): url - """ - return self.db.upstream_get_dict() - - def get_pcommit_dict(self, find_svid=None): - """Get a dict of pcommits entries from the database - - Args: - find_svid (int): If not None, finds the records associated with a - particular series and version - - Return: - OrderedDict: - key (int): record ID if find_svid is None, else seq - value (PCOMMIT): record data - """ - pcdict = OrderedDict() - for rec in self.db.pcommit_get_list(find_svid): - if find_svid is not None: - pcdict[rec.seq] = rec - else: - pcdict[rec.idnum] = rec - return pcdict - - def _get_series_info(self, idnum): - """Get information for a series from the database - - Args: - idnum (int): Series ID to look up - - Return: tuple: - str: Series name - str: Series description - - Raises: - ValueError: Series is not found - """ - return self.db.series_get_info(idnum) - - def prep_series(self, name, end=None): - """Prepare to work with a series - - Args: - name (str): Branch name with version appended, e.g. 'fix2' - end (str or None): Commit to end at, e.g. 'my_branch~16'. Only - commits up to that are processed. None to process commits up to - the upstream branch - - Return: tuple: - str: Series name, e.g. 'fix' - Series: Collected series information, including name - int: Version number, e.g. 2 - str: Message to show - """ - ser, version = self._parse_series_and_version(name, None) - if not name: - name = self._get_branch_name(ser.name, version) - - # First check we have a branch with this name - if not gitutil.check_branch(name, git_dir=self.gitdir): - raise ValueError(f"No branch named '{name}'") - - count = gitutil.count_commits_to_branch(name, self.gitdir, end) - if not count: - raise ValueError('Cannot detect branch automatically: ' - 'Perhaps use -U <upstream-commit> ?') - - series = patchstream.get_metadata(name, 0, count, git_dir=self.gitdir) - self._copy_db_fields_to(series, ser) - msg = None - if end: - repo = pygit2.Repository(self.gitdir) - target = repo.revparse_single(end) - first_line = target.message.splitlines()[0] - msg = f'Ending before {oid(target.id)} {first_line}' - - return name, series, version, msg - - def _copy_db_fields_to(self, series, in_series): - """Copy over fields used by Cseries from one series to another - - This copes desc, idnum and name - - Args: - series (Series): Series to copy to - in_series (Series): Series to copy from - """ - series.desc = in_series.desc - series.idnum = in_series.idnum - series.name = in_series.name - - def _handle_mark(self, branch_name, in_series, version, mark, - allow_unmarked, force_version, dry_run): - """Handle marking a series, checking for unmarked commits, etc. - - Args: - branch_name (str): Name of branch to sync, or None for current one - in_series (Series): Series object - version (int): branch version, e.g. 2 for 'mychange2' - mark (bool): True to mark each commit with a change ID - allow_unmarked (str): True to not require each commit to be marked - force_version (bool): True if ignore a Series-version tag that - doesn't match its branch name - dry_run (bool): True to do a dry run - - Returns: - Series: New series object, if the series was marked; - copy_db_fields_to() is used to copy fields over - - Raises: - ValueError: Series being unmarked when it should be marked, etc. - """ - series = in_series - if 'version' in series and int(series.version) != version: - msg = (f"Series name '{branch_name}' suggests version {version} " - f"but Series-version tag indicates {series.version}") - if not force_version: - raise ValueError(msg + ' (see --force-version)') - - tout.warning(msg) - tout.warning(f'Updating Series-version tag to version {version}') - self.update_series(branch_name, series, int(series.version), - new_name=None, dry_run=dry_run, - add_vers=version) - - # Collect the commits again, as the hashes have changed - series = patchstream.get_metadata(branch_name, 0, - len(series.commits), - git_dir=self.gitdir) - self._copy_db_fields_to(series, in_series) - - if mark: - add_oid = self._mark_series(branch_name, series, dry_run=dry_run) - - # Collect the commits again, as the hashes have changed - series = patchstream.get_metadata(add_oid, 0, len(series.commits), - git_dir=self.gitdir) - self._copy_db_fields_to(series, in_series) - - bad_count = 0 - for commit in series.commits: - if not commit.change_id: - bad_count += 1 - if bad_count and not allow_unmarked: - raise ValueError( - f'{bad_count} commit(s) are unmarked; please use -m or -M') - - return series - - def _add_series_commits(self, series, svid): - """Add a commits from a series into the database - - Args: - series (Series): Series containing commits to add - svid (int): ser_ver-table ID to use for each commit - """ - to_add = [Pcommit(None, seq, commit.subject, None, commit.change_id, - None, None, None) - for seq, commit in enumerate(series.commits)] - - self.db.pcommit_add_list(svid, to_add) - - def get_series_by_name(self, name, include_archived=False): - """Get a Series object from the database by name - - Args: - name (str): Name of series to get - include_archived (bool): True to search in archives series - - Return: - Series: Object containing series info, or None if none - """ - idnum = self.db.series_find_by_name(name, include_archived) - if not idnum: - return None - name, desc = self.db.series_get_info(idnum) - - return Series.from_fields(idnum, name, desc) - - def _get_branch_name(self, name, version): - """Get the branch name for a particular version - - Args: - name (str): Base name of branch - version (int): Version number to use - """ - return name + (f'{version}' if version > 1 else '') - - def _ensure_version(self, ser, version): - """Ensure that a version exists in a series - - Args: - ser (Series): Series information, with idnum and name used here - version (int): Version to check - - Returns: - list of int: List of versions - """ - versions = self._get_version_list(ser.idnum) - if version not in versions: - raise ValueError( - f"Series '{ser.name}' does not have a version {version}") - return versions - - def _set_link(self, ser_id, name, version, link, update_commit, - dry_run=False): - """Add / update a series-links link for a series - - Args: - ser_id (int): Series ID number - name (str): Series name (used to find the branch) - version (int): Version number (used to update the database) - link (str): Patchwork link-string for the series - update_commit (bool): True to update the current commit with the - link - dry_run (bool): True to do a dry run - - Return: - bool: True if the database was update, False if the ser_id or - version was not found - """ - if update_commit: - branch_name = self._get_branch_name(name, version) - _, ser, max_vers, _ = self.prep_series(branch_name) - self.update_series(branch_name, ser, max_vers, add_vers=version, - dry_run=dry_run, add_link=link) - if link is None: - link = '' - updated = 1 if self.db.ser_ver_set_link(ser_id, version, link) else 0 - if dry_run: - self.rollback() - else: - self.commit() - - return updated - - def _get_autolink_dict(self, sdict, link_all_versions): - """Get a dict of ser_vers to fetch, along with their patchwork links - - Note that this returns items that already have links, as well as those - without links - - Args: - sdict: - key: series ID - value: Series with idnum, name and desc filled out - link_all_versions (bool): True to sync all versions of a series, - False to sync only the latest version - - Return: tuple: - dict: - key (int): svid - value (tuple): - int: series ID - str: series name - int: series version - str: patchwork link for the series, or None if none - desc: cover-letter name / series description - """ - svdict = self.get_ser_ver_dict() - to_fetch = {} - - if link_all_versions: - for svinfo in self.get_ser_ver_list(): - ser = sdict[svinfo.series_id] - - pwc = self.get_pcommit_dict(svinfo.idnum) - count = len(pwc) - branch = self._join_name_version(ser.name, svinfo.version) - series = patchstream.get_metadata(branch, 0, count, - git_dir=self.gitdir) - self._copy_db_fields_to(series, ser) - - to_fetch[svinfo.idnum] = (svinfo.series_id, series.name, - svinfo.version, svinfo.link, series) - else: - # Find the maximum version for each series - max_vers = self._series_all_max_versions() - - # Get a list of links to fetch - for svid, ser_id, version in max_vers: - svinfo = svdict[svid] - ser = sdict[ser_id] - - pwc = self.get_pcommit_dict(svid) - count = len(pwc) - branch = self._join_name_version(ser.name, version) - series = patchstream.get_metadata(branch, 0, count, - git_dir=self.gitdir) - self._copy_db_fields_to(series, ser) - - to_fetch[svid] = (ser_id, series.name, version, svinfo.link, - series) - return to_fetch - - def _get_version_list(self, idnum): - """Get a list of the versions available for a series - - Args: - idnum (int): ID of series to look up - - Return: - str: List of versions - """ - if idnum is None: - raise ValueError('Unknown series idnum') - return self.db.series_get_version_list(idnum) - - def _join_name_version(self, in_name, version): - """Convert a series name plus a version into a branch name - - For example: - ('series', 1) returns 'series' - ('series', 3) returns 'series3' - - Args: - in_name (str): Series name - version (int): Version number - - Return: - str: associated branch name - """ - if version == 1: - return in_name - return f'{in_name}{version}' - - def _parse_series(self, name, include_archived=False): - """Parse the name of a series, or detect it from the current branch - - Args: - name (str or None): name of series - include_archived (bool): True to search in archives series - - Return: - Series: New object with the name set; idnum is also set if the - series exists in the database - """ - if not name: - name = gitutil.get_branch(self.gitdir) - name, _ = split_name_version(name) - ser = self.get_series_by_name(name, include_archived) - if not ser: - ser = Series() - ser.name = name - return ser - - def _parse_series_and_version(self, in_name, in_version): - """Parse name and version of a series, or detect from current branch - - Figures out the name from in_name, or if that is None, from the current - branch. - - Uses the version in_version, or if that is None, uses the int at the - end of the name (e.g. 'series' is version 1, 'series4' is version 4) - - Args: - in_name (str or None): name of series - in_version (str or None): version of series - - Return: - tuple: - Series: New object with the name set; idnum is also set if the - series exists in the database - int: Series version-number detected from the name - (e.g. 'fred' is version 1, 'fred2' is version 2) - """ - name = in_name - if not name: - name = gitutil.get_branch(self.gitdir) - if not name: - raise ValueError('No branch detected: please use -s <series>') - name, version = split_name_version(name) - if not name: - raise ValueError(f"Series name '{in_name}' cannot be a number, " - f"use '<name><version>'") - if in_version: - if version and version != in_version: - tout.warning( - f"Version mismatch: -V has {in_version} but branch name " - f'indicates {version}') - version = in_version - if not version: - version = 1 - if version > 99: - raise ValueError(f"Version {version} exceeds 99") - ser = self.get_series_by_name(name) - if not ser: - ser = Series() - ser.name = name - return ser, version - - def _series_get_version_stats(self, idnum, vers): - """Get the stats for a series - - Args: - idnum (int): ID number of series to process - vers (int): Version number to process - - Return: - tuple: - str: Status string, '<accepted>/<count>' - OrderedDict: - key (int): record ID if find_svid is None, else seq - value (PCOMMIT): record data - """ - svid, link = self._get_series_svid_link(idnum, vers) - pwc = self.get_pcommit_dict(svid) - count = len(pwc.values()) - if link: - accepted = 0 - for pcm in pwc.values(): - accepted += pcm.state == 'accepted' - else: - accepted = '-' - return f'{accepted}/{count}', pwc - - def get_series_svid(self, series_id, version): - """Get the patchwork ID of a series version - - Args: - series_id (int): id of the series to look up - version (int): version number to look up - - Return: - str: link found - - Raises: - ValueError: No matching series found - """ - return self._get_series_svid_link(series_id, version)[0] - - def _get_series_svid_link(self, series_id, version): - """Get the patchwork ID of a series version - - Args: - series_id (int): series ID to look up - version (int): version number to look up - - Return: - tuple: - int: record id - str: link - """ - recs = self.get_ser_ver(series_id, version) - return recs.idnum, recs.link - - def get_ser_ver(self, series_id, version): - """Get the patchwork details for a series version - - Args: - series_id (int): series ID to look up - version (int): version number to look up - - Return: - SER_VER: Requested information - - Raises: - ValueError: There is no matching idnum/version - """ - return self.db.ser_ver_get_for_series(series_id, version) - - def _prepare_process(self, name, count, new_name=None, quiet=False): - """Get ready to process all commits in a branch - - Args: - name (str): Name of the branch to process - count (int): Number of commits - new_name (str or None): New name, if a new branch is to be created - quiet (bool): True to avoid output (used for testing) - - Return: tuple: - pygit2.repo: Repo to use - pygit2.oid: Upstream commit, onto which commits should be added - Pygit2.branch: Original branch, for later use - str: (Possibly new) name of branch to process - list of Commit: commits to process, in order - pygit2.Reference: Original head before processing started - """ - upstream_guess = gitutil.get_upstream(self.gitdir, name)[0] - - tout.debug(f"_process_series name '{name}' new_name '{new_name}' " - f"upstream_guess '{upstream_guess}'") - dirty = gitutil.check_dirty(self.gitdir, self.topdir) - if dirty: - raise ValueError( - f"Modified files exist: use 'git status' to check: " - f'{dirty[:5]}') - repo = pygit2.Repository(self.gitdir) - - commit = None - upstream_name = None - if upstream_guess: - try: - upstream = repo.lookup_reference(upstream_guess) - upstream_name = upstream.name - commit = upstream.peel(pygit2.enums.ObjectType.COMMIT) - except KeyError: - pass - except pygit2.repository.InvalidSpecError as exc: - print(f"Error '{exc}'") - if not upstream_name: - upstream_name = f'{name}~{count}' - commit = repo.revparse_single(upstream_name) - - branch = repo.lookup_branch(name) - if not quiet: - tout.info( - f'Checking out upstream commit {upstream_name}: ' - f'{oid(commit.oid)}') - - old_head = repo.head - if old_head.shorthand == name: - old_head = None - else: - old_head = repo.head - - if new_name: - name = new_name - repo.set_head(commit.oid) - - commits = [] - cmt = repo.get(branch.target) - for _ in range(count): - commits.append(cmt) - cmt = cmt.parents[0] - - return (repo, repo.head, branch, name, commit, list(reversed(commits)), - old_head) - - def _pick_commit(self, repo, cmt): - """Apply a commit to the source tree, without committing it - - _prepare_process() must be called before starting to pick commits - - This function must be called before _finish_commit() - - Note that this uses a cherry-pick method, creating a new tree_id each - time, so can make source-code changes - - Args: - repo (pygit2.repo): Repo to use - cmt (Commit): Commit to apply - - Return: tuple: - tree_id (pygit2.oid): Oid of index with source-changes applied - commit (pygit2.oid): Old commit being cherry-picked - """ - tout.detail(f"- adding {oid(cmt.hash)} {cmt}") - repo.cherrypick(cmt.hash) - if repo.index.conflicts: - raise ValueError('Conflicts detected') - - tree_id = repo.index.write_tree() - cherry = repo.get(cmt.hash) - tout.detail(f"cherry {oid(cherry.oid)}") - return tree_id, cherry - - def _finish_commit(self, repo, tree_id, commit, cur, msg=None): - """Complete a commit - - This must be called after _pick_commit(). - - Args: - repo (pygit2.repo): Repo to use - tree_id (pygit2.oid): Oid of index with source-changes applied; if - None then the existing commit.tree_id is used - commit (pygit2.oid): Old commit being cherry-picked - cur (pygit2.reference): Reference to parent to use for the commit - msg (str): Commit subject and message; None to use commit.message - """ - if msg is None: - msg = commit.message - if not tree_id: - tree_id = commit.tree_id - repo.create_commit('HEAD', commit.author, commit.committer, - msg, tree_id, [cur.target]) - return repo.head - - def _finish_process(self, repo, branch, name, cur, old_head, new_name=None, - switch=False, dry_run=False, quiet=False): - """Finish processing commits - - Args: - repo (pygit2.repo): Repo to use - branch (pygit2.branch): Branch returned by _prepare_process() - name (str): Name of the branch to process - new_name (str or None): New name, if a new branch is being created - switch (bool): True to switch to the new branch after processing; - otherwise HEAD remains at the original branch, as amended - dry_run (bool): True to do a dry run, restoring the original tree - afterwards - quiet (bool): True to avoid output (used for testing) - - Return: - pygit2.reference: Final commit after everything is completed - """ - repo.state_cleanup() - - # Update the branch - target = repo.revparse_single('HEAD') - if not quiet: - tout.info(f'Updating branch {name} from {oid(branch.target)} to ' - f'{str(target.oid)[:HASH_LEN]}') - if dry_run: - if new_name: - repo.head.set_target(branch.target) - else: - branch_oid = branch.peel(pygit2.enums.ObjectType.COMMIT).oid - repo.head.set_target(branch_oid) - repo.head.set_target(branch.target) - repo.set_head(branch.name) - else: - if new_name: - new_branch = repo.branches.create(new_name, target) - if branch.upstream: - new_branch.upstream = branch.upstream - branch = new_branch - else: - branch.set_target(cur.target) - repo.set_head(branch.name) - if old_head: - if not switch: - repo.set_head(old_head.name) - return target - - def make_change_id(self, commit): - """Make a Change ID for a commit - - This is similar to the gerrit script: - git var GIT_COMMITTER_IDENT ; echo "$refhash" ; cat "README"; } - | git hash-object --stdin) - - Args: - commit (pygit2.commit): Commit to process - - Return: - Change ID in hex format - """ - sig = commit.committer - val = hashlib.sha1() - to_hash = f'{sig.name} <{sig.email}> {sig.time} {sig.offset}' - val.update(to_hash.encode('utf-8')) - val.update(str(commit.tree_id).encode('utf-8')) - val.update(commit.message.encode('utf-8')) - return val.hexdigest() - - def _filter_commits(self, name, series, seq_to_drop): - """Filter commits to drop one - - This function rebases the current branch, dropping a single commit, - thus changing the resulting code in the tree. - - Args: - name (str): Name of the branch to process - series (Series): Series object - seq_to_drop (int): Commit sequence to drop; commits are numbered - from 0, which is the one after the upstream branch, to - count - 1 - """ - count = len(series.commits) - (repo, cur, branch, name, commit, _, _) = self._prepare_process( - name, count, quiet=True) - repo.checkout_tree(commit, strategy=CheckoutStrategy.FORCE | - CheckoutStrategy.RECREATE_MISSING) - repo.set_head(commit.oid) - for seq, cmt in enumerate(series.commits): - if seq != seq_to_drop: - tree_id, cherry = self._pick_commit(repo, cmt) - cur = self._finish_commit(repo, tree_id, cherry, cur) - self._finish_process(repo, branch, name, cur, None, quiet=True) - - def process_series(self, name, series, new_name=None, switch=False, - dry_run=False): - """Rewrite a series commit messages, leaving code alone - - This uses a 'vals' namespace to pass things to the controlling - function. - - Each time _process_series() yields, it sets up: - commit (Commit): The pygit2 commit that is being processed - msg (str): Commit message, which can be modified - info (str): Initially empty; the controlling function can add a - short message here which will be shown to the user - final (bool): True if this is the last commit to apply - seq (int): Current sequence number in the commits to apply (0,,n-1) - - It also sets git HEAD at the commit before this commit being - processed - - The function can change msg and info, e.g. to add or remove tags from - the commit. - - Args: - name (str): Name of the branch to process - series (Series): Series object - new_name (str or None): New name, if a new branch is to be created - switch (bool): True to switch to the new branch after processing; - otherwise HEAD remains at the original branch, as amended - dry_run (bool): True to do a dry run, restoring the original tree - afterwards - - Return: - pygit.oid: oid of the new branch - """ - count = len(series.commits) - repo, cur, branch, name, _, commits, old_head = self._prepare_process( - name, count, new_name) - vals = SimpleNamespace() - vals.final = False - tout.info(f"Processing {count} commits from branch '{name}'") - - # Record the message lines - lines = [] - for seq, cmt in enumerate(series.commits): - commit = commits[seq] - vals.commit = commit - vals.msg = commit.message - vals.info = '' - vals.final = seq == len(series.commits) - 1 - vals.seq = seq - yield vals - - cur = self._finish_commit(repo, None, commit, cur, vals.msg) - lines.append([vals.info.strip(), - f'{oid(cmt.hash)} as {oid(cur.target)} {cmt}']) - - max_len = max(len(info) for info, rest in lines) + 1 - for info, rest in lines: - if info: - info += ':' - tout.info(f'- {info.ljust(max_len)} {rest}') - target = self._finish_process(repo, branch, name, cur, old_head, - new_name, switch, dry_run) - vals.oid = target.oid - - def _mark_series(self, name, series, dry_run=False): - """Mark a series with Change-Id tags - - Args: - name (str): Name of the series to mark - series (Series): Series object - dry_run (bool): True to do a dry run, restoring the original tree - afterwards - - Return: - pygit.oid: oid of the new branch - """ - vals = None - for vals in self.process_series(name, series, dry_run=dry_run): - if CHANGE_ID_TAG not in vals.msg: - change_id = self.make_change_id(vals.commit) - vals.msg = vals.msg + f'\n{CHANGE_ID_TAG}: {change_id}' - tout.detail(" - adding mark") - vals.info = 'marked' - else: - vals.info = 'has mark' - - return vals.oid - - def update_series(self, branch_name, series, max_vers, new_name=None, - dry_run=False, add_vers=None, add_link=None, - add_rtags=None, switch=False): - """Rewrite a series to update the Series-version/Series-links lines - - This updates the series in git; it does not update the database - - Args: - branch_name (str): Name of the branch to process - series (Series): Series object - max_vers (int): Version number of the series being updated - new_name (str or None): New name, if a new branch is to be created - dry_run (bool): True to do a dry run, restoring the original tree - afterwards - add_vers (int or None): Version number to add to the series, if any - add_link (str or None): Link to add to the series, if any - add_rtags (list of dict): List of review tags to add, one item for - each commit, each a dict: - key: Response tag (e.g. 'Reviewed-by') - value: Set of people who gave that response, each a name/email - string - switch (bool): True to switch to the new branch after processing; - otherwise HEAD remains at the original branch, as amended - - Return: - pygit.oid: oid of the new branch - """ - def _do_version(): - if add_vers: - if add_vers == 1: - vals.info += f'rm v{add_vers} ' - else: - vals.info += f'add v{add_vers} ' - out.append(f'Series-version: {add_vers}') - - def _do_links(new_links): - if add_link: - if 'add' not in vals.info: - vals.info += 'add ' - vals.info += f"links '{new_links}' " - else: - vals.info += f"upd links '{new_links}' " - out.append(f'Series-links: {new_links}') - - added_version = False - added_link = False - for vals in self.process_series(branch_name, series, new_name, switch, - dry_run): - out = [] - for line in vals.msg.splitlines(): - m_ver = re.match('Series-version:(.*)', line) - m_links = re.match('Series-links:(.*)', line) - if m_ver and add_vers: - if ('version' in series and - int(series.version) != max_vers): - tout.warning( - f'Branch {branch_name}: Series-version tag ' - f'{series.version} does not match expected ' - f'version {max_vers}') - _do_version() - added_version = True - elif m_links: - links = series.get_links(m_links.group(1), max_vers) - if add_link: - links[max_vers] = add_link - _do_links(series.build_links(links)) - added_link = True - else: - out.append(line) - if vals.final: - if not added_version and add_vers and add_vers > 1: - _do_version() - if not added_link and add_link: - _do_links(f'{max_vers}:{add_link}') - - vals.msg = '\n'.join(out) + '\n' - if add_rtags and add_rtags[vals.seq]: - lines = [] - for tag, people in add_rtags[vals.seq].items(): - for who in people: - lines.append(f'{tag}: {who}') - vals.msg = patchstream.insert_tags(vals.msg.rstrip(), - sorted(lines)) - vals.info += (f'added {len(lines)} ' - f"tag{'' if len(lines) == 1 else 's'}") - - def _build_col(self, state, prefix='', base_str=None): - """Build a patch-state string with colour - - Args: - state (str): State to colourise (also indicates the colour to use) - prefix (str): Prefix string to also colourise - base_str (str or None): String to show instead of state, or None to - show state - - Return: - str: String with ANSI colour characters - """ - bright = True - if state == 'accepted': - col = self.col.GREEN - elif state == 'awaiting-upstream': - bright = False - col = self.col.GREEN - elif state in ['changes-requested']: - col = self.col.CYAN - elif state in ['rejected', 'deferred', 'not-applicable', 'superseded', - 'handled-elsewhere']: - col = self.col.RED - elif not state: - state = 'unknown' - col = self.col.MAGENTA - else: - # under-review, rfc, needs-review-ack - col = self.col.WHITE - out = base_str or SHORTEN_STATE.get(state, state) - pad = ' ' * (10 - len(out)) - col_state = self.col.build(col, prefix + out, bright) - return col_state, pad - - def _get_patches(self, series, version): - """Get a Series object containing the patches in a series - - Args: - series (str): Name of series to use, or None to use current branch - version (int): Version number, or None to detect from name - - Return: tuple: - str: Name of branch, e.g. 'mary2' - Series: Series object containing the commits and idnum, desc, name - int: Version number of series, e.g. 2 - OrderedDict: - key (int): record ID if find_svid is None, else seq - value (PCOMMIT): record data - str: series name (for this version) - str: patchwork link - str: cover_id - int: cover_num_comments - """ - ser, version = self._parse_series_and_version(series, version) - if not ser.idnum: - raise ValueError(f"Unknown series '{series}'") - self._ensure_version(ser, version) - svinfo = self.get_ser_ver(ser.idnum, version) - pwc = self.get_pcommit_dict(svinfo.idnum) - - count = len(pwc) - branch = self._join_name_version(ser.name, version) - series = patchstream.get_metadata(branch, 0, count, - git_dir=self.gitdir) - self._copy_db_fields_to(series, ser) - - return (branch, series, version, pwc, svinfo.name, svinfo.link, - svinfo.cover_id, svinfo.cover_num_comments) - - def _list_patches(self, branch, pwc, series, desc, cover_id, num_comments, - show_commit, show_patch, list_patches, state_totals): - """List patches along with optional status info - - Args: - branch (str): Branch name if self.show_progress - pwc (dict): pcommit records: - key (int): seq - value (PCOMMIT): Record from database - series (Series): Series to show, or None to just use the database - desc (str): Series title - cover_id (int): Cover-letter ID - num_comments (int): The number of comments on the cover letter - show_commit (bool): True to show the commit and diffstate - show_patch (bool): True to show the patch - list_patches (bool): True to list all patches for each series, - False to just show the series summary on a single line - state_totals (dict): Holds totals for each state across all patches - key (str): state name - value (int): Number of patches in that state - - Return: - bool: True if OK, False if any commit subjects don't match their - patchwork subjects - """ - lines = [] - states = defaultdict(int) - count = len(pwc) - ok = True - for seq, item in enumerate(pwc.values()): - if series: - cmt = series.commits[seq] - if cmt.subject != item.subject: - ok = False - - col_state, pad = self._build_col(item.state) - patch_id = item.patch_id if item.patch_id else '' - if item.num_comments: - comments = str(item.num_comments) - elif item.num_comments is None: - comments = '-' - else: - comments = '' - - if show_commit or show_patch: - subject = self.col.build(self.col.BLACK, item.subject, - bright=False, back=self.col.YELLOW) - else: - subject = item.subject - - line = (f'{seq:3} {col_state}{pad} {comments.rjust(3)} ' - f'{patch_id:7} {oid(cmt.hash)} {subject}') - lines.append(line) - states[item.state] += 1 - out = '' - for state, freq in states.items(): - out += ' ' + self._build_col(state, f'{freq}:')[0] - state_totals[state] += freq - name = '' - if not list_patches: - name = desc or series.desc - name = self.col.build(self.col.YELLOW, name[:41].ljust(41)) - if not ok: - out = '*' + out[1:] - print(f"{branch:16} {name} {len(pwc):5} {out}") - return ok - print(f"Branch '{branch}' (total {len(pwc)}):{out}{name}") - - print(self.col.build( - self.col.MAGENTA, - f"Seq State Com PatchId {'Commit'.ljust(HASH_LEN)} Subject")) - - comments = '' if num_comments is None else str(num_comments) - if desc or comments or cover_id: - cov = 'Cov' if cover_id else '' - print(self.col.build( - self.col.WHITE, - f"{cov:14} {comments.rjust(3)} {cover_id or '':7} " - f'{desc or series.desc}', - bright=False)) - for seq in range(count): - line = lines[seq] - print(line) - if show_commit or show_patch: - print() - cmt = series.commits[seq] if series else '' - msg = gitutil.show_commit( - cmt.hash, show_commit, True, show_patch, - colour=self.col.enabled(), git_dir=self.gitdir) - sys.stdout.write(msg) - if seq != count - 1: - print() - print() - - return ok - - def _find_matched_commit(self, commits, pcm): - """Find a commit in a list of possible matches - - Args: - commits (dict of Commit): Possible matches - key (int): sequence number of patch (from 0) - value (Commit): Commit object - pcm (PCOMMIT): Patch to check - - Return: - int: Sequence number of matching commit, or None if not found - """ - for seq, cmt in commits.items(): - tout.debug(f"- match subject: '{cmt.subject}'") - if pcm.subject == cmt.subject: - return seq - return None - - def _find_matched_patch(self, patches, cmt): - """Find a patch in a list of possible matches - - Args: - patches: dict of ossible matches - key (int): sequence number of patch - value (PCOMMIT): patch - cmt (Commit): Commit to check - - Return: - int: Sequence number of matching patch, or None if not found - """ - for seq, pcm in patches.items(): - tout.debug(f"- match subject: '{pcm.subject}'") - if cmt.subject == pcm.subject: - return seq - return None - - def _sync_one(self, svid, series_name, version, show_comments, - show_cover_comments, gather_tags, cover, patches, dry_run): - """Sync one series to the database - - Args: - svid (int): Ser/ver ID - cover (dict or None): Cover letter from patchwork, with keys: - id (int): Cover-letter ID in patchwork - num_comments (int): Number of comments - name (str): Cover-letter name - patches (list of Patch): Patches in the series - """ - pwc = self.get_pcommit_dict(svid) - if gather_tags: - count = len(pwc) - branch = self._join_name_version(series_name, version) - series = patchstream.get_metadata(branch, 0, count, - git_dir=self.gitdir) - - _, new_rtag_list = status.do_show_status( - series, cover, patches, show_comments, show_cover_comments, - self.col, warnings_on_stderr=False) - self.update_series(branch, series, version, None, dry_run, - add_rtags=new_rtag_list) - - updated = 0 - for seq, item in enumerate(pwc.values()): - if seq >= len(patches): - continue - patch = patches[seq] - if patch.id: - if self.db.pcommit_update( - Pcommit(item.idnum, seq, None, None, None, patch.state, - patch.id, len(patch.comments))): - updated += 1 - if cover: - info = SerVer(svid, None, None, None, cover.id, - cover.num_comments, cover.name, None) - else: - info = SerVer(svid, None, None, None, None, None, patches[0].name, - None) - self.db.ser_ver_set_info(info) - - return updated, 1 if cover else 0 - - async def _gather(self, pwork, link, show_cover_comments): - """Sync the series status from patchwork - - Creates a new client sesion and calls _sync() - - Args: - pwork (Patchwork): Patchwork object to use - link (str): Patchwork link for the series - show_cover_comments (bool): True to show the comments on the cover - letter - - Return: tuple: - COVER object, or None if none or not read_cover_comments - list of PATCH objects - """ - async with aiohttp.ClientSession() as client: - return await pwork.series_get_state(client, link, True, - show_cover_comments) - - def _get_fetch_dict(self, sync_all_versions): - """Get a dict of ser_vers to fetch, along with their patchwork links - - Args: - sync_all_versions (bool): True to sync all versions of a series, - False to sync only the latest version - - Return: tuple: - dict: things to fetch - key (int): svid - value (str): patchwork link for the series - int: number of series which are missing a link - """ - missing = 0 - svdict = self.get_ser_ver_dict() - sdict = self.db.series_get_dict_by_id() - to_fetch = {} - - if sync_all_versions: - for svinfo in self.get_ser_ver_list(): - ser_ver = svdict[svinfo.idnum] - if svinfo.link: - to_fetch[svinfo.idnum] = patchwork.STATE_REQ( - svinfo.link, svinfo.series_id, - sdict[svinfo.series_id].name, svinfo.version, False, - False) - else: - missing += 1 - else: - # Find the maximum version for each series - max_vers = self._series_all_max_versions() - - # Get a list of links to fetch - for svid, series_id, version in max_vers: - ser_ver = svdict[svid] - if series_id not in sdict: - # skip archived item - continue - if ser_ver.link: - to_fetch[svid] = patchwork.STATE_REQ( - ser_ver.link, series_id, sdict[series_id].name, - version, False, False) - else: - missing += 1 - - # order by series name, version - ordered = OrderedDict() - for svid in sorted( - to_fetch, - key=lambda k: (to_fetch[k].series_name, to_fetch[k].version)): - sync = to_fetch[svid] - ordered[svid] = sync - - return ordered, missing - - async def _sync_all(self, client, pwork, to_fetch): - """Sync all series status from patchwork - - Args: - pwork (Patchwork): Patchwork object to use - sync_all_versions (bool): True to sync all versions of a series, - False to sync only the latest version - gather_tags (bool): True to gather review/test tags - - Return: list of tuple: - COVER object, or None if none or not read_cover_comments - list of PATCH objects - """ - with pwork.collect_stats() as stats: - tasks = [pwork.series_get_state(client, sync.link, True, True) - for sync in to_fetch.values() if sync.link] - result = await asyncio.gather(*tasks) - return result, stats.request_count - - async def _do_series_sync_all(self, pwork, to_fetch): - async with aiohttp.ClientSession() as client: - return await self._sync_all(client, pwork, to_fetch) - - def _progress_one(self, ser, show_all_versions, list_patches, - state_totals): - """Show progress information for all versions in a series - - Args: - ser (Series): Series to use - show_all_versions (bool): True to show all versions of a series, - False to show only the final version - list_patches (bool): True to list all patches for each series, - False to just show the series summary on a single line - state_totals (dict): Holds totals for each state across all patches - key (str): state name - value (int): Number of patches in that state - - Return: tuple - int: Number of series shown - int: Number of patches shown - int: Number of version which need a 'scan' - """ - max_vers = self._series_max_version(ser.idnum) - name, desc = self._get_series_info(ser.idnum) - coloured = self.col.build(self.col.BLACK, desc, bright=False, - back=self.col.YELLOW) - versions = self._get_version_list(ser.idnum) - vstr = list(map(str, versions)) - - if list_patches: - print(f"{name}: {coloured} (versions: {' '.join(vstr)})") - add_blank_line = False - total_series = 0 - total_patches = 0 - need_scan = 0 - for ver in versions: - if not show_all_versions and ver != max_vers: - continue - if add_blank_line: - print() - _, pwc = self._series_get_version_stats(ser.idnum, ver) - count = len(pwc) - branch = self._join_name_version(ser.name, ver) - series = patchstream.get_metadata(branch, 0, count, - git_dir=self.gitdir) - svinfo = self.get_ser_ver(ser.idnum, ver) - self._copy_db_fields_to(series, ser) - - ok = self._list_patches( - branch, pwc, series, svinfo.name, svinfo.cover_id, - svinfo.cover_num_comments, False, False, list_patches, - state_totals) - if not ok: - need_scan += 1 - add_blank_line = list_patches - total_series += 1 - total_patches += count - return total_series, total_patches, need_scan - - def _summary_one(self, ser): - """Show summary information for the latest version in a series - - Args: - series (str): Name of series to use, or None to show progress for - all series - """ - max_vers = self._series_max_version(ser.idnum) - name, desc = self._get_series_info(ser.idnum) - stats, pwc = self._series_get_version_stats(ser.idnum, max_vers) - states = {x.state for x in pwc.values()} - state = 'accepted' - for val in ['awaiting-upstream', 'changes-requested', 'rejected', - 'deferred', 'not-applicable', 'superseded', - 'handled-elsewhere']: - if val in states: - state = val - state_str, pad = self._build_col(state, base_str=name) - print(f"{state_str}{pad} {stats.rjust(6)} {desc}") - - def _series_max_version(self, idnum): - """Find the latest version of a series - - Args: - idnum (int): Series ID to look up - - Return: - int: maximum version - """ - return self.db.series_get_max_version(idnum) - - def _series_all_max_versions(self): - """Find the latest version of all series - - Return: list of: - int: ser_ver ID - int: series ID - int: Maximum version - """ - return self.db.series_get_all_max_versions() diff --git a/tools/patman/cseries.py b/tools/patman/cseries.py deleted file mode 100644 index 0844b5f0257..00000000000 --- a/tools/patman/cseries.py +++ /dev/null @@ -1,1165 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2025 Google LLC -# -"""Handles the 'series' subcommand -""" - -import asyncio -from collections import OrderedDict, defaultdict - -import pygit2 - -from u_boot_pylib import cros_subprocess -from u_boot_pylib import gitutil -from u_boot_pylib import terminal -from u_boot_pylib import tout - -from patman import patchstream -from patman import cser_helper -from patman.cser_helper import AUTOLINK, oid -from patman import send -from patman import status - - -class Cseries(cser_helper.CseriesHelper): - """Database with information about series - - This class handles database read/write as well as operations in a git - directory to update series information. - """ - def __init__(self, topdir=None, colour=terminal.COLOR_IF_TERMINAL): - """Set up a new Cseries - - Args: - topdir (str): Top-level directory of the repo - colour (terminal.enum): Whether to enable ANSI colour or not - """ - super().__init__(topdir, colour) - - def add(self, branch_name, desc=None, mark=False, allow_unmarked=False, - end=None, force_version=False, dry_run=False): - """Add a series (or new version of a series) to the database - - Args: - branch_name (str): Name of branch to sync, or None for current one - desc (str): Description to use, or None to use the series subject - mark (str): True to mark each commit with a change ID - allow_unmarked (str): True to not require each commit to be marked - end (str): Add only commits up to but exclu - force_version (bool): True if ignore a Series-version tag that - doesn't match its branch name - dry_run (bool): True to do a dry run - """ - name, ser, version, msg = self.prep_series(branch_name, end) - tout.info(f"Adding series '{ser.name}' v{version}: mark {mark} " - f'allow_unmarked {allow_unmarked}') - if msg: - tout.info(msg) - if desc is None: - if not ser.cover: - raise ValueError(f"Branch '{name}' has no cover letter - " - 'please provide description') - desc = ser['cover'][0] - - ser = self._handle_mark(name, ser, version, mark, allow_unmarked, - force_version, dry_run) - link = ser.get_link_for_version(version) - - msg = 'Added' - added = False - series_id = self.db.series_find_by_name(ser.name) - if not series_id: - series_id = self.db.series_add(ser.name, desc) - added = True - msg += f" series '{ser.name}'" - - if version not in self._get_version_list(series_id): - svid = self.db.ser_ver_add(series_id, version, link) - msg += f" v{version}" - if not added: - msg += f" to existing series '{ser.name}'" - added = True - - self._add_series_commits(ser, svid) - count = len(ser.commits) - msg += f" ({count} commit{'s' if count > 1 else ''})" - if not added: - tout.info(f"Series '{ser.name}' v{version} already exists") - msg = None - elif not dry_run: - self.commit() - else: - self.rollback() - series_id = None - ser.desc = desc - ser.idnum = series_id - - if msg: - tout.info(msg) - if dry_run: - tout.info('Dry run completed') - - def decrement(self, series, dry_run=False): - """Decrement a series to the previous version and delete the branch - - Args: - series (str): Name of series to use, or None to use current branch - dry_run (bool): True to do a dry run - """ - ser = self._parse_series(series) - if not ser.idnum: - raise ValueError(f"Series '{ser.name}' not found in database") - - max_vers = self._series_max_version(ser.idnum) - if max_vers < 2: - raise ValueError(f"Series '{ser.name}' only has one version") - - tout.info(f"Removing series '{ser.name}' v{max_vers}") - - new_max = max_vers - 1 - - repo = pygit2.Repository(self.gitdir) - if not dry_run: - name = self._get_branch_name(ser.name, new_max) - branch = repo.lookup_branch(name) - try: - repo.checkout(branch) - except pygit2.errors.GitError: - tout.warning(f"Failed to checkout branch {name}") - raise - - del_name = f'{ser.name}{max_vers}' - del_branch = repo.lookup_branch(del_name) - branch_oid = del_branch.peel(pygit2.enums.ObjectType.COMMIT).oid - del_branch.delete() - print(f"Deleted branch '{del_name}' {oid(branch_oid)}") - - self.db.ser_ver_remove(ser.idnum, max_vers) - if not dry_run: - self.commit() - else: - self.rollback() - - def increment(self, series_name, dry_run=False): - """Increment a series to the next version and create a new branch - - Args: - series_name (str): Name of series to use, or None to use current - branch - dry_run (bool): True to do a dry run - """ - ser = self._parse_series(series_name) - if not ser.idnum: - raise ValueError(f"Series '{ser.name}' not found in database") - - max_vers = self._series_max_version(ser.idnum) - - branch_name = self._get_branch_name(ser.name, max_vers) - on_branch = gitutil.get_branch(self.gitdir) == branch_name - svid = self.get_series_svid(ser.idnum, max_vers) - pwc = self.get_pcommit_dict(svid) - count = len(pwc.values()) - series = patchstream.get_metadata(branch_name, 0, count, - git_dir=self.gitdir) - tout.info(f"Increment '{ser.name}' v{max_vers}: {count} patches") - - # Create a new branch - vers = max_vers + 1 - new_name = self._join_name_version(ser.name, vers) - - self.update_series(branch_name, series, max_vers, new_name, dry_run, - add_vers=vers, switch=on_branch) - - old_svid = self.get_series_svid(ser.idnum, max_vers) - pcd = self.get_pcommit_dict(old_svid) - - svid = self.db.ser_ver_add(ser.idnum, vers) - self.db.pcommit_add_list(svid, pcd.values()) - if not dry_run: - self.commit() - else: - self.rollback() - - # repo.head.set_target(amended) - tout.info(f'Added new branch {new_name}') - if dry_run: - tout.info('Dry run completed') - - def link_set(self, series_name, version, link, update_commit): - """Add / update a series-links link for a series - - Args: - series_name (str): Name of series to use, or None to use current - branch - version (int): Version number, or None to detect from name - link (str): Patchwork link-string for the series - update_commit (bool): True to update the current commit with the - link - """ - ser, version = self._parse_series_and_version(series_name, version) - self._ensure_version(ser, version) - - self._set_link(ser.idnum, ser.name, version, link, update_commit) - self.commit() - tout.info(f"Setting link for series '{ser.name}' v{version} to {link}") - - def link_get(self, series, version): - """Get the patchwork link for a version of a series - - Args: - series (str): Name of series to use, or None to use current branch - version (int): Version number or None for current - - Return: - str: Patchwork link as a string, e.g. '12325' - """ - ser, version = self._parse_series_and_version(series, version) - self._ensure_version(ser, version) - return self.db.ser_ver_get_link(ser.idnum, version) - - def link_search(self, pwork, series, version): - """Search patch for the link for a series - - Returns either the single match, or None, in which case the second part - of the tuple is filled in - - Args: - pwork (Patchwork): Patchwork object to use - series (str): Series name to search for, or None for current series - that is checked out - version (int): Version to search for, or None for current version - detected from branch name - - Returns: - tuple: - int: ID of the series found, or None - list of possible matches, or None, each a dict: - 'id': series ID - 'name': series name - str: series name - int: series version - str: series description - """ - _, ser, version, _, _, _, _, _ = self._get_patches(series, version) - - if not ser.desc: - raise ValueError(f"Series '{ser.name}' has an empty description") - - pws, options = self.loop.run_until_complete(pwork.find_series( - ser, version)) - return pws, options, ser.name, version, ser.desc - - def link_auto(self, pwork, series, version, update_commit, wait_s=0): - """Automatically find a series link by looking in patchwork - - Args: - pwork (Patchwork): Patchwork object to use - series (str): Series name to search for, or None for current series - that is checked out - version (int): Version to search for, or None for current version - detected from branch name - update_commit (bool): True to update the current commit with the - link - wait_s (int): Number of seconds to wait for the autolink to succeed - """ - start = self.get_time() - stop = start + wait_s - sleep_time = 5 - while True: - pws, options, name, version, desc = self.link_search( - pwork, series, version) - if pws: - if wait_s: - tout.info('Link completed after ' - f'{self.get_time() - start} seconds') - break - - print(f"Possible matches for '{name}' v{version} desc '{desc}':") - print(' Link Version Description') - for opt in options: - print(f"{opt['id']:6} {opt['version']:7} {opt['name']}") - if not wait_s or self.get_time() > stop: - delay = f' after {wait_s} seconds' if wait_s else '' - raise ValueError(f"Cannot find series '{desc}{delay}'") - - self.sleep(sleep_time) - - self.link_set(name, version, pws, update_commit) - - def link_auto_all(self, pwork, update_commit, link_all_versions, - replace_existing, dry_run, show_summary=True): - """Automatically find a series link by looking in patchwork - - Args: - pwork (Patchwork): Patchwork object to use - update_commit (bool): True to update the current commit with the - link - link_all_versions (bool): True to sync all versions of a series, - False to sync only the latest version - replace_existing (bool): True to sync a series even if it already - has a link - dry_run (bool): True to do a dry run - show_summary (bool): True to show a summary of how things went - - Return: - OrderedDict of summary info: - key (int): ser_ver ID - value (AUTOLINK): result of autolinking on this ser_ver - """ - sdict = self.db.series_get_dict_by_id() - all_ser_vers = self._get_autolink_dict(sdict, link_all_versions) - - # Get rid of things without a description - valid = {} - state = {} - no_desc = 0 - not_found = 0 - updated = 0 - failed = 0 - already = 0 - for svid, (ser_id, name, version, link, desc) in all_ser_vers.items(): - if link and not replace_existing: - state[svid] = f'already:{link}' - already += 1 - elif desc: - valid[svid] = ser_id, version, link, desc - else: - no_desc += 1 - state[svid] = 'missing description' - - results, requests = self.loop.run_until_complete( - pwork.find_series_list(valid)) - - for svid, ser_id, link, _ in results: - if link: - version = all_ser_vers[svid][2] - if self._set_link(ser_id, sdict[ser_id].name, version, - link, update_commit, dry_run=dry_run): - updated += 1 - state[svid] = f'linked:{link}' - else: - failed += 1 - state[svid] = 'failed' - else: - not_found += 1 - state[svid] = 'not found' - - # Create a summary sorted by name and version - summary = OrderedDict() - for svid in sorted(all_ser_vers, key=lambda k: all_ser_vers[k][1:2]): - _, name, version, link, ser = all_ser_vers[svid] - summary[svid] = AUTOLINK(name, version, link, ser.desc, - state[svid]) - - if show_summary: - msg = f'{updated} series linked' - if already: - msg += f', {already} already linked' - if not_found: - msg += f', {not_found} not found' - if no_desc: - msg += f', {no_desc} missing description' - if failed: - msg += f', {failed} updated failed' - tout.info(msg + f' ({requests} requests)') - - tout.info('') - tout.info(f"{'Name':15} Version {'Description':40} Result") - border = f"{'-' * 15} ------- {'-' * 40} {'-' * 15}" - tout.info(border) - for name, version, link, desc, state in summary.values(): - bright = True - if state.startswith('already'): - col = self.col.GREEN - bright = False - elif state.startswith('linked'): - col = self.col.MAGENTA - else: - col = self.col.RED - col_state = self.col.build(col, state, bright) - tout.info(f"{name:16.16} {version:7} {desc or '':40.40} " - f'{col_state}') - tout.info(border) - if dry_run: - tout.info('Dry run completed') - - return summary - - def series_list(self): - """List all series - - Lines all series along with their description, number of patches - accepted and the available versions - """ - sdict = self.db.series_get_dict() - print(f"{'Name':15} {'Description':40} Accepted Versions") - border = f"{'-' * 15} {'-' * 40} -------- {'-' * 15}" - print(border) - for name in sorted(sdict): - ser = sdict[name] - versions = self._get_version_list(ser.idnum) - stat = self._series_get_version_stats( - ser.idnum, self._series_max_version(ser.idnum))[0] - - vlist = ' '.join([str(ver) for ver in sorted(versions)]) - - print(f'{name:16.16} {ser.desc:41.41} {stat.rjust(8)} {vlist}') - print(border) - - def list_patches(self, series, version, show_commit=False, - show_patch=False): - """List patches in a series - - Args: - series (str): Name of series to use, or None to use current branch - version (int): Version number, or None to detect from name - show_commit (bool): True to show the commit and diffstate - show_patch (bool): True to show the patch - """ - branch, series, version, pwc, name, _, cover_id, num_comments = ( - self._get_patches(series, version)) - with terminal.pager(): - state_totals = defaultdict(int) - self._list_patches(branch, pwc, series, name, cover_id, - num_comments, show_commit, show_patch, True, - state_totals) - - def mark(self, in_name, allow_marked=False, dry_run=False): - """Add Change-Id tags to a series - - Args: - in_name (str): Name of the series to unmark - allow_marked (bool): Allow commits to be (already) marked - dry_run (bool): True to do a dry run, restoring the original tree - afterwards - - Return: - pygit.oid: oid of the new branch - """ - name, ser, _, _ = self.prep_series(in_name) - tout.info(f"Marking series '{name}': allow_marked {allow_marked}") - - if not allow_marked: - bad = [] - for cmt in ser.commits: - if cmt.change_id: - bad.append(cmt) - if bad: - print(f'{len(bad)} commit(s) already have marks') - for cmt in bad: - print(f' - {oid(cmt.hash)} {cmt.subject}') - raise ValueError( - f'Marked commits {len(bad)}/{len(ser.commits)}') - new_oid = self._mark_series(in_name, ser, dry_run=dry_run) - - if dry_run: - tout.info('Dry run completed') - return new_oid - - def unmark(self, name, allow_unmarked=False, dry_run=False): - """Remove Change-Id tags from a series - - Args: - name (str): Name of the series to unmark - allow_unmarked (bool): Allow commits to be (already) unmarked - dry_run (bool): True to do a dry run, restoring the original tree - afterwards - - Return: - pygit.oid: oid of the new branch - """ - name, ser, _, _ = self.prep_series(name) - tout.info( - f"Unmarking series '{name}': allow_unmarked {allow_unmarked}") - - if not allow_unmarked: - bad = [] - for cmt in ser.commits: - if not cmt.change_id: - bad.append(cmt) - if bad: - print(f'{len(bad)} commit(s) are missing marks') - for cmt in bad: - print(f' - {oid(cmt.hash)} {cmt.subject}') - raise ValueError( - f'Unmarked commits {len(bad)}/{len(ser.commits)}') - vals = None - for vals in self.process_series(name, ser, dry_run=dry_run): - if cser_helper.CHANGE_ID_TAG in vals.msg: - lines = vals.msg.splitlines() - updated = [line for line in lines - if not line.startswith(cser_helper.CHANGE_ID_TAG)] - vals.msg = '\n'.join(updated) - - tout.detail(" - removing mark") - vals.info = 'unmarked' - else: - vals.info = 'no mark' - - if dry_run: - tout.info('Dry run completed') - return vals.oid - - def open(self, pwork, name, version): - """Open the patchwork page for a series - - Args: - pwork (Patchwork): Patchwork object to use - name (str): Name of series to open - version (str): Version number to open - """ - ser, version = self._parse_series_and_version(name, version) - link = self.link_get(ser.name, version) - pwork.url = 'https://patchwork.ozlabs.org' - url = self.loop.run_until_complete(pwork.get_series_url(link)) - print(f'Opening {url}') - - # With Firefox, GTK produces lots of warnings, so suppress them - # Gtk-Message: 06:48:20.692: Failed to load module "xapp-gtk3-module" - # Gtk-Message: 06:48:20.692: Not loading module "atk-bridge": The - # functionality is provided by GTK natively. Please try to not load it. - # Gtk-Message: 06:48:20.692: Failed to load module "appmenu-gtk-module" - # Gtk-Message: 06:48:20.692: Failed to load module "appmenu-gtk-module" - # [262145, Main Thread] WARNING: GTK+ module /snap/firefox/5987/ - # gnome-platform/usr/lib/gtk-2.0/modules/libcanberra-gtk-module.so - # cannot be loaded. - # GTK+ 2.x symbols detected. Using GTK+ 2.x and GTK+ 3 in the same - # process # is not supported.: 'glib warning', file /build/firefox/ - # parts/firefox/build/toolkit/xre/nsSigHandlers.cpp:201 - # - # (firefox_firefox:262145): Gtk-WARNING **: 06:48:20.728: GTK+ module - # /snap/firefox/5987/gnome-platform/usr/lib/gtk-2.0/modules/ - # libcanberra-gtk-module.so cannot be loaded. - # GTK+ 2.x symbols detected. Using GTK+ 2.x and GTK+ 3 in the same - # process is not supported. - # Gtk-Message: 06:48:20.728: Failed to load module - # "canberra-gtk-module" - # [262145, Main Thread] WARNING: GTK+ module /snap/firefox/5987/ - # gnome-platform/usr/lib/gtk-2.0/modules/libcanberra-gtk-module.so - # cannot be loaded. - # GTK+ 2.x symbols detected. Using GTK+ 2.x and GTK+ 3 in the same - # process is not supported.: 'glib warning', file /build/firefox/ - # parts/firefox/build/toolkit/xre/nsSigHandlers.cpp:201 - # - # (firefox_firefox:262145): Gtk-WARNING **: 06:48:20.729: GTK+ module - # /snap/firefox/5987/gnome-platform/usr/lib/gtk-2.0/modules/ - # libcanberra-gtk-module.so cannot be loaded. - # GTK+ 2.x symbols detected. Using GTK+ 2.x and GTK+ 3 in the same - # process is not supported. - # Gtk-Message: 06:48:20.729: Failed to load module - # "canberra-gtk-module" - # ATTENTION: default value of option mesa_glthread overridden by - # environment. - cros_subprocess.Popen(['xdg-open', url]) - - def progress(self, series, show_all_versions, list_patches): - """Show progress information for all versions in a series - - Args: - series (str): Name of series to use, or None to show progress for - all series - show_all_versions (bool): True to show all versions of a series, - False to show only the final version - list_patches (bool): True to list all patches for each series, - False to just show the series summary on a single line - """ - with terminal.pager(): - state_totals = defaultdict(int) - if series is not None: - _, _, need_scan = self._progress_one( - self._parse_series(series), show_all_versions, - list_patches, state_totals) - if need_scan: - tout.warning( - 'Inconsistent commit-subject: Please use ' - "'patman series -s <branch> scan' to resolve this") - return - - total_patches = 0 - total_series = 0 - sdict = self.db.series_get_dict() - border = None - total_need_scan = 0 - if not list_patches: - print(self.col.build( - self.col.MAGENTA, - f"{'Name':16} {'Description':41} Count {'Status'}")) - border = f"{'-' * 15} {'-' * 40} ----- {'-' * 15}" - print(border) - for name in sorted(sdict): - ser = sdict[name] - num_series, num_patches, need_scan = self._progress_one( - ser, show_all_versions, list_patches, state_totals) - total_need_scan += need_scan - if list_patches: - print() - total_series += num_series - total_patches += num_patches - if not list_patches: - print(border) - total = f'{total_series} series' - out = '' - for state, freq in state_totals.items(): - out += ' ' + self._build_col(state, f'{freq}:')[0] - if total_need_scan: - out = '*' + out[1:] - - print(f"{total:15} {'':40} {total_patches:5} {out}") - if total_need_scan: - tout.info( - f'Series marked * ({total_need_scan}) have commit ' - 'subjects which mismatch their patches and need to be ' - 'scanned') - - def project_set(self, pwork, name, quiet=False): - """Set the name of the project - - Args: - pwork (Patchwork): Patchwork object to use - name (str): Name of the project to use in patchwork - quiet (bool): True to skip writing the message - """ - res = self.loop.run_until_complete(pwork.get_projects()) - proj_id = None - link_name = None - for proj in res: - if proj['name'] == name: - proj_id = proj['id'] - link_name = proj['link_name'] - if not proj_id: - raise ValueError(f"Unknown project name '{name}'") - self.db.settings_update(name, proj_id, link_name) - self.commit() - if not quiet: - tout.info(f"Project '{name}' patchwork-ID {proj_id} " - f'link-name {link_name}') - - def project_get(self): - """Get the details of the project - - Returns: - tuple or None if there are no settings: - name (str): Project name, e.g. 'U-Boot' - proj_id (int): Patchworks project ID for this project - link_name (str): Patchwork's link-name for the project - """ - return self.db.settings_get() - - def remove(self, name, dry_run=False): - """Remove a series from the database - - Args: - name (str): Name of series to remove, or None to use current one - dry_run (bool): True to do a dry run - """ - ser = self._parse_series(name) - name = ser.name - if not ser.idnum: - raise ValueError(f"No such series '{name}'") - - self.db.ser_ver_remove(ser.idnum, None) - if not dry_run: - self.commit() - else: - self.rollback() - - self.commit() - tout.info(f"Removed series '{name}'") - if dry_run: - tout.info('Dry run completed') - - def rename(self, series, name, dry_run=False): - """Rename a series - - Renames a series and changes the name of any branches which match - versions present in the database - - Args: - series (str): Name of series to use, or None to use current branch - name (str): new name to use (must not include version number) - dry_run (bool): True to do a dry run - """ - old_ser, _ = self._parse_series_and_version(series, None) - if not old_ser.idnum: - raise ValueError(f"Series '{old_ser.name}' not found in database") - if old_ser.name != series: - raise ValueError(f"Invalid series name '{series}': " - 'did you use the branch name?') - chk, _ = cser_helper.split_name_version(name) - if chk != name: - raise ValueError( - f"Invalid series name '{name}': did you use the branch name?") - if chk == old_ser.name: - raise ValueError( - f"Cannot rename series '{old_ser.name}' to itself") - if self.get_series_by_name(name): - raise ValueError(f"Cannot rename: series '{name}' already exists") - - versions = self._get_version_list(old_ser.idnum) - missing = [] - exists = [] - todo = {} - for ver in versions: - ok = True - old_branch = self._get_branch_name(old_ser.name, ver) - if not gitutil.check_branch(old_branch, self.gitdir): - missing.append(old_branch) - ok = False - - branch = self._get_branch_name(name, ver) - if gitutil.check_branch(branch, self.gitdir): - exists.append(branch) - ok = False - - if ok: - todo[ver] = [old_branch, branch] - - if missing or exists: - msg = 'Cannot rename' - if missing: - msg += f": branches missing: {', '.join(missing)}" - if exists: - msg += f": branches exist: {', '.join(exists)}" - raise ValueError(msg) - - for old_branch, branch in todo.values(): - tout.info(f"Renaming branch '{old_branch}' to '{branch}'") - if not dry_run: - gitutil.rename_branch(old_branch, branch, self.gitdir) - - # Change the series name; nothing needs to change in ser_ver - self.db.series_set_name(old_ser.idnum, name) - - if not dry_run: - self.commit() - else: - self.rollback() - - tout.info(f"Renamed series '{series}' to '{name}'") - if dry_run: - tout.info('Dry run completed') - - def scan(self, branch_name, mark=False, allow_unmarked=False, end=None, - dry_run=False): - """Scan a branch and make updates to the database if it has changed - - Args: - branch_name (str): Name of branch to sync, or None for current one - mark (str): True to mark each commit with a change ID - allow_unmarked (str): True to not require each commit to be marked - end (str): Add only commits up to but exclu - dry_run (bool): True to do a dry run - """ - def _show_item(oper, seq, subject): - col = None - if oper == '+': - col = self.col.GREEN - elif oper == '-': - col = self.col.RED - out = self.col.build(col, subject) if col else subject - tout.info(f'{oper} {seq:3} {out}') - - name, ser, version, msg = self.prep_series(branch_name, end) - svid = self.get_ser_ver(ser.idnum, version).idnum - pcdict = self.get_pcommit_dict(svid) - - tout.info( - f"Syncing series '{name}' v{version}: mark {mark} " - f'allow_unmarked {allow_unmarked}') - if msg: - tout.info(msg) - - ser = self._handle_mark(name, ser, version, mark, allow_unmarked, - False, dry_run) - - # First check for new patches that are not in the database - to_add = dict(enumerate(ser.commits)) - for pcm in pcdict.values(): - tout.debug(f'pcm {pcm.subject}') - i = self._find_matched_commit(to_add, pcm) - if i is not None: - del to_add[i] - - # Now check for patches in the database that are not in the branch - to_remove = dict(enumerate(pcdict.values())) - for cmt in ser.commits: - tout.debug(f'cmt {cmt.subject}') - i = self._find_matched_patch(to_remove, cmt) - if i is not None: - del to_remove[i] - - for seq, cmt in enumerate(ser.commits): - if seq in to_remove: - _show_item('-', seq, to_remove[seq].subject) - del to_remove[seq] - if seq in to_add: - _show_item('+', seq, to_add[seq].subject) - del to_add[seq] - else: - _show_item(' ', seq, cmt.subject) - seq = len(ser.commits) - for cmt in to_add.items(): - _show_item('+', seq, cmt.subject) - seq += 1 - for seq, pcm in to_remove.items(): - _show_item('+', seq, pcm.subject) - - self.db.pcommit_delete(svid) - self._add_series_commits(ser, svid) - if not dry_run: - self.commit() - else: - self.rollback() - tout.info('Dry run completed') - - def send(self, pwork, name, autolink, autolink_wait, args): - """Send out a series - - Args: - pwork (Patchwork): Patchwork object to use - name (str): Series name to search for, or None for current series - that is checked out - autolink (bool): True to auto-link the series after sending - args (argparse.Namespace): 'send' arguments provided - autolink_wait (int): Number of seconds to wait for the autolink to - succeed - """ - ser, version = self._parse_series_and_version(name, None) - if not ser.idnum: - raise ValueError(f"Series '{ser.name}' not found in database") - - args.branch = self._get_branch_name(ser.name, version) - likely_sent = send.send(args, git_dir=self.gitdir, cwd=self.topdir) - - if likely_sent and autolink: - print(f'Autolinking with Patchwork ({autolink_wait} seconds)') - self.link_auto(pwork, name, version, True, wait_s=autolink_wait) - - def archive(self, series): - """Archive a series - - Args: - series (str): Name of series to use, or None to use current branch - """ - ser = self._parse_series(series, include_archived=True) - if not ser.idnum: - raise ValueError(f"Series '{ser.name}' not found in database") - - svlist = self.db.ser_ver_get_for_series(ser.idnum) - - # Figure out the tags we will create - tag_info = {} - now = self.get_now() - now_str = now.strftime('%d%b%y').lower() - for svi in svlist: - name = self._get_branch_name(ser.name, svi.version) - if not gitutil.check_branch(name, git_dir=self.gitdir): - raise ValueError(f"No branch named '{name}'") - tag_info[svi.version] = [svi.idnum, name, f'{name}-{now_str}'] - - # Create the tags - repo = pygit2.Repository(self.gitdir) - for _, (idnum, name, tag_name) in tag_info.items(): - commit = repo.revparse_single(name) - repo.create_tag(tag_name, commit.hex, - pygit2.enums.ObjectType.COMMIT, - commit.author, commit.message) - - # Update the database - for idnum, name, tag_name in tag_info.values(): - self.db.ser_ver_set_archive_tag(idnum, tag_name) - - # Delete the branches - for idnum, name, tag_name in tag_info.values(): - # Detach HEAD from the branch if pointing to this branch - commit = repo.revparse_single(name) - if repo.head.target == commit.oid: - repo.set_head(commit.oid) - - repo.branches.delete(name) - - self.db.series_set_archived(ser.idnum, True) - self.commit() - - def unarchive(self, series): - """Unarchive a series - - Args: - series (str): Name of series to use, or None to use current branch - """ - ser = self._parse_series(series, include_archived=True) - if not ser.idnum: - raise ValueError(f"Series '{ser.name}' not found in database") - self.db.series_set_archived(ser.idnum, False) - - svlist = self.db.ser_ver_get_for_series(ser.idnum) - - # Collect the tags - repo = pygit2.Repository(self.gitdir) - tag_info = {} - for svi in svlist: - name = self._get_branch_name(ser.name, svi.version) - target = repo.revparse_single(svi.archive_tag) - tag_info[svi.idnum] = name, svi.archive_tag, target - - # Make sure the branches don't exist - for name, tag_name, tag in tag_info.values(): - if name in repo.branches: - raise ValueError( - f"Cannot restore branch '{name}': already exists") - - # Recreate the branches - for name, tag_name, tag in tag_info.values(): - target = repo.get(tag.target) - repo.branches.create(name, target) - - # Delete the tags - for name, tag_name, tag in tag_info.values(): - repo.references.delete(f'refs/tags/{tag_name}') - - # Update the database - for idnum, (name, tag_name, tag) in tag_info.items(): - self.db.ser_ver_set_archive_tag(idnum, None) - - self.commit() - - def status(self, pwork, series, version, show_comments, - show_cover_comments=False): - """Show the series status from patchwork - - Args: - pwork (Patchwork): Patchwork object to use - series (str): Name of series to use, or None to use current branch - version (int): Version number, or None to detect from name - show_comments (bool): Show all comments on each patch - show_cover_comments (bool): Show all comments on the cover letter - """ - branch, series, version, _, _, link, _, _ = self._get_patches( - series, version) - if not link: - raise ValueError( - f"Series '{series.name}' v{version} has no patchwork link: " - f"Try 'patman series -s {branch} autolink'") - status.check_and_show_status( - series, link, branch, None, False, show_comments, - show_cover_comments, pwork, self.gitdir) - - def summary(self, series): - """Show summary information for all series - - Args: - series (str): Name of series to use - """ - print(f"{'Name':17} Status Description") - print(f"{'-' * 17} {'-' * 6} {'-' * 30}") - if series is not None: - self._summary_one(self._parse_series(series)) - return - - sdict = self.db.series_get_dict() - for ser in sdict.values(): - self._summary_one(ser) - - def gather(self, pwork, series, version, show_comments, - show_cover_comments, gather_tags, dry_run=False): - """Gather any new tags from Patchwork, optionally showing comments - - Args: - pwork (Patchwork): Patchwork object to use - series (str): Name of series to use, or None to use current branch - version (int): Version number, or None to detect from name - show_comments (bool): True to show the comments on each patch - show_cover_comments (bool): True to show the comments on the cover - letter - gather_tags (bool): True to gather review/test tags - dry_run (bool): True to do a dry run (database is not updated) - """ - ser, version = self._parse_series_and_version(series, version) - self._ensure_version(ser, version) - svid, link = self._get_series_svid_link(ser.idnum, version) - if not link: - raise ValueError( - "No patchwork link is available: use 'patman series autolink'") - tout.info( - f"Updating series '{ser.name}' version {version} " - f"from link '{link}'") - - loop = asyncio.get_event_loop() - with pwork.collect_stats() as stats: - cover, patches = loop.run_until_complete(self._gather( - pwork, link, show_cover_comments)) - - with terminal.pager(): - updated, updated_cover = self._sync_one( - svid, ser.name, version, show_comments, show_cover_comments, - gather_tags, cover, patches, dry_run) - tout.info(f"{updated} patch{'es' if updated != 1 else ''}" - f"{' and cover letter' if updated_cover else ''} " - f'updated ({stats.request_count} requests)') - - if not dry_run: - self.commit() - else: - self.rollback() - tout.info('Dry run completed') - - def gather_all(self, pwork, show_comments, show_cover_comments, - sync_all_versions, gather_tags, dry_run=False): - to_fetch, missing = self._get_fetch_dict(sync_all_versions) - - loop = asyncio.get_event_loop() - result, requests = loop.run_until_complete(self._do_series_sync_all( - pwork, to_fetch)) - - with terminal.pager(): - tot_updated = 0 - tot_cover = 0 - add_newline = False - for (svid, sync), (cover, patches) in zip(to_fetch.items(), - result): - if add_newline: - tout.info('') - tout.info(f"Syncing '{sync.series_name}' v{sync.version}") - updated, updated_cover = self._sync_one( - svid, sync.series_name, sync.version, show_comments, - show_cover_comments, gather_tags, cover, patches, dry_run) - tot_updated += updated - tot_cover += updated_cover - add_newline = gather_tags - - tout.info('') - tout.info( - f"{tot_updated} patch{'es' if tot_updated != 1 else ''} and " - f"{tot_cover} cover letter{'s' if tot_cover != 1 else ''} " - f'updated, {missing} missing ' - f"link{'s' if missing != 1 else ''} ({requests} requests)") - if not dry_run: - self.commit() - else: - self.rollback() - tout.info('Dry run completed') - - def upstream_add(self, name, url): - """Add a new upstream tree - - Args: - name (str): Name of the tree - url (str): URL for the tree - """ - self.db.upstream_add(name, url) - self.commit() - - def upstream_list(self): - """List the upstream repos - - Shows a list of the repos, obtained from the database - """ - udict = self.get_upstream_dict() - - for name, items in udict.items(): - url, is_default = items - default = 'default' if is_default else '' - print(f'{name:15.15} {default:8} {url}') - - def upstream_set_default(self, name): - """Set the default upstream target - - Args: - name (str): Name of the upstream remote to set as default, or None - for none - """ - self.db.upstream_set_default(name) - self.commit() - - def upstream_get_default(self): - """Get the default upstream target - - Return: - str: Name of the upstream remote to set as default, or None if none - """ - return self.db.upstream_get_default() - - def upstream_delete(self, name): - """Delete an upstream target - - Args: - name (str): Name of the upstream remote to delete - """ - self.db.upstream_delete(name) - self.commit() - - def version_remove(self, name, version, dry_run=False): - """Remove a version of a series from the database - - Args: - name (str): Name of series to remove, or None to use current one - version (int): Version number to remove - dry_run (bool): True to do a dry run - """ - ser, version = self._parse_series_and_version(name, version) - name = ser.name - - versions = self._ensure_version(ser, version) - - if versions == [version]: - raise ValueError( - f"Series '{ser.name}' only has one version: remove the series") - - self.db.ser_ver_remove(ser.idnum, version) - if not dry_run: - self.commit() - else: - self.rollback() - - tout.info(f"Removed version {version} from series '{name}'") - if dry_run: - tout.info('Dry run completed') - - def version_change(self, name, version, new_version, dry_run=False): - """Change a version of a series to be a different version - - Args: - name (str): Name of series to remove, or None to use current one - version (int): Version number to change - new_version (int): New version - dry_run (bool): True to do a dry run - """ - ser, version = self._parse_series_and_version(name, version) - name = ser.name - - versions = self._ensure_version(ser, version) - vstr = list(map(str, versions)) - if version not in versions: - raise ValueError( - f"Series '{ser.name}' does not have v{version}: " - f"{' '.join(vstr)}") - - if not new_version: - raise ValueError('Please provide a new version number') - - if new_version in versions: - raise ValueError( - f"Series '{ser.name}' already has a v{new_version}: " - f"{' '.join(vstr)}") - - new_name = self._join_name_version(ser.name, new_version) - - svid = self.get_series_svid(ser.idnum, version) - pwc = self.get_pcommit_dict(svid) - count = len(pwc.values()) - series = patchstream.get_metadata(name, 0, count, git_dir=self.gitdir) - - self.update_series(name, series, version, new_name, dry_run, - add_vers=new_version, switch=True) - self.db.ser_ver_set_version(svid, new_version) - - if not dry_run: - self.commit() - else: - self.rollback() - - tout.info(f"Changed version {version} in series '{ser.name}' " - f"to {new_version} named '{new_name}'") - if dry_run: - tout.info('Dry run completed') diff --git a/tools/patman/database.py b/tools/patman/database.py deleted file mode 100644 index 9c25b04a720..00000000000 --- a/tools/patman/database.py +++ /dev/null @@ -1,823 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2025 Simon Glass <[email protected]> -# -"""Handles the patman database - -This uses sqlite3 with a local file. - -To adjsut the schema, increment LATEST, create a migrate_to_v<x>() function -and write some code in migrate_to() to call it. -""" - -from collections import namedtuple, OrderedDict -import os -import sqlite3 - -from u_boot_pylib import tools -from u_boot_pylib import tout -from patman.series import Series - -# Schema version (version 0 means there is no database yet) -LATEST = 4 - -# Information about a series/version record -SerVer = namedtuple( - 'SER_VER', - 'idnum,series_id,version,link,cover_id,cover_num_comments,name,' - 'archive_tag') - -# Record from the pcommit table: -# idnum (int): record ID -# seq (int): Patch sequence in series (0 is first) -# subject (str): patch subject -# svid (int): ID of series/version record in ser_ver table -# change_id (str): Change-ID value -# state (str): Current status in patchwork -# patch_id (int): Patchwork's patch ID for this patch -# num_comments (int): Number of comments attached to the commit -Pcommit = namedtuple( - 'PCOMMIT', - 'idnum,seq,subject,svid,change_id,state,patch_id,num_comments') - - -class Database: - """Database of information used by patman""" - - # dict of databases: - # key: filename - # value: Database object - instances = {} - - def __init__(self, db_path): - """Set up a new database object - - Args: - db_path (str): Path to the database - """ - if db_path in Database.instances: - # Two connections to the database can cause: - # sqlite3.OperationalError: database is locked - raise ValueError(f"There is already a database for '{db_path}'") - self.con = None - self.cur = None - self.db_path = db_path - self.is_open = False - Database.instances[db_path] = self - - @staticmethod - def get_instance(db_path): - """Get the database instance for a path - - This is provides to ensure that different callers can obtain the - same database object when accessing the same database file. - - Args: - db_path (str): Path to the database - - Return: - Database: Database instance, which is created if necessary - """ - db = Database.instances.get(db_path) - if db: - return db, False - return Database(db_path), True - - def start(self): - """Open the database read for use, migrate to latest schema""" - self.open_it() - self.migrate_to(LATEST) - - def open_it(self): - """Open the database, creating it if necessary""" - if self.is_open: - raise ValueError('Already open') - if not os.path.exists(self.db_path): - tout.warning(f'Creating new database {self.db_path}') - self.con = sqlite3.connect(self.db_path) - self.cur = self.con.cursor() - self.is_open = True - - def close(self): - """Close the database""" - if not self.is_open: - raise ValueError('Already closed') - self.con.close() - self.cur = None - self.con = None - self.is_open = False - - def create_v1(self): - """Create a database with the v1 schema""" - self.cur.execute( - 'CREATE TABLE series (id INTEGER PRIMARY KEY AUTOINCREMENT,' - 'name UNIQUE, desc, archived BIT)') - - # Provides a series_id/version pair, which is used to refer to a - # particular series version sent to patchwork. This stores the link - # to patchwork - self.cur.execute( - 'CREATE TABLE ser_ver (id INTEGER PRIMARY KEY AUTOINCREMENT,' - 'series_id INTEGER, version INTEGER, link,' - 'FOREIGN KEY (series_id) REFERENCES series (id))') - - self.cur.execute( - 'CREATE TABLE upstream (name UNIQUE, url, is_default BIT)') - - # change_id is the Change-Id - # patch_id is the ID of the patch on the patchwork server - self.cur.execute( - 'CREATE TABLE pcommit (id INTEGER PRIMARY KEY AUTOINCREMENT,' - 'svid INTEGER, seq INTEGER, subject, patch_id INTEGER, ' - 'change_id, state, num_comments INTEGER, ' - 'FOREIGN KEY (svid) REFERENCES ser_ver (id))') - - self.cur.execute( - 'CREATE TABLE settings (name UNIQUE, proj_id INT, link_name)') - - def _migrate_to_v2(self): - """Add a schema_version table""" - self.cur.execute('CREATE TABLE schema_version (version INTEGER)') - - def _migrate_to_v3(self): - """Store the number of cover-letter comments in the schema""" - self.cur.execute('ALTER TABLE ser_ver ADD COLUMN cover_id') - self.cur.execute('ALTER TABLE ser_ver ADD COLUMN cover_num_comments ' - 'INTEGER') - self.cur.execute('ALTER TABLE ser_ver ADD COLUMN name') - - def _migrate_to_v4(self): - """Add an archive tag for each ser_ver""" - self.cur.execute('ALTER TABLE ser_ver ADD COLUMN archive_tag') - - def migrate_to(self, dest_version): - """Migrate the database to the selected version - - Args: - dest_version (int): Version to migrate to - """ - while True: - version = self.get_schema_version() - if version == dest_version: - break - - self.close() - tools.write_file(f'{self.db_path}old.v{version}', - tools.read_file(self.db_path)) - - version += 1 - tout.info(f'Update database to v{version}') - self.open_it() - if version == 1: - self.create_v1() - elif version == 2: - self._migrate_to_v2() - elif version == 3: - self._migrate_to_v3() - elif version == 4: - self._migrate_to_v4() - - # Save the new version if we have a schema_version table - if version > 1: - self.cur.execute('DELETE FROM schema_version') - self.cur.execute( - 'INSERT INTO schema_version (version) VALUES (?)', - (version,)) - self.commit() - - def get_schema_version(self): - """Get the version of the database's schema - - Return: - int: Database version, 0 means there is no data; anything less than - LATEST means the schema is out of date and must be updated - """ - # If there is no database at all, assume v0 - version = 0 - try: - self.cur.execute('SELECT name FROM series') - except sqlite3.OperationalError: - return 0 - - # If there is no schema, assume v1 - try: - self.cur.execute('SELECT version FROM schema_version') - version = self.cur.fetchone()[0] - except sqlite3.OperationalError: - return 1 - return version - - def execute(self, query, parameters=()): - """Execute a database query - - Args: - query (str): Query string - parameters (list of values): Parameters to pass - - Return: - - """ - return self.cur.execute(query, parameters) - - def commit(self): - """Commit changes to the database""" - self.con.commit() - - def rollback(self): - """Roll back changes to the database""" - self.con.rollback() - - def lastrowid(self): - """Get the last row-ID reported by the database - - Return: - int: Value for lastrowid - """ - return self.cur.lastrowid - - def rowcount(self): - """Get the row-count reported by the database - - Return: - int: Value for rowcount - """ - return self.cur.rowcount - - def _get_series_list(self, include_archived): - """Get a list of Series objects from the database - - Args: - include_archived (bool): True to include archives series - - Return: - list of Series - """ - res = self.execute( - 'SELECT id, name, desc FROM series ' + - ('WHERE archived = 0' if not include_archived else '')) - return [Series.from_fields(idnum=idnum, name=name, desc=desc) - for idnum, name, desc in res.fetchall()] - - # series functions - - def series_get_dict_by_id(self, include_archived=False): - """Get a dict of Series objects from the database - - Args: - include_archived (bool): True to include archives series - - Return: - OrderedDict: - key: series ID - value: Series with idnum, name and desc filled out - """ - sdict = OrderedDict() - for ser in self._get_series_list(include_archived): - sdict[ser.idnum] = ser - return sdict - - def series_find_by_name(self, name, include_archived=False): - """Find a series and return its details - - Args: - name (str): Name to search for - include_archived (bool): True to include archives series - - Returns: - idnum, or None if not found - """ - res = self.execute( - 'SELECT id FROM series WHERE name = ?' + - ('AND archived = 0' if not include_archived else ''), (name,)) - recs = res.fetchall() - - # This shouldn't happen - assert len(recs) <= 1, 'Expected one match, but multiple found' - - if len(recs) != 1: - return None - return recs[0][0] - - def series_get_info(self, idnum): - """Get information for a series from the database - - Args: - idnum (int): Series ID to look up - - Return: tuple: - str: Series name - str: Series description - - Raises: - ValueError: Series is not found - """ - res = self.execute('SELECT name, desc FROM series WHERE id = ?', - (idnum,)) - recs = res.fetchall() - if len(recs) != 1: - raise ValueError(f'No series found (id {idnum} len {len(recs)})') - return recs[0] - - def series_get_dict(self, include_archived=False): - """Get a dict of Series objects from the database - - Args: - include_archived (bool): True to include archives series - - Return: - OrderedDict: - key: series name - value: Series with idnum, name and desc filled out - """ - sdict = OrderedDict() - for ser in self._get_series_list(include_archived): - sdict[ser.name] = ser - return sdict - - def series_get_version_list(self, series_idnum): - """Get a list of the versions available for a series - - Args: - series_idnum (int): ID of series to look up - - Return: - str: List of versions, which may be empty if the series is in the - process of being added - """ - res = self.execute('SELECT version FROM ser_ver WHERE series_id = ?', - (series_idnum,)) - return [x[0] for x in res.fetchall()] - - def series_get_max_version(self, series_idnum): - """Get the highest version number available for a series - - Args: - series_idnum (int): ID of series to look up - - Return: - int: Maximum version number - """ - res = self.execute( - 'SELECT MAX(version) FROM ser_ver WHERE series_id = ?', - (series_idnum,)) - return res.fetchall()[0][0] - - def series_get_all_max_versions(self): - """Find the latest version of all series - - Return: list of: - int: ser_ver ID - int: series ID - int: Maximum version - """ - res = self.execute( - 'SELECT id, series_id, MAX(version) FROM ser_ver ' - 'GROUP BY series_id') - return res.fetchall() - - def series_add(self, name, desc): - """Add a new series record - - The new record is set to not archived - - Args: - name (str): Series name - desc (str): Series description - - Return: - int: ID num of the new series record - """ - self.execute( - 'INSERT INTO series (name, desc, archived) ' - f"VALUES ('{name}', '{desc}', 0)") - return self.lastrowid() - - def series_remove(self, idnum): - """Remove a series from the database - - The series must exist - - Args: - idnum (int): ID num of series to remove - """ - self.execute('DELETE FROM series WHERE id = ?', (idnum,)) - assert self.rowcount() == 1 - - def series_remove_by_name(self, name): - """Remove a series from the database - - Args: - name (str): Name of series to remove - - Raises: - ValueError: Series does not exist (database is rolled back) - """ - self.execute('DELETE FROM series WHERE name = ?', (name,)) - if self.rowcount() != 1: - self.rollback() - raise ValueError(f"No such series '{name}'") - - def series_set_archived(self, series_idnum, archived): - """Update archive flag for a series - - Args: - series_idnum (int): ID num of the series - archived (bool): Whether to mark the series as archived or - unarchived - """ - self.execute( - 'UPDATE series SET archived = ? WHERE id = ?', - (archived, series_idnum)) - - def series_set_name(self, series_idnum, name): - """Update name for a series - - Args: - series_idnum (int): ID num of the series - name (str): new name to use - """ - self.execute( - 'UPDATE series SET name = ? WHERE id = ?', (name, series_idnum)) - - # ser_ver functions - - def ser_ver_get_link(self, series_idnum, version): - """Get the link for a series version - - Args: - series_idnum (int): ID num of the series - version (int): Version number to search for - - Return: - str: Patchwork link as a string, e.g. '12325', or None if none - - Raises: - ValueError: Multiple matches are found - """ - res = self.execute( - 'SELECT link FROM ser_ver WHERE ' - f"series_id = {series_idnum} AND version = '{version}'") - recs = res.fetchall() - if not recs: - return None - if len(recs) > 1: - raise ValueError('Expected one match, but multiple matches found') - return recs[0][0] - - def ser_ver_set_link(self, series_idnum, version, link): - """Set the link for a series version - - Args: - series_idnum (int): ID num of the series - version (int): Version number to search for - link (str): Patchwork link for the ser_ver - - Return: - bool: True if the record was found and updated, else False - """ - if link is None: - link = '' - self.execute( - 'UPDATE ser_ver SET link = ? WHERE series_id = ? AND version = ?', - (str(link), series_idnum, version)) - return self.rowcount() != 0 - - def ser_ver_set_info(self, info): - """Set the info for a series version - - Args: - info (SER_VER): Info to set. Only two options are supported: - 1: svid,cover_id,cover_num_comments,name - 2: svid,name - - Return: - bool: True if the record was found and updated, else False - """ - assert info.idnum is not None - if info.cover_id: - assert info.series_id is None - self.execute( - 'UPDATE ser_ver SET cover_id = ?, cover_num_comments = ?, ' - 'name = ? WHERE id = ?', - (info.cover_id, info.cover_num_comments, info.name, - info.idnum)) - else: - assert not info.cover_id - assert not info.cover_num_comments - assert not info.series_id - assert not info.version - assert not info.link - self.execute('UPDATE ser_ver SET name = ? WHERE id = ?', - (info.name, info.idnum)) - - return self.rowcount() != 0 - - def ser_ver_set_version(self, svid, version): - """Sets the version for a ser_ver record - - Args: - svid (int): Record ID to update - version (int): Version number to add - - Raises: - ValueError: svid was not found - """ - self.execute( - 'UPDATE ser_ver SET version = ? WHERE id = ?', (version, svid)) - if self.rowcount() != 1: - raise ValueError(f'No ser_ver updated (svid {svid})') - - def ser_ver_set_archive_tag(self, svid, tag): - """Sets the archive tag for a ser_ver record - - Args: - svid (int): Record ID to update - tag (tag): Tag to add - - Raises: - ValueError: svid was not found - """ - self.execute( - 'UPDATE ser_ver SET archive_tag = ? WHERE id = ?', (tag, svid)) - if self.rowcount() != 1: - raise ValueError(f'No ser_ver updated (svid {svid})') - - def ser_ver_add(self, series_idnum, version, link=None): - """Add a new ser_ver record - - Args: - series_idnum (int): ID num of the series which is getting a new - version - version (int): Version number to add - link (str): Patchwork link, or None if not known - - Return: - int: ID num of the new ser_ver record - """ - self.execute( - 'INSERT INTO ser_ver (series_id, version, link) VALUES (?, ?, ?)', - (series_idnum, version, link)) - return self.lastrowid() - - def ser_ver_get_for_series(self, series_idnum, version=None): - """Get a list of ser_ver records for a given series ID - - Args: - series_idnum (int): ID num of the series to search - version (int): Version number to search for, or None for all - - Return: - SER_VER: Requested information - - Raises: - ValueError: There is no matching idnum/version - """ - base = ('SELECT id, series_id, version, link, cover_id, ' - 'cover_num_comments, name, archive_tag FROM ser_ver ' - 'WHERE series_id = ?') - if version: - res = self.execute(base + ' AND version = ?', - (series_idnum, version)) - else: - res = self.execute(base, (series_idnum,)) - recs = res.fetchall() - if not recs: - raise ValueError( - f'No matching series for id {series_idnum} version {version}') - if version: - return SerVer(*recs[0]) - return [SerVer(*x) for x in recs] - - def ser_ver_get_ids_for_series(self, series_idnum, version=None): - """Get a list of ser_ver records for a given series ID - - Args: - series_idnum (int): ID num of the series to search - version (int): Version number to search for, or None for all - - Return: - list of int: List of svids for the matching records - """ - if version: - res = self.execute( - 'SELECT id FROM ser_ver WHERE series_id = ? AND version = ?', - (series_idnum, version)) - else: - res = self.execute( - 'SELECT id FROM ser_ver WHERE series_id = ?', (series_idnum,)) - return list(res.fetchall()[0]) - - def ser_ver_get_list(self): - """Get a list of patchwork entries from the database - - Return: - list of SER_VER - """ - res = self.execute( - 'SELECT id, series_id, version, link, cover_id, ' - 'cover_num_comments, name, archive_tag FROM ser_ver') - items = res.fetchall() - return [SerVer(*x) for x in items] - - def ser_ver_remove(self, series_idnum, version=None, remove_pcommits=True, - remove_series=True): - """Delete a ser_ver record - - Removes the record which has the given series ID num and version - - Args: - series_idnum (int): ID num of the series - version (int): Version number, or None to remove all versions - remove_pcommits (bool): True to remove associated pcommits too - remove_series (bool): True to remove the series if versions is None - """ - if remove_pcommits: - # Figure out svids to delete - svids = self.ser_ver_get_ids_for_series(series_idnum, version) - - self.pcommit_delete_list(svids) - - if version: - self.execute( - 'DELETE FROM ser_ver WHERE series_id = ? AND version = ?', - (series_idnum, version)) - else: - self.execute( - 'DELETE FROM ser_ver WHERE series_id = ?', - (series_idnum,)) - if not version and remove_series: - self.series_remove(series_idnum) - - # pcommit functions - - def pcommit_get_list(self, find_svid=None): - """Get a dict of pcommits entries from the database - - Args: - find_svid (int): If not None, finds the records associated with a - particular series and version; otherwise returns all records - - Return: - list of PCOMMIT: pcommit records - """ - query = ('SELECT id, seq, subject, svid, change_id, state, patch_id, ' - 'num_comments FROM pcommit') - if find_svid is not None: - query += f' WHERE svid = {find_svid}' - res = self.execute(query) - return [Pcommit(*rec) for rec in res.fetchall()] - - def pcommit_add_list(self, svid, pcommits): - """Add records to the pcommit table - - Args: - svid (int): ser_ver ID num - pcommits (list of PCOMMIT): Only seq, subject, change_id are - uses; svid comes from the argument passed in and the others - are assumed to be obtained from patchwork later - """ - for pcm in pcommits: - self.execute( - 'INSERT INTO pcommit (svid, seq, subject, change_id) VALUES ' - '(?, ?, ?, ?)', (svid, pcm.seq, pcm.subject, pcm.change_id)) - - def pcommit_delete(self, svid): - """Delete pcommit records for a given ser_ver ID - - Args_: - svid (int): ser_ver ID num of records to delete - """ - self.execute('DELETE FROM pcommit WHERE svid = ?', (svid,)) - - def pcommit_delete_list(self, svid_list): - """Delete pcommit records for a given set of ser_ver IDs - - Args_: - svid (list int): ser_ver ID nums of records to delete - """ - vals = ', '.join([str(x) for x in svid_list]) - self.execute('DELETE FROM pcommit WHERE svid IN (?)', (vals,)) - - def pcommit_update(self, pcm): - """Update a pcommit record - - Args: - pcm (PCOMMIT): Information to write; only the idnum, state, - patch_id and num_comments are used - - Return: - True if the data was written - """ - self.execute( - 'UPDATE pcommit SET ' - 'patch_id = ?, state = ?, num_comments = ? WHERE id = ?', - (pcm.patch_id, pcm.state, pcm.num_comments, pcm.idnum)) - return self.rowcount() > 0 - - # upstream functions - - def upstream_add(self, name, url): - """Add a new upstream record - - Args: - name (str): Name of the tree - url (str): URL for the tree - - Raises: - ValueError if the name already exists in the database - """ - try: - self.execute( - 'INSERT INTO upstream (name, url) VALUES (?, ?)', (name, url)) - except sqlite3.IntegrityError as exc: - if 'UNIQUE constraint failed: upstream.name' in str(exc): - raise ValueError(f"Upstream '{name}' already exists") from exc - - def upstream_set_default(self, name): - """Mark (only) the given upstream as the default - - Args: - name (str): Name of the upstream remote to set as default, or None - - Raises: - ValueError if more than one name matches (should not happen); - database is rolled back - """ - self.execute("UPDATE upstream SET is_default = 0") - if name is not None: - self.execute( - 'UPDATE upstream SET is_default = 1 WHERE name = ?', (name,)) - if self.rowcount() != 1: - self.rollback() - raise ValueError(f"No such upstream '{name}'") - - def upstream_get_default(self): - """Get the name of the default upstream - - Return: - str: Default-upstream name, or None if there is no default - """ - res = self.execute( - "SELECT name FROM upstream WHERE is_default = 1") - recs = res.fetchall() - if len(recs) != 1: - return None - return recs[0][0] - - def upstream_delete(self, name): - """Delete an upstream target - - Args: - name (str): Name of the upstream remote to delete - - Raises: - ValueError: Upstream does not exist (database is rolled back) - """ - self.execute(f"DELETE FROM upstream WHERE name = '{name}'") - if self.rowcount() != 1: - self.rollback() - raise ValueError(f"No such upstream '{name}'") - - def upstream_get_dict(self): - """Get a list of upstream entries from the database - - Return: - OrderedDict: - key (str): upstream name - value (str): url - """ - res = self.execute('SELECT name, url, is_default FROM upstream') - udict = OrderedDict() - for name, url, is_default in res.fetchall(): - udict[name] = url, is_default - return udict - - # settings functions - - def settings_update(self, name, proj_id, link_name): - """Set the patchwork settings of the project - - Args: - name (str): Name of the project to use in patchwork - proj_id (int): Project ID for the project - link_name (str): Link name for the project - """ - self.execute('DELETE FROM settings') - self.execute( - 'INSERT INTO settings (name, proj_id, link_name) ' - 'VALUES (?, ?, ?)', (name, proj_id, link_name)) - - def settings_get(self): - """Get the patchwork settings of the project - - Returns: - tuple or None if there are no settings: - name (str): Project name, e.g. 'U-Boot' - proj_id (int): Patchworks project ID for this project - link_name (str): Patchwork's link-name for the project - """ - res = self.execute("SELECT name, proj_id, link_name FROM settings") - recs = res.fetchall() - if len(recs) != 1: - return None - return recs[0] diff --git a/tools/patman/func_test.py b/tools/patman/func_test.py deleted file mode 100644 index d029181765c..00000000000 --- a/tools/patman/func_test.py +++ /dev/null @@ -1,1342 +0,0 @@ -# -*- coding: utf-8 -*- -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2017 Google, Inc -# - -"""Functional tests for checking that patman behaves correctly""" - -import asyncio -import contextlib -import os -import pathlib -import re -import shutil -import sys -import unittest - -import pygit2 - -from u_boot_pylib import command -from u_boot_pylib import gitutil -from u_boot_pylib import terminal -from u_boot_pylib import tools - -from patman.commit import Commit -from patman import control -from patman import patchstream -from patman.patchstream import PatchStream -from patman import patchwork -from patman import send -from patman.series import Series -from patman import status -from patman.test_common import TestCommon - -PATMAN_DIR = pathlib.Path(__file__).parent -TEST_DATA_DIR = PATMAN_DIR / 'test/' - - -def directory_excursion(directory): - """Change directory to `directory` for a limited to the context block.""" - current = os.getcwd() - try: - os.chdir(directory) - yield - finally: - os.chdir(current) - - -class TestFunctional(unittest.TestCase, TestCommon): - """Functional tests for checking that patman behaves correctly""" - fred = 'Fred Bloggs <[email protected]>' - joe = 'Joe Bloggs <[email protected]>' - mary = 'Mary Bloggs <[email protected]>' - commits = None - patches = None - - def setUp(self): - TestCommon.setUp(self) - self.repo = None - self._patman_pathname = sys.argv[0] - self._patman_dir = os.path.dirname(os.path.realpath(sys.argv[0])) - - def tearDown(self): - TestCommon.tearDown(self) - - @staticmethod - def _get_path(fname): - """Get the path to a test file - - Args: - fname (str): Filename to obtain - - Returns: - str: Full path to file in the test directory - """ - return TEST_DATA_DIR / fname - - @classmethod - def _get_text(cls, fname): - """Read a file as text - - Args: - fname (str): Filename to read - - Returns: - str: Contents of file - """ - return open(cls._get_path(fname), encoding='utf-8').read() - - @classmethod - def _get_patch_name(cls, subject): - """Get the filename of a patch given its subject - - Args: - subject (str): Patch subject - - Returns: - str: Filename for that patch - """ - fname = re.sub('[ :]', '-', subject) - return fname.replace('--', '-') - - def _create_patches_for_test(self, series): - """Create patch files for use by tests - - This copies patch files from the test directory as needed by the series - - Args: - series (Series): Series containing commits to convert - - Returns: - tuple: - str: Cover-letter filename, or None if none - fname_list: list of str, each a patch filename - """ - cover_fname = None - fname_list = [] - for i, commit in enumerate(series.commits): - clean_subject = self._get_patch_name(commit.subject) - src_fname = '%04d-%s.patch' % (i + 1, clean_subject[:52]) - fname = os.path.join(self.tmpdir, src_fname) - shutil.copy(self._get_path(src_fname), fname) - fname_list.append(fname) - if series.get('cover'): - src_fname = '0000-cover-letter.patch' - cover_fname = os.path.join(self.tmpdir, src_fname) - fname = os.path.join(self.tmpdir, src_fname) - shutil.copy(self._get_path(src_fname), fname) - - return cover_fname, fname_list - - def test_basic(self): - """Tests the basic flow of patman - - This creates a series from some hard-coded patches build from a simple - tree with the following metadata in the top commit: - - Series-to: u-boot - Series-prefix: RFC - Series-postfix: some-branch - Series-cc: Stefan Brüns <[email protected]> - Cover-letter-cc: Lord Mëlchett <[email protected]> - Series-version: 3 - Patch-cc: fred - Series-process-log: sort, uniq - Series-changes: 4 - - Some changes - - Multi - line - change - - Commit-changes: 2 - - Changes only for this commit - - Cover-changes: 4 - - Some notes for the cover letter - - Cover-letter: - test: A test patch series - This is a test of how the cover - letter - works - END - - and this in the first commit: - - Commit-changes: 2 - - second revision change - - Series-notes: - some notes - about some things - from the first commit - END - - Commit-notes: - Some notes about - the first commit - END - - with the following commands: - - git log -n2 --reverse >/path/to/tools/patman/test/test01.txt - git format-patch --subject-prefix RFC --cover-letter HEAD~2 - mv 00* /path/to/tools/patman/test - - It checks these aspects: - - git log can be processed by patchstream - - emailing patches uses the correct command - - CC file has information on each commit - - cover letter has the expected text and subject - - each patch has the correct subject - - dry-run information prints out correctly - - unicode is handled correctly - - Series-to, Series-cc, Series-prefix, Series-postfix, Cover-letter - - Cover-letter-cc, Series-version, Series-changes, Series-notes - - Commit-notes - """ - process_tags = True - ignore_bad_tags = False - stefan = (b'Stefan Br\xc3\xbcns <[email protected]>' - .decode('utf-8')) - rick = 'Richard III <[email protected]>' - mel = b'Lord M\xc3\xablchett <[email protected]>'.decode('utf-8') - add_maintainers = [stefan, rick] - dry_run = True - in_reply_to = mel - count = 2 - alias = { - 'fdt': ['simon'], - 'u-boot': ['[email protected]'], - 'simon': [self.leb], - 'fred': [self.fred], - 'joe': [self.joe], - } - - text = self._get_text('test01.txt') - series = patchstream.get_metadata_for_test(text) - series.base_commit = Commit('1a44532') - series.branch = 'mybranch' - cover_fname, args = self._create_patches_for_test(series) - get_maintainer_script = str(pathlib.Path(__file__).parent.parent.parent - / 'get_maintainer.pl') + ' --norolestats' - with terminal.capture() as out: - patchstream.fix_patches(series, args) - if cover_fname and series.get('cover'): - patchstream.insert_cover_letter(cover_fname, series, count) - series.DoChecks() - cc_file = series.MakeCcFile(process_tags, cover_fname, - not ignore_bad_tags, add_maintainers, - None, get_maintainer_script, alias) - cmd = gitutil.email_patches( - series, cover_fname, args, dry_run, not ignore_bad_tags, - cc_file, alias, in_reply_to=in_reply_to, thread=None) - series.ShowActions(args, cmd, process_tags, alias) - cc_lines = tools.read_file(cc_file, binary=False).splitlines() - os.remove(cc_file) - - itr = iter(out[0].getvalue().splitlines()) - self.assertEqual('Cleaned %s patches' % len(series.commits), - next(itr)) - self.assertEqual('Change log missing for v2', next(itr)) - self.assertEqual('Change log missing for v3', next(itr)) - self.assertEqual('Change log for unknown version v4', next(itr)) - self.assertEqual("Alias 'pci' not found", next(itr)) - while next(itr) != 'Cc processing complete': - pass - self.assertIn('Dry run', next(itr)) - self.assertEqual('', next(itr)) - self.assertIn('Send a total of %d patches' % count, next(itr)) - prev = next(itr) - for i in range(len(series.commits)): - self.assertEqual(' %s' % args[i], prev) - while True: - prev = next(itr) - if 'Cc:' not in prev: - break - self.assertEqual('To: [email protected]', prev) - self.assertEqual('Cc: %s' % stefan, next(itr)) - self.assertEqual('Version: 3', next(itr)) - self.assertEqual('Prefix:\t RFC', next(itr)) - self.assertEqual('Postfix:\t some-branch', next(itr)) - self.assertEqual('Cover: 4 lines', next(itr)) - self.assertEqual(' Cc: %s' % self.fred, next(itr)) - self.assertEqual(' Cc: %s' % self.joe, next(itr)) - self.assertEqual(' Cc: %s' % self.leb, - next(itr)) - self.assertEqual(' Cc: %s' % mel, next(itr)) - self.assertEqual(' Cc: %s' % rick, next(itr)) - expected = ('Git command: git send-email --annotate ' - '--in-reply-to="%s" --to [email protected] ' - '--cc "%s" --cc-cmd "%s send --cc-cmd %s" %s %s' - % (in_reply_to, stefan, sys.argv[0], cc_file, cover_fname, - ' '.join(args))) - self.assertEqual(expected, next(itr)) - - self.assertEqual(('%s %s\0%s' % (args[0], rick, stefan)), cc_lines[0]) - self.assertEqual( - '%s %s\0%s\0%s\0%s\0%s' % (args[1], self.fred, self.joe, self.leb, - rick, stefan), - cc_lines[1]) - - expected = ''' -This is a test of how the cover -letter -works - -some notes -about some things -from the first commit - -Changes in v4: -- Multi - line - change -- Some changes -- Some notes for the cover letter -- fdt: Correct cast for sandbox in fdtdec_setup_mem_size_base() - -Simon Glass (2): - pci: Correct cast for sandbox - fdt: Correct cast for sandbox in fdtdec_setup_mem_size_base() - - cmd/pci.c | 3 ++- - fs/fat/fat.c | 1 + - lib/efi_loader/efi_memory.c | 1 + - lib/fdtdec.c | 3 ++- - 4 files changed, 6 insertions(+), 2 deletions(-) - ---\x20 -2.7.4 - -base-commit: 1a44532 -branch: mybranch -''' - lines = tools.read_file(cover_fname, binary=False).splitlines() - self.assertEqual( - 'Subject: [RFC PATCH some-branch v3 0/2] test: A test patch series', - lines[3]) - self.assertEqual(expected.splitlines(), lines[7:]) - - for i, fname in enumerate(args): - lines = tools.read_file(fname, binary=False).splitlines() - subject = [line for line in lines if line.startswith('Subject')] - self.assertEqual('Subject: [RFC %d/%d]' % (i + 1, count), - subject[0][:18]) - - # Check that we got our commit notes - start = 0 - expected = '' - - if i == 0: - start = 17 - expected = '''--- -Some notes about -the first commit - -(no changes since v2) - -Changes in v2: -- second revision change''' - elif i == 1: - start = 17 - expected = '''--- - -Changes in v4: -- Multi - line - change -- New -- Some changes - -Changes in v2: -- Changes only for this commit''' - - if expected: - expected = expected.splitlines() - self.assertEqual(expected, lines[start:(start+len(expected))]) - - def test_base_commit(self): - """Test adding a base commit with no cover letter""" - orig_text = self._get_text('test01.txt') - pos = orig_text.index( - 'commit 5ab48490f03051875ab13d288a4bf32b507d76fd') - text = orig_text[:pos] - series = patchstream.get_metadata_for_test(text) - series.base_commit = Commit('1a44532') - series.branch = 'mybranch' - cover_fname, args = self._create_patches_for_test(series) - self.assertFalse(cover_fname) - with terminal.capture() as out: - patchstream.fix_patches(series, args, insert_base_commit=True) - self.assertEqual('Cleaned 1 patch\n', out[0].getvalue()) - lines = tools.read_file(args[0], binary=False).splitlines() - pos = lines.index('-- ') - - # We expect these lines at the end: - # -- (with trailing space) - # 2.7.4 - # (empty) - # base-commit: xxx - # branch: xxx - self.assertEqual('base-commit: 1a44532', lines[pos + 3]) - self.assertEqual('branch: mybranch', lines[pos + 4]) - - def test_branch(self): - """Test creating patches from a branch""" - repo = self.make_git_tree() - target = repo.lookup_reference('refs/heads/first') - # pylint doesn't seem to find this - # pylint: disable=E1101 - self.repo.checkout(target, strategy=pygit2.GIT_CHECKOUT_FORCE) - control.setup() - orig_dir = os.getcwd() - try: - os.chdir(self.tmpdir) - - # Check that it can detect the current branch - self.assertEqual(2, gitutil.count_commits_to_branch(None)) - col = terminal.Color() - with terminal.capture() as _: - _, cover_fname, patch_files = send.prepare_patches( - col, branch=None, count=-1, start=0, end=0, - ignore_binary=False, signoff=True) - self.assertIsNone(cover_fname) - self.assertEqual(2, len(patch_files)) - - # Check that it can detect a different branch - self.assertEqual(3, gitutil.count_commits_to_branch('second')) - with terminal.capture() as _: - _, cover_fname, patch_files = send.prepare_patches( - col, branch='second', count=-1, start=0, end=0, - ignore_binary=False, signoff=True) - self.assertIsNotNone(cover_fname) - self.assertEqual(3, len(patch_files)) - - cover = tools.read_file(cover_fname, binary=False) - lines = cover.splitlines()[-2:] - base = repo.lookup_reference('refs/heads/base').target - self.assertEqual(f'base-commit: {base}', lines[0]) - self.assertEqual('branch: second', lines[1]) - - # Make sure that the base-commit is not present when it is in the - # cover letter - for fname in patch_files: - self.assertNotIn(b'base-commit:', tools.read_file(fname)) - - # Check that it can skip patches at the end - with terminal.capture() as _: - _, cover_fname, patch_files = send.prepare_patches( - col, branch='second', count=-1, start=0, end=1, - ignore_binary=False, signoff=True) - self.assertIsNotNone(cover_fname) - self.assertEqual(2, len(patch_files)) - - cover = tools.read_file(cover_fname, binary=False) - lines = cover.splitlines()[-2:] - base2 = repo.lookup_reference('refs/heads/second') - ref = base2.peel(pygit2.GIT_OBJ_COMMIT).parents[0].parents[0].id - self.assertEqual(f'base-commit: {ref}', lines[0]) - self.assertEqual('branch: second', lines[1]) - finally: - os.chdir(orig_dir) - - def test_custom_get_maintainer_script(self): - """Validate that a custom get_maintainer script gets used.""" - self.make_git_tree() - with directory_excursion(self.tmpdir): - # Setup git. - os.environ['GIT_CONFIG_GLOBAL'] = '/dev/null' - os.environ['GIT_CONFIG_SYSTEM'] = '/dev/null' - tools.run('git', 'config', 'user.name', 'Dummy') - tools.run('git', 'config', 'user.email', '[email protected]') - tools.run('git', 'branch', 'upstream') - tools.run('git', 'branch', '--set-upstream-to=upstream') - - # Setup patman configuration. - tools.write_file('.patman', '[settings]\n' - 'get_maintainer_script: dummy-script.sh\n' - 'check_patch: False\n' - 'add_maintainers: True\n', binary=False) - tools.write_file('dummy-script.sh', - '#!/usr/bin/env python3\n' - 'print("[email protected]")\n', binary=False) - os.chmod('dummy-script.sh', 0x555) - tools.run('git', 'add', '.') - tools.run('git', 'commit', '-m', 'new commit') - - # Finally, do the test - with terminal.capture(): - output = tools.run(PATMAN_DIR / 'patman', '--dry-run') - # Assert the email address is part of the dry-run - # output. - self.assertIn('[email protected]', output) - - def test_tags(self): - """Test collection of tags in a patchstream""" - text = '''This is a patch - -Signed-off-by: Terminator -Reviewed-by: %s -Reviewed-by: %s -Tested-by: %s -''' % (self.joe, self.mary, self.leb) - pstrm = PatchStream.process_text(text) - self.assertEqual(pstrm.commit.rtags, { - 'Reviewed-by': {self.joe, self.mary}, - 'Tested-by': {self.leb}}) - - def test_invalid_tag(self): - """Test invalid tag in a patchstream""" - text = '''This is a patch - -Serie-version: 2 -''' - with self.assertRaises(ValueError) as exc: - PatchStream.process_text(text) - self.assertEqual("Line 3: Invalid tag = 'Serie-version: 2'", - str(exc.exception)) - - def test_missing_end(self): - """Test a missing END tag""" - text = '''This is a patch - -Cover-letter: -This is the title -missing END after this line -Signed-off-by: Fred -''' - pstrm = PatchStream.process_text(text) - self.assertEqual(["Missing 'END' in section 'cover'"], - pstrm.commit.warn) - - def test_missing_blank_line(self): - """Test a missing blank line after a tag""" - text = '''This is a patch - -Series-changes: 2 -- First line of changes -- Missing blank line after this line -Signed-off-by: Fred -''' - pstrm = PatchStream.process_text(text) - self.assertEqual(["Missing 'blank line' in section 'Series-changes'"], - pstrm.commit.warn) - - def test_invalid_commit_tag(self): - """Test an invalid Commit-xxx tag""" - text = '''This is a patch - -Commit-fred: testing -''' - pstrm = PatchStream.process_text(text) - self.assertEqual(["Line 3: Ignoring Commit-fred"], pstrm.commit.warn) - - def test_self_test(self): - """Test a tested by tag by this user""" - test_line = 'Tested-by: %[email protected]' % os.getenv('USER') - text = '''This is a patch - -%s -''' % test_line - pstrm = PatchStream.process_text(text) - self.assertEqual(["Ignoring '%s'" % test_line], pstrm.commit.warn) - - def test_space_before_tab(self): - """Test a space before a tab""" - text = '''This is a patch - -+ \tSomething -''' - pstrm = PatchStream.process_text(text) - self.assertEqual(["Line 3/0 has space before tab"], pstrm.commit.warn) - - def test_lines_after_test(self): - """Test detecting lines after TEST= line""" - text = '''This is a patch - -TEST=sometest -more lines -here -''' - pstrm = PatchStream.process_text(text) - self.assertEqual(["Found 2 lines after TEST="], pstrm.commit.warn) - - def test_blank_line_at_end(self): - """Test detecting a blank line at the end of a file""" - text = '''This is a patch - -diff --git a/lib/fdtdec.c b/lib/fdtdec.c -index c072e54..942244f 100644 ---- a/lib/fdtdec.c -+++ b/lib/fdtdec.c -@@ -1200,7 +1200,8 @@ int fdtdec_setup_mem_size_base(void) - \t} - - \tgd->ram_size = (phys_size_t)(res.end - res.start + 1); -- debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size); -+ debug("%s: Initial DRAM size %llx\n", __func__, -+ (unsigned long long)gd->ram_size); -+ -diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c - --- -2.7.4 - - ''' - pstrm = PatchStream.process_text(text) - self.assertEqual( - ["Found possible blank line(s) at end of file 'lib/fdtdec.c'"], - pstrm.commit.warn) - - def test_no_upstream(self): - """Test CountCommitsToBranch when there is no upstream""" - repo = self.make_git_tree() - target = repo.lookup_reference('refs/heads/base') - # pylint doesn't seem to find this - # pylint: disable=E1101 - self.repo.checkout(target, strategy=pygit2.GIT_CHECKOUT_FORCE) - - # Check that it can detect the current branch - orig_dir = os.getcwd() - try: - os.chdir(self.gitdir) - with self.assertRaises(ValueError) as exc: - gitutil.count_commits_to_branch(None) - self.assertIn( - "Failed to determine upstream: fatal: no upstream configured for branch 'base'", - str(exc.exception)) - finally: - os.chdir(orig_dir) - - def run_patman(self, *args): - """Run patman using the provided arguments - - This runs the patman executable from scratch, as opposed to calling - the control.do_patman() function. - - Args: - args (list of str): Arguments to pass (excluding argv[0]) - - Return: - CommandResult: Result of execution - """ - all_args = [self._patman_pathname] + list(args) - return command.run_one(*all_args, capture=True, capture_stderr=True) - - def test_full_help(self): - """Test getting full help""" - command.TEST_RESULT = None - result = self.run_patman('-H') - help_file = os.path.join(self._patman_dir, 'README.rst') - # Remove possible extraneous strings - extra = '::::::::::::::\n' + help_file + '\n::::::::::::::\n' - gothelp = result.stdout.replace(extra, '') - self.assertEqual(len(gothelp), os.path.getsize(help_file)) - self.assertEqual(0, len(result.stderr)) - self.assertEqual(0, result.return_code) - - def test_help(self): - """Test getting help with commands and arguments""" - command.TEST_RESULT = None - result = self.run_patman('-h') - self.assertTrue(len(result.stdout) > 1000) - self.assertEqual(0, len(result.stderr)) - self.assertEqual(0, result.return_code) - - @staticmethod - def _fake_patchwork(subpath): - """Fake Patchwork server for the function below - - This handles accessing a series, providing a list consisting of a - single patch - - Args: - subpath (str): URL subpath to use - """ - re_series = re.match(r'series/(\d*)/$', subpath) - if re_series: - series_num = re_series.group(1) - if series_num == '1234': - return {'patches': [ - {'id': '1', 'name': 'Some patch'}]} - raise ValueError('Fake Patchwork does not understand: %s' % subpath) - - def test_status_mismatch(self): - """Test Patchwork patches not matching the series""" - pwork = patchwork.Patchwork.for_testing(self._fake_patchwork) - with terminal.capture() as (_, err): - loop = asyncio.get_event_loop() - _, patches = loop.run_until_complete(status.check_status(1234, - pwork)) - status.check_patch_count(0, len(patches)) - self.assertIn('Warning: Patchwork reports 1 patches, series has 0', - err.getvalue()) - - def test_status_read_patch(self): - """Test handling a single patch in Patchwork""" - pwork = patchwork.Patchwork.for_testing(self._fake_patchwork) - loop = asyncio.get_event_loop() - _, patches = loop.run_until_complete(status.check_status(1234, pwork)) - self.assertEqual(1, len(patches)) - patch = patches[0] - self.assertEqual('1', patch.id) - self.assertEqual('Some patch', patch.raw_subject) - - def test_parse_subject(self): - """Test parsing of the patch subject""" - patch = patchwork.Patch('1') - - # Simple patch not in a series - patch.parse_subject('Testing') - self.assertEqual('Testing', patch.raw_subject) - self.assertEqual('Testing', patch.subject) - self.assertEqual(1, patch.seq) - self.assertEqual(1, patch.count) - self.assertEqual(None, patch.prefix) - self.assertEqual(None, patch.version) - - # First patch in a series - patch.parse_subject('[1/2] Testing') - self.assertEqual('[1/2] Testing', patch.raw_subject) - self.assertEqual('Testing', patch.subject) - self.assertEqual(1, patch.seq) - self.assertEqual(2, patch.count) - self.assertEqual(None, patch.prefix) - self.assertEqual(None, patch.version) - - # Second patch in a series - patch.parse_subject('[2/2] Testing') - self.assertEqual('Testing', patch.subject) - self.assertEqual(2, patch.seq) - self.assertEqual(2, patch.count) - self.assertEqual(None, patch.prefix) - self.assertEqual(None, patch.version) - - # With PATCH prefix - patch.parse_subject('[PATCH,2/5] Testing') - self.assertEqual('Testing', patch.subject) - self.assertEqual(2, patch.seq) - self.assertEqual(5, patch.count) - self.assertEqual('PATCH', patch.prefix) - self.assertEqual(None, patch.version) - - # RFC patch - patch.parse_subject('[RFC,3/7] Testing') - self.assertEqual('Testing', patch.subject) - self.assertEqual(3, patch.seq) - self.assertEqual(7, patch.count) - self.assertEqual('RFC', patch.prefix) - self.assertEqual(None, patch.version) - - # Version patch - patch.parse_subject('[v2,3/7] Testing') - self.assertEqual('Testing', patch.subject) - self.assertEqual(3, patch.seq) - self.assertEqual(7, patch.count) - self.assertEqual(None, patch.prefix) - self.assertEqual('v2', patch.version) - - # All fields - patch.parse_subject('[RESEND,v2,3/7] Testing') - self.assertEqual('Testing', patch.subject) - self.assertEqual(3, patch.seq) - self.assertEqual(7, patch.count) - self.assertEqual('RESEND', patch.prefix) - self.assertEqual('v2', patch.version) - - # RFC only - patch.parse_subject('[RESEND] Testing') - self.assertEqual('Testing', patch.subject) - self.assertEqual(1, patch.seq) - self.assertEqual(1, patch.count) - self.assertEqual('RESEND', patch.prefix) - self.assertEqual(None, patch.version) - - def test_compare_series(self): - """Test operation of compare_with_series()""" - commit1 = Commit('abcd') - commit1.subject = 'Subject 1' - commit2 = Commit('ef12') - commit2.subject = 'Subject 2' - commit3 = Commit('3456') - commit3.subject = 'Subject 2' - - patch1 = patchwork.Patch('1') - patch1.subject = 'Subject 1' - patch2 = patchwork.Patch('2') - patch2.subject = 'Subject 2' - patch3 = patchwork.Patch('3') - patch3.subject = 'Subject 2' - - series = Series() - series.commits = [commit1] - patches = [patch1] - patch_for_commit, commit_for_patch, warnings = ( - status.compare_with_series(series, patches)) - self.assertEqual(1, len(patch_for_commit)) - self.assertEqual(patch1, patch_for_commit[0]) - self.assertEqual(1, len(commit_for_patch)) - self.assertEqual(commit1, commit_for_patch[0]) - - series.commits = [commit1] - patches = [patch1, patch2] - patch_for_commit, commit_for_patch, warnings = ( - status.compare_with_series(series, patches)) - self.assertEqual(1, len(patch_for_commit)) - self.assertEqual(patch1, patch_for_commit[0]) - self.assertEqual(1, len(commit_for_patch)) - self.assertEqual(commit1, commit_for_patch[0]) - self.assertEqual(["Cannot find commit for patch 2 ('Subject 2')"], - warnings) - - series.commits = [commit1, commit2] - patches = [patch1] - patch_for_commit, commit_for_patch, warnings = ( - status.compare_with_series(series, patches)) - self.assertEqual(1, len(patch_for_commit)) - self.assertEqual(patch1, patch_for_commit[0]) - self.assertEqual(1, len(commit_for_patch)) - self.assertEqual(commit1, commit_for_patch[0]) - self.assertEqual(["Cannot find patch for commit 2 ('Subject 2')"], - warnings) - - series.commits = [commit1, commit2, commit3] - patches = [patch1, patch2] - patch_for_commit, commit_for_patch, warnings = ( - status.compare_with_series(series, patches)) - self.assertEqual(2, len(patch_for_commit)) - self.assertEqual(patch1, patch_for_commit[0]) - self.assertEqual(patch2, patch_for_commit[1]) - self.assertEqual(1, len(commit_for_patch)) - self.assertEqual(commit1, commit_for_patch[0]) - self.assertEqual(["Cannot find patch for commit 3 ('Subject 2')", - "Multiple commits match patch 2 ('Subject 2'):\n" - ' Subject 2\n Subject 2'], - warnings) - - series.commits = [commit1, commit2] - patches = [patch1, patch2, patch3] - patch_for_commit, commit_for_patch, warnings = ( - status.compare_with_series(series, patches)) - self.assertEqual(1, len(patch_for_commit)) - self.assertEqual(patch1, patch_for_commit[0]) - self.assertEqual(2, len(commit_for_patch)) - self.assertEqual(commit1, commit_for_patch[0]) - self.assertEqual(["Multiple patches match commit 2 ('Subject 2'):\n" - ' Subject 2\n Subject 2', - "Cannot find commit for patch 3 ('Subject 2')"], - warnings) - - def _fake_patchwork2(self, subpath): - """Fake Patchwork server for the function below - - This handles accessing series, patches and comments, providing the data - in self.patches to the caller - - Args: - subpath (str): URL subpath to use - """ - re_series = re.match(r'series/(\d*)/$', subpath) - re_patch = re.match(r'patches/(\d*)/$', subpath) - re_comments = re.match(r'patches/(\d*)/comments/$', subpath) - if re_series: - series_num = re_series.group(1) - if series_num == '1234': - return {'patches': self.patches} - elif re_patch: - patch_num = int(re_patch.group(1)) - patch = self.patches[patch_num - 1] - return patch - elif re_comments: - patch_num = int(re_comments.group(1)) - patch = self.patches[patch_num - 1] - return patch.comments - raise ValueError('Fake Patchwork does not understand: %s' % subpath) - - def test_find_new_responses(self): - """Test operation of find_new_responses()""" - commit1 = Commit('abcd') - commit1.subject = 'Subject 1' - commit2 = Commit('ef12') - commit2.subject = 'Subject 2' - - patch1 = patchwork.Patch('1') - patch1.parse_subject('[1/2] Subject 1') - patch1.name = patch1.raw_subject - patch1.content = 'This is my patch content' - comment1a = {'content': 'Reviewed-by: %s\n' % self.joe} - - patch1.comments = [comment1a] - - patch2 = patchwork.Patch('2') - patch2.parse_subject('[2/2] Subject 2') - patch2.name = patch2.raw_subject - patch2.content = 'Some other patch content' - comment2a = { - 'content': 'Reviewed-by: %s\nTested-by: %s\n' % - (self.mary, self.leb)} - comment2b = {'content': 'Reviewed-by: %s' % self.fred} - patch2.comments = [comment2a, comment2b] - - # This test works by setting up commits and patch for use by the fake - # Rest API function _fake_patchwork2(). It calls various functions in - # the status module after setting up tags in the commits, checking that - # things behaves as expected - self.commits = [commit1, commit2] - self.patches = [patch1, patch2] - - # Check that the tags are picked up on the first patch - new_rtags, _ = status.process_reviews(patch1.content, patch1.comments, - commit1.rtags) - self.assertEqual(new_rtags, {'Reviewed-by': {self.joe}}) - - # Now the second patch - new_rtags, _ = status.process_reviews(patch2.content, patch2.comments, - commit2.rtags) - self.assertEqual(new_rtags, { - 'Reviewed-by': {self.mary, self.fred}, - 'Tested-by': {self.leb}}) - - # Now add some tags to the commit, which means they should not appear as - # 'new' tags when scanning comments - commit1.rtags = {'Reviewed-by': {self.joe}} - new_rtags, _ = status.process_reviews(patch1.content, patch1.comments, - commit1.rtags) - self.assertEqual(new_rtags, {}) - - # For the second commit, add Ed and Fred, so only Mary should be left - commit2.rtags = { - 'Tested-by': {self.leb}, - 'Reviewed-by': {self.fred}} - new_rtags, _ = status.process_reviews(patch2.content, patch2.comments, - commit2.rtags) - self.assertEqual(new_rtags, {'Reviewed-by': {self.mary}}) - - # Check that the output patches expectations: - # 1 Subject 1 - # Reviewed-by: Joe Bloggs <[email protected]> - # 2 Subject 2 - # Tested-by: Lord Edmund Blackaddër <[email protected]> - # Reviewed-by: Fred Bloggs <[email protected]> - # + Reviewed-by: Mary Bloggs <[email protected]> - # 1 new response available in patchwork - - series = Series() - series.commits = [commit1, commit2] - terminal.set_print_test_mode() - pwork = patchwork.Patchwork.for_testing(self._fake_patchwork2) - status.check_and_show_status(series, '1234', None, None, False, False, - False, pwork) - itr = iter(terminal.get_print_test_lines()) - col = terminal.Color() - self.assertEqual(terminal.PrintLine(' 1 Subject 1', col.YELLOW), - next(itr)) - self.assertEqual( - terminal.PrintLine(' Reviewed-by: ', col.GREEN, newline=False, - bright=False), - next(itr)) - self.assertEqual(terminal.PrintLine(self.joe, col.WHITE, bright=False), - next(itr)) - - self.assertEqual(terminal.PrintLine(' 2 Subject 2', col.YELLOW), - next(itr)) - self.assertEqual( - terminal.PrintLine(' Reviewed-by: ', col.GREEN, newline=False, - bright=False), - next(itr)) - self.assertEqual(terminal.PrintLine(self.fred, col.WHITE, - bright=False), next(itr)) - self.assertEqual( - terminal.PrintLine(' Tested-by: ', col.GREEN, newline=False, - bright=False), - next(itr)) - self.assertEqual(terminal.PrintLine(self.leb, col.WHITE, bright=False), - next(itr)) - self.assertEqual( - terminal.PrintLine(' + Reviewed-by: ', col.GREEN, newline=False), - next(itr)) - self.assertEqual(terminal.PrintLine(self.mary, col.WHITE), - next(itr)) - self.assertEqual(terminal.PrintLine( - '1 new response available in patchwork (use -d to write them to a new branch)', - None), next(itr)) - - def _fake_patchwork3(self, subpath): - """Fake Patchwork server for the function below - - This handles accessing series, patches and comments, providing the data - in self.patches to the caller - - Args: - subpath (str): URL subpath to use - """ - re_series = re.match(r'series/(\d*)/$', subpath) - re_patch = re.match(r'patches/(\d*)/$', subpath) - re_comments = re.match(r'patches/(\d*)/comments/$', subpath) - if re_series: - series_num = re_series.group(1) - if series_num == '1234': - return {'patches': self.patches} - elif re_patch: - patch_num = int(re_patch.group(1)) - patch = self.patches[patch_num - 1] - return patch - elif re_comments: - patch_num = int(re_comments.group(1)) - patch = self.patches[patch_num - 1] - return patch.comments - raise ValueError('Fake Patchwork does not understand: %s' % subpath) - - def test_create_branch(self): - """Test operation of create_branch()""" - repo = self.make_git_tree() - branch = 'first' - dest_branch = 'first2' - count = 2 - gitdir = self.gitdir - - # Set up the test git tree. We use branch 'first' which has two commits - # in it - series = patchstream.get_metadata_for_list(branch, gitdir, count) - self.assertEqual(2, len(series.commits)) - - patch1 = patchwork.Patch('1') - patch1.parse_subject('[1/2] %s' % series.commits[0].subject) - patch1.name = patch1.raw_subject - patch1.content = 'This is my patch content' - comment1a = {'content': 'Reviewed-by: %s\n' % self.joe} - - patch1.comments = [comment1a] - - patch2 = patchwork.Patch('2') - patch2.parse_subject('[2/2] %s' % series.commits[1].subject) - patch2.name = patch2.raw_subject - patch2.content = 'Some other patch content' - comment2a = { - 'content': 'Reviewed-by: %s\nTested-by: %s\n' % - (self.mary, self.leb)} - comment2b = { - 'content': 'Reviewed-by: %s' % self.fred} - patch2.comments = [comment2a, comment2b] - - # This test works by setting up patches for use by the fake Rest API - # function _fake_patchwork3(). The fake patch comments above should - # result in new review tags that are collected and added to the commits - # created in the destination branch. - self.patches = [patch1, patch2] - count = 2 - - # Expected output: - # 1 i2c: I2C things - # + Reviewed-by: Joe Bloggs <[email protected]> - # 2 spi: SPI fixes - # + Reviewed-by: Fred Bloggs <[email protected]> - # + Reviewed-by: Mary Bloggs <[email protected]> - # + Tested-by: Lord Edmund Blackaddër <[email protected]> - # 4 new responses available in patchwork - # 4 responses added from patchwork into new branch 'first2' - # <unittest.result.TestResult run=8 errors=0 failures=0> - - terminal.set_print_test_mode() - pwork = patchwork.Patchwork.for_testing(self._fake_patchwork3) - status.check_and_show_status( - series, '1234', branch, dest_branch, False, False, False, pwork, - repo) - lines = terminal.get_print_test_lines() - self.assertEqual(12, len(lines)) - self.assertEqual( - "4 responses added from patchwork into new branch 'first2'", - lines[11].text) - - # Check that the destination branch has the new tags - new_series = patchstream.get_metadata_for_list(dest_branch, gitdir, - count) - self.assertEqual( - {'Reviewed-by': {self.joe}}, - new_series.commits[0].rtags) - self.assertEqual( - {'Tested-by': {self.leb}, - 'Reviewed-by': {self.fred, self.mary}}, - new_series.commits[1].rtags) - - # Now check the actual test of the first commit message. We expect to - # see the new tags immediately below the old ones. - stdout = patchstream.get_list(dest_branch, count=count, git_dir=gitdir) - itr = iter([line.strip() for line in stdout.splitlines() - if '-by:' in line]) - - # First patch should have the review tag - self.assertEqual('Reviewed-by: %s' % self.joe, next(itr)) - - # Second patch should have the sign-off then the tested-by and two - # reviewed-by tags - self.assertEqual('Signed-off-by: %s' % self.leb, next(itr)) - self.assertEqual('Reviewed-by: %s' % self.fred, next(itr)) - self.assertEqual('Reviewed-by: %s' % self.mary, next(itr)) - self.assertEqual('Tested-by: %s' % self.leb, next(itr)) - - def test_parse_snippets(self): - """Test parsing of review snippets""" - text = '''Hi Fred, - -This is a comment from someone. - -Something else - -On some recent date, Fred wrote: -> This is why I wrote the patch -> so here it is - -Now a comment about the commit message -A little more to say - -Even more - -> diff --git a/file.c b/file.c -> Some more code -> Code line 2 -> Code line 3 -> Code line 4 -> Code line 5 -> Code line 6 -> Code line 7 -> Code line 8 -> Code line 9 - -And another comment - -> @@ -153,8 +143,13 @@ def check_patch(fname, show_types=False): -> further down on the file -> and more code -> +Addition here -> +Another addition here -> codey -> more codey - -and another thing in same file - -> @@ -253,8 +243,13 @@ -> with no function context - -one more thing - -> diff --git a/tools/patman/main.py b/tools/patman/main.py -> +line of code -now a very long comment in a different file -line2 -line3 -line4 -line5 -line6 -line7 -line8 -''' - pstrm = PatchStream.process_text(text, True) - self.assertEqual([], pstrm.commit.warn) - - # We expect to the filename and up to 5 lines of code context before - # each comment. The 'On xxx wrote:' bit should be removed. - self.assertEqual( - [['Hi Fred,', - 'This is a comment from someone.', - 'Something else'], - ['> This is why I wrote the patch', - '> so here it is', - 'Now a comment about the commit message', - 'A little more to say', 'Even more'], - ['> File: file.c', '> Code line 5', '> Code line 6', - '> Code line 7', '> Code line 8', '> Code line 9', - 'And another comment'], - ['> File: file.c', - '> Line: 153 / 143: def check_patch(fname, show_types=False):', - '> and more code', '> +Addition here', - '> +Another addition here', '> codey', '> more codey', - 'and another thing in same file'], - ['> File: file.c', '> Line: 253 / 243', - '> with no function context', 'one more thing'], - ['> File: tools/patman/main.py', '> +line of code', - 'now a very long comment in a different file', - 'line2', 'line3', 'line4', 'line5', 'line6', 'line7', 'line8']], - pstrm.snippets) - - def test_review_snippets(self): - """Test showing of review snippets""" - def _to_submitter(who): - m_who = re.match('(.*) <(.*)>', who) - return { - 'name': m_who.group(1), - 'email': m_who.group(2) - } - - commit1 = Commit('abcd') - commit1.subject = 'Subject 1' - commit2 = Commit('ef12') - commit2.subject = 'Subject 2' - - patch1 = patchwork.Patch('1') - patch1.parse_subject('[1/2] Subject 1') - patch1.name = patch1.raw_subject - patch1.content = 'This is my patch content' - comment1a = {'submitter': _to_submitter(self.joe), - 'content': '''Hi Fred, - -On some date Fred wrote: - -> diff --git a/file.c b/file.c -> Some code -> and more code - -Here is my comment above the above... - - -Reviewed-by: %s -''' % self.joe} - - patch1.comments = [comment1a] - - patch2 = patchwork.Patch('2') - patch2.parse_subject('[2/2] Subject 2') - patch2.name = patch2.raw_subject - patch2.content = 'Some other patch content' - comment2a = { - 'content': 'Reviewed-by: %s\nTested-by: %s\n' % - (self.mary, self.leb)} - comment2b = {'submitter': _to_submitter(self.fred), - 'content': '''Hi Fred, - -On some date Fred wrote: - -> diff --git a/tools/patman/commit.py b/tools/patman/commit.py -> @@ -41,6 +41,9 @@ class Commit: -> self.rtags = collections.defaultdict(set) -> self.warn = [] -> -> + def __str__(self): -> + return self.subject -> + -> def add_change(self, version, info): -> """Add a new change line to the change list for a version. -> -A comment - -Reviewed-by: %s -''' % self.fred} - patch2.comments = [comment2a, comment2b] - - # This test works by setting up commits and patch for use by the fake - # Rest API function _fake_patchwork2(). It calls various functions in - # the status module after setting up tags in the commits, checking that - # things behaves as expected - self.commits = [commit1, commit2] - self.patches = [patch1, patch2] - - # Check that the output patches expectations: - # 1 Subject 1 - # Reviewed-by: Joe Bloggs <[email protected]> - # 2 Subject 2 - # Tested-by: Lord Edmund Blackaddër <[email protected]> - # Reviewed-by: Fred Bloggs <[email protected]> - # + Reviewed-by: Mary Bloggs <[email protected]> - # 1 new response available in patchwork - - series = Series() - series.commits = [commit1, commit2] - terminal.set_print_test_mode() - pwork = patchwork.Patchwork.for_testing(self._fake_patchwork2) - status.check_and_show_status( - series, '1234', None, None, False, True, False, pwork) - itr = iter(terminal.get_print_test_lines()) - col = terminal.Color() - self.assertEqual(terminal.PrintLine(' 1 Subject 1', col.YELLOW), - next(itr)) - self.assertEqual( - terminal.PrintLine(' + Reviewed-by: ', col.GREEN, newline=False), - next(itr)) - self.assertEqual(terminal.PrintLine(self.joe, col.WHITE), next(itr)) - - self.assertEqual(terminal.PrintLine('Review: %s' % self.joe, col.RED), - next(itr)) - self.assertEqual(terminal.PrintLine(' Hi Fred,', None), next(itr)) - self.assertEqual(terminal.PrintLine('', None), next(itr)) - self.assertEqual(terminal.PrintLine(' > File: file.c', col.MAGENTA), - next(itr)) - self.assertEqual(terminal.PrintLine(' > Some code', col.MAGENTA), - next(itr)) - self.assertEqual(terminal.PrintLine(' > and more code', - col.MAGENTA), - next(itr)) - self.assertEqual(terminal.PrintLine( - ' Here is my comment above the above...', None), next(itr)) - self.assertEqual(terminal.PrintLine('', None), next(itr)) - - self.assertEqual(terminal.PrintLine(' 2 Subject 2', col.YELLOW), - next(itr)) - self.assertEqual( - terminal.PrintLine(' + Reviewed-by: ', col.GREEN, newline=False), - next(itr)) - self.assertEqual(terminal.PrintLine(self.fred, col.WHITE), - next(itr)) - self.assertEqual( - terminal.PrintLine(' + Reviewed-by: ', col.GREEN, newline=False), - next(itr)) - self.assertEqual(terminal.PrintLine(self.mary, col.WHITE), - next(itr)) - self.assertEqual( - terminal.PrintLine(' + Tested-by: ', col.GREEN, newline=False), - next(itr)) - self.assertEqual(terminal.PrintLine(self.leb, col.WHITE), - next(itr)) - - self.assertEqual(terminal.PrintLine('Review: %s' % self.fred, col.RED), - next(itr)) - self.assertEqual(terminal.PrintLine(' Hi Fred,', None), next(itr)) - self.assertEqual(terminal.PrintLine('', None), next(itr)) - self.assertEqual(terminal.PrintLine( - ' > File: tools/patman/commit.py', col.MAGENTA), next(itr)) - self.assertEqual(terminal.PrintLine( - ' > Line: 41 / 41: class Commit:', col.MAGENTA), next(itr)) - self.assertEqual(terminal.PrintLine( - ' > + return self.subject', col.MAGENTA), next(itr)) - self.assertEqual(terminal.PrintLine( - ' > +', col.MAGENTA), next(itr)) - self.assertEqual( - terminal.PrintLine( - ' > def add_change(self, version, info):', - col.MAGENTA), - next(itr)) - self.assertEqual(terminal.PrintLine( - ' > """Add a new change line to the change list for a version.', - col.MAGENTA), next(itr)) - self.assertEqual(terminal.PrintLine( - ' >', col.MAGENTA), next(itr)) - self.assertEqual(terminal.PrintLine( - ' A comment', None), next(itr)) - self.assertEqual(terminal.PrintLine('', None), next(itr)) - - self.assertEqual(terminal.PrintLine( - '4 new responses available in patchwork (use -d to write them to a new branch)', - None), next(itr)) - - def test_insert_tags(self): - """Test inserting of review tags""" - msg = '''first line -second line.''' - tags = [ - 'Reviewed-by: Bin Meng <[email protected]>', - 'Tested-by: Bin Meng <[email protected]>' - ] - signoff = 'Signed-off-by: Simon Glass <[email protected]>' - tag_str = '\n'.join(tags) - - new_msg = patchstream.insert_tags(msg, tags) - self.assertEqual(msg + '\n\n' + tag_str, new_msg) - - new_msg = patchstream.insert_tags(msg + '\n', tags) - self.assertEqual(msg + '\n\n' + tag_str, new_msg) - - msg += '\n\n' + signoff - new_msg = patchstream.insert_tags(msg, tags) - self.assertEqual(msg + '\n' + tag_str, new_msg) diff --git a/tools/patman/patchwork.py b/tools/patman/patchwork.py deleted file mode 100644 index d485648e467..00000000000 --- a/tools/patman/patchwork.py +++ /dev/null @@ -1,852 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2025 Simon Glass <[email protected]> -# -"""Provides a basic API for the patchwork server -""" - -import asyncio -import re - -import aiohttp -from collections import namedtuple - -from u_boot_pylib import terminal - -# Information passed to series_get_states() -# link (str): Patchwork link for series -# series_id (int): Series ID in database -# series_name (str): Series name -# version (int): Version number of series -# show_comments (bool): True to show comments -# show_cover_comments (bool): True to show cover-letter comments -STATE_REQ = namedtuple( - 'state_req', - 'link,series_id,series_name,version,show_comments,show_cover_comments') - -# Responses from series_get_states() -# int: ser_ver ID number -# COVER: Cover-letter info -# list of Patch: Information on each patch in the series -# list of dict: patches, see get_series()['patches'] -STATE_RESP = namedtuple('state_resp', 'svid,cover,patches,patch_list') - -# Information about a cover-letter on patchwork -# id (int): Patchwork ID of cover letter -# state (str): Current state, e.g. 'accepted' -# num_comments (int): Number of comments -# name (str): Series name -# comments (list of dict): Comments -COVER = namedtuple('cover', 'id,num_comments,name,comments') - -# Number of retries -RETRIES = 3 - -# Max concurrent request -MAX_CONCURRENT = 50 - -# Patches which are part of a multi-patch series are shown with a prefix like -# [prefix, version, sequence], for example '[RFC, v2, 3/5]'. All but the last -# part is optional. This decodes the string into groups. For single patches -# the [] part is not present: -# Groups: (ignore, ignore, ignore, prefix, version, sequence, subject) -RE_PATCH = re.compile(r'(\[(((.*),)?(.*),)?(.*)\]\s)?(.*)$') - -# This decodes the sequence string into a patch number and patch count -RE_SEQ = re.compile(r'(\d+)/(\d+)') - - -class Patch(dict): - """Models a patch in patchwork - - This class records information obtained from patchwork - - Some of this information comes from the 'Patch' column: - - [RFC,v2,1/3] dm: Driver and uclass changes for tiny-dm - - This shows the prefix, version, seq, count and subject. - - The other properties come from other columns in the display. - - Properties: - pid (str): ID of the patch (typically an integer) - seq (int): Sequence number within series (1=first) parsed from sequence - string - count (int): Number of patches in series, parsed from sequence string - raw_subject (str): Entire subject line, e.g. - "[1/2,v2] efi_loader: Sort header file ordering" - prefix (str): Prefix string or None (e.g. 'RFC') - version (str): Version string or None (e.g. 'v2') - raw_subject (str): Raw patch subject - subject (str): Patch subject with [..] part removed (same as commit - subject) - data (dict or None): Patch data: - """ - def __init__(self, pid, state=None, data=None, comments=None, - series_data=None): - super().__init__() - self.id = pid # Use 'id' to match what the Rest API provides - self.seq = None - self.count = None - self.prefix = None - self.version = None - self.raw_subject = None - self.subject = None - self.state = state - self.data = data - self.comments = comments - self.series_data = series_data - self.name = None - - # These make us more like a dictionary - def __setattr__(self, name, value): - self[name] = value - - def __getattr__(self, name): - return self[name] - - def __hash__(self): - return hash(frozenset(self.items())) - - def __str__(self): - return self.raw_subject - - def parse_subject(self, raw_subject): - """Parse the subject of a patch into its component parts - - See RE_PATCH for details. The parsed info is placed into seq, count, - prefix, version, subject - - Args: - raw_subject (str): Subject string to parse - - Raises: - ValueError: the subject cannot be parsed - """ - self.raw_subject = raw_subject.strip() - mat = RE_PATCH.search(raw_subject.strip()) - if not mat: - raise ValueError(f"Cannot parse subject '{raw_subject}'") - self.prefix, self.version, seq_info, self.subject = mat.groups()[3:] - mat_seq = RE_SEQ.match(seq_info) if seq_info else False - if mat_seq is None: - self.version = seq_info - seq_info = None - if self.version and not self.version.startswith('v'): - self.prefix = self.version - self.version = None - if seq_info: - if mat_seq: - self.seq = int(mat_seq.group(1)) - self.count = int(mat_seq.group(2)) - else: - self.seq = 1 - self.count = 1 - - -class Review: - """Represents a single review email collected in Patchwork - - Patches can attract multiple reviews. Each consists of an author/date and - a variable number of 'snippets', which are groups of quoted and unquoted - text. - """ - def __init__(self, meta, snippets): - """Create new Review object - - Args: - meta (str): Text containing review author and date - snippets (list): List of snippets in th review, each a list of text - lines - """ - self.meta = ' : '.join([line for line in meta.splitlines() if line]) - self.snippets = snippets - - -class Patchwork: - """Class to handle communication with patchwork - """ - def __init__(self, url, show_progress=True, single_thread=False): - """Set up a new patchwork handler - - Args: - url (str): URL of patchwork server, e.g. - 'https://patchwork.ozlabs.org' - """ - self.url = url - self.fake_request = None - self.proj_id = None - self.link_name = None - self._show_progress = show_progress - self.semaphore = asyncio.Semaphore( - 1 if single_thread else MAX_CONCURRENT) - self.request_count = 0 - - async def _request(self, client, subpath): - """Call the patchwork API and return the result as JSON - - Args: - client (aiohttp.ClientSession): Session to use - subpath (str): URL subpath to use - - Returns: - dict: Json result - - Raises: - ValueError: the URL could not be read - """ - # print('subpath', subpath) - self.request_count += 1 - if self.fake_request: - return self.fake_request(subpath) - - full_url = f'{self.url}/api/1.2/{subpath}' - async with self.semaphore: - # print('full_url', full_url) - for i in range(RETRIES + 1): - try: - async with client.get(full_url) as response: - if response.status != 200: - raise ValueError( - f"Could not read URL '{full_url}'") - result = await response.json() - # print('- done', full_url) - return result - break - except aiohttp.client_exceptions.ServerDisconnectedError: - if i == RETRIES: - raise - - @staticmethod - def for_testing(func): - """Get an instance to use for testing - - Args: - func (function): Function to call to handle requests. The function - is passed a URL and is expected to return a dict with the - resulting data - - Returns: - Patchwork: testing instance - """ - pwork = Patchwork(None, show_progress=False) - pwork.fake_request = func - return pwork - - class _Stats: - def __init__(self, parent): - self.parent = parent - self.request_count = 0 - - def __enter__(self): - return self - - def __exit__(self, exc_type, exc_val, exc_tb): - self.request_count = self.parent.request_count - - def collect_stats(self): - """Context manager to count requests across a range of patchwork calls - - Usage: - pwork = Patchwork(...) - with pwork.count_requests() as counter: - pwork.something() - print(f'{counter.count} requests') - """ - self.request_count = 0 - return self._Stats(self) - - async def get_projects(self): - """Get a list of projects on the server - - Returns: - list of dict, one for each project - 'name' (str): Project name, e.g. 'U-Boot' - 'id' (int): Project ID, e.g. 9 - 'link_name' (str): Project's link-name, e.g. 'uboot' - """ - async with aiohttp.ClientSession() as client: - return await self._request(client, 'projects/') - - async def _query_series(self, client, desc): - """Query series by name - - Args: - client (aiohttp.ClientSession): Session to use - desc: String to search for - - Return: - list of series matches, each a dict, see get_series() - """ - query = desc.replace(' ', '+') - return await self._request( - client, f'series/?project={self.proj_id}&q={query}') - - async def _find_series(self, client, svid, ser_id, version, ser): - """Find a series on the server - - Args: - client (aiohttp.ClientSession): Session to use - svid (int): ser_ver ID - ser_id (int): series ID - version (int): Version number to search for - ser (Series): Contains description (cover-letter title) - - Returns: - tuple: - int: ser_ver ID (as passed in) - int: series ID (as passed in) - str: Series link, or None if not found - list of dict, or None if found - each dict is the server result from a possible series - """ - desc = ser.desc - name_found = [] - - # Do a series query on the description - res = await self._query_series(client, desc) - for pws in res: - if pws['name'] == desc: - if int(pws['version']) == version: - return svid, ser_id, pws['id'], None - name_found.append(pws) - - # When there is no cover letter, patchwork uses the first patch as the - # series name - cmt = ser.commits[0] - - res = await self._query_series(client, cmt.subject) - for pws in res: - patch = Patch(0) - patch.parse_subject(pws['name']) - if patch.subject == cmt.subject: - if int(pws['version']) == version: - return svid, ser_id, pws['id'], None - name_found.append(pws) - - return svid, ser_id, None, name_found or res - - async def find_series(self, ser, version): - """Find a series based on its description and version - - Args: - ser (Series): Contains description (cover-letter title) - version (int): Version number - - Return: tuple: - tuple: - str: Series ID, or None if not found - list of dict, or None if found - each dict is the server result from a possible series - int: number of server requests done - """ - async with aiohttp.ClientSession() as client: - # We don't know the svid and it isn't needed, so use -1 - _, _, link, options = await self._find_series(client, -1, -1, - version, ser) - return link, options - - async def find_series_list(self, to_find): - """Find the link for each series in a list - - Args: - to_find (dict of svids to sync): - key (int): ser_ver ID - value (tuple): - int: Series ID - int: Series version - str: Series link - str: Series description - - Return: tuple: - list of tuple, one for each item in to_find: - int: ser_ver_ID - int: series ID - int: Series version - str: Series link, or None if not found - list of dict, or None if found - each dict is the server result from a possible series - int: number of server requests done - """ - self.request_count = 0 - async with aiohttp.ClientSession() as client: - tasks = [asyncio.create_task( - self._find_series(client, svid, ser_id, version, desc)) - for svid, (ser_id, version, link, desc) in to_find.items()] - results = await asyncio.gather(*tasks) - - return results, self.request_count - - def project_set(self, project_id, link_name): - """Set the project ID - - The patchwork server has multiple projects. This allows the ID and - link_name of the relevant project to be selected - - This function is used for testing - - Args: - project_id (int): Project ID to use, e.g. 6 - link_name (str): Name to use for project URL links, e.g. 'uboot' - """ - self.proj_id = project_id - self.link_name = link_name - - async def get_series(self, client, link): - """Read information about a series - - Args: - client (aiohttp.ClientSession): Session to use - link (str): Patchwork series ID - - Returns: dict containing patchwork's series information - id (int): series ID unique across patchwork instance, e.g. 3 - url (str): Full URL, e.g. - 'https://patchwork.ozlabs.org/api/1.2/series/3/' - web_url (str): Full URL, e.g. - 'https://patchwork.ozlabs.org/project/uboot/list/?series=3 - project (dict): project information (id, url, name, link_name, - list_id, list_email, etc. - name (str): Series name, e.g. '[U-Boot] moveconfig: fix error' - date (str): Date, e.g. '2017-08-27T08:00:51' - submitter (dict): id, url, name, email, e.g.: - "id": 6125, - "url": "https://patchwork.ozlabs.org/api/1.2/people/6125/", - "name": "Chris Packham", - "email": "[email protected]" - version (int): Version number - total (int): Total number of patches based on subject - received_total (int): Total patches received by patchwork - received_all (bool): True if all patches were received - mbox (str): URL of mailbox, e.g. - 'https://patchwork.ozlabs.org/series/3/mbox/' - cover_letter (dict) or None, e.g.: - "id": 806215, - "url": "https://patchwork.ozlabs.org/api/1.2/covers/806215/", - "web_url": "https://patchwork.ozlabs.org/project/uboot/cover/ - [email protected]/", - "msgid": "<[email protected]>", - "list_archive_url": null, - "date": "2017-08-27T09:44:07", - "name": "[U-Boot,v2,0/4] usb: net: Migrate USB Ethernet", - "mbox": "https://patchwork.ozlabs.org/project/uboot/cover/ - [email protected]/mbox/" - patches (list of dict), each e.g.: - "id": 806202, - "url": "https://patchwork.ozlabs.org/api/1.2/patches/806202/", - "web_url": "https://patchwork.ozlabs.org/project/uboot/patch/ - [email protected]/", - "msgid": "<[email protected]>", - "list_archive_url": null, - "date": "2017-08-27T08:00:51", - "name": "[U-Boot] moveconfig: fix error message do_autoconf()", - "mbox": "https://patchwork.ozlabs.org/project/uboot/patch/ - [email protected]/mbox/" - """ - return await self._request(client, f'series/{link}/') - - async def get_patch(self, client, patch_id): - """Read information about a patch - - Args: - client (aiohttp.ClientSession): Session to use - patch_id (str): Patchwork patch ID - - Returns: dict containing patchwork's patch information - "id": 185, - "url": "https://patchwork.ozlabs.org/api/1.2/patches/185/", - "web_url": "https://patchwork.ozlabs.org/project/cbe-oss-dev/patch/ - [email protected]/", - project (dict): project information (id, url, name, link_name, - list_id, list_email, etc. - "msgid": "<[email protected]>", - "list_archive_url": null, - "date": "2008-09-05T07:16:27", - "name": "powerpc/spufs: Fix possible scheduling of a context", - "commit_ref": "b2e601d14deb2083e2a537b47869ab3895d23a28", - "pull_url": null, - "state": "accepted", - "archived": false, - "hash": "bc1c0b80d7cff66c0d1e5f3f8f4d10eb36176f0d", - "submitter": { - "id": 93, - "url": "https://patchwork.ozlabs.org/api/1.2/people/93/", - "name": "Andre Detsch", - "email": "[email protected]" - }, - "delegate": { - "id": 1, - "url": "https://patchwork.ozlabs.org/api/1.2/users/1/", - "username": "jk", - "first_name": "Jeremy", - "last_name": "Kerr", - "email": "[email protected]" - }, - "mbox": "https://patchwork.ozlabs.org/project/cbe-oss-dev/patch/ - [email protected]/mbox/", - "series": [], - "comments": "https://patchwork.ozlabs.org/api/patches/185/ - comments/", - "check": "pending", - "checks": "https://patchwork.ozlabs.org/api/patches/185/checks/", - "tags": {}, - "related": [], - "headers": {...} - "content": "We currently have a race when scheduling a context - after we have found a runnable context in spusched_tick, the - context may have been scheduled by spu_activate(). - - This may result in a panic if we try to unschedule a context - been freed in the meantime. - - This change exits spu_schedule() if the context has already - scheduled, so we don't end up scheduling it twice. - - Signed-off-by: Andre Detsch <[email protected]>", - "diff": '''Index: spufs/arch/powerpc/platforms/cell/spufs/sched.c - ======================================================= - --- spufs.orig/arch/powerpc/platforms/cell/spufs/sched.c - +++ spufs/arch/powerpc/platforms/cell/spufs/sched.c - @@ -727,7 +727,8 @@ static void spu_schedule(struct spu *spu - \t/* not a candidate for interruptible because it's called - \t from the scheduler thread or from spu_deactivate */ - \tmutex_lock(&ctx->state_mutex); - -\t__spu_schedule(spu, ctx); - +\tif (ctx->state == SPU_STATE_SAVED) - +\t\t__spu_schedule(spu, ctx); - \tspu_release(ctx); - } - ''' - "prefixes": ["3/3", ...] - """ - return await self._request(client, f'patches/{patch_id}/') - - async def _get_patch_comments(self, client, patch_id): - """Read comments about a patch - - Args: - client (aiohttp.ClientSession): Session to use - patch_id (str): Patchwork patch ID - - Returns: list of dict: list of comments: - id (int): series ID unique across patchwork instance, e.g. 3331924 - web_url (str): Full URL, e.g. - 'https://patchwork.ozlabs.org/comment/3331924/' - msgid (str): Message ID, e.g. - '<[email protected]>' - list_archive_url: (unknown?) - date (str): Date, e.g. '2024-06-20T13:38:03' - subject (str): email subject, e.g. 'Re: [PATCH 3/5] buildman: - Support building within a Python venv' - date (str): Date, e.g. '2017-08-27T08:00:51' - submitter (dict): id, url, name, email, e.g.: - "id": 61270, - "url": "https://patchwork.ozlabs.org/api/people/61270/", - "name": "Heinrich Schuchardt", - "email": "[email protected]" - content (str): Content of email, e.g. 'On 20.06.24 15:19, - Simon Glass wrote: - >...' - headers: dict: email headers, see get_cover() for an example - """ - return await self._request(client, f'patches/{patch_id}/comments/') - - async def get_cover(self, client, cover_id): - """Read information about a cover letter - - Args: - client (aiohttp.ClientSession): Session to use - cover_id (int): Patchwork cover-letter ID - - Returns: dict containing patchwork's cover-letter information: - id (int): series ID unique across patchwork instance, e.g. 3 - url (str): Full URL, e.g. https://patchwork.ozlabs.org/project/uboot/list/?series=3 - project (dict): project information (id, url, name, link_name, - list_id, list_email, etc. - url (str): Full URL, e.g. 'https://patchwork.ozlabs.org/api/1.2/covers/2054866/' - web_url (str): Full URL, e.g. 'https://patchwork.ozlabs.org/project/uboot/cover/[email protected]/' - project (dict): project information (id, url, name, link_name, - list_id, list_email, etc. - msgid (str): Message ID, e.g. '[email protected]>' - list_archive_url (?) - date (str): Date, e.g. '2017-08-27T08:00:51' - name (str): Series name, e.g. '[U-Boot] moveconfig: fix error' - submitter (dict): id, url, name, email, e.g.: - "id": 6170, - "url": "https://patchwork.ozlabs.org/api/1.2/people/6170/", - "name": "Simon Glass", - "email": "[email protected]" - mbox (str): URL to mailbox, e.g. 'https://patchwork.ozlabs.org/project/uboot/cover/[email protected]/mbox/' - series (list of dict) each e.g.: - "id": 446956, - "url": "https://patchwork.ozlabs.org/api/1.2/series/446956/", - "web_url": "https://patchwork.ozlabs.org/project/uboot/list/?series=446956", - "date": "2025-03-04T13:09:37", - "name": "binman: Check code-coverage requirements", - "version": 1, - "mbox": "https://patchwork.ozlabs.org/series/446956/mbox/" - comments: Web URL to comments: 'https://patchwork.ozlabs.org/api/covers/2054866/comments/' - headers: dict: e.g.: - "Return-Path": "<[email protected]>", - "X-Original-To": "[email protected]", - "Delivered-To": "[email protected]", - "Authentication-Results": [ - "legolas.ozlabs.org; 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- Tue, 04 Mar 2025 05:09:52 -0800 (PST)", - "From": "Simon Glass <[email protected]>", - "To": "U-Boot Mailing List <[email protected]>", - "Cc": "Simon Glass <[email protected]>, Alexander Kochetkov <[email protected]>, - Alper Nebi Yasak <[email protected]>, - Brandon Maier <[email protected]>, - Jerome Forissier <[email protected]>, - Jiaxun Yang <[email protected]>, - Neha Malcom Francis <[email protected]>, - Patrick Rudolph <[email protected]>, - Paul HENRYS <[email protected]>, Peng Fan <[email protected]>, - Philippe Reynes <[email protected]>, - Stefan Herbrechtsmeier <[email protected]>, - Tom Rini <[email protected]>", - "Subject": "[PATCH 0/7] binman: Check code-coverage requirements", - "Date": "Tue, 4 Mar 2025 06:09:37 -0700", - "Message-ID": "<[email protected]>", - "X-Mailer": "git-send-email 2.43.0", - "MIME-Version": "1.0", - "Content-Transfer-Encoding": "8bit", - "X-BeenThere": "[email protected]", - "X-Mailman-Version": "2.1.39", - "Precedence": "list", - "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", - "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>, - <mailto:[email protected]?subject=unsubscribe>", - "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", - "List-Post": "<mailto:[email protected]>", - "List-Help": "<mailto:[email protected]?subject=help>", - "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>, - <mailto:[email protected]?subject=subscribe>", - "Errors-To": "[email protected]", - "Sender": "\"U-Boot\" <[email protected]>", - "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", - "X-Virus-Status": "Clean" - content (str): Email content, e.g. 'This series adds a cover-coverage check to CI for Binman. The iMX8 tests -are still not completed,...' - """ - async with aiohttp.ClientSession() as client: - return await self._request(client, f'covers/{cover_id}/') - - async def get_cover_comments(self, client, cover_id): - """Read comments about a cover letter - - Args: - client (aiohttp.ClientSession): Session to use - cover_id (str): Patchwork cover-letter ID - - Returns: list of dict: list of comments, each: - id (int): series ID unique across patchwork instance, e.g. 3472068 - web_url (str): Full URL, e.g. 'https://patchwork.ozlabs.org/comment/3472068/' - list_archive_url: (unknown?) - - project (dict): project information (id, url, name, link_name, - list_id, list_email, etc. - url (str): Full URL, e.g. 'https://patchwork.ozlabs.org/api/1.2/covers/2054866/' - web_url (str): Full URL, e.g. 'https://patchwork.ozlabs.org/project/uboot/cover/[email protected]/' - project (dict): project information (id, url, name, link_name, - list_id, list_email, etc. - date (str): Date, e.g. '2025-03-04T13:16:15' - subject (str): 'Re: [PATCH 0/7] binman: Check code-coverage requirements' - submitter (dict): id, url, name, email, e.g.: - "id": 6170, - "url": "https://patchwork.ozlabs.org/api/people/6170/", - "name": "Simon Glass", - "email": "[email protected]" - content (str): Email content, e.g. 'Hi, - -On Tue, 4 Mar 2025 at 06:09, Simon Glass <[email protected]> wrote: -> -> This '... - headers: dict: email headers, see get_cover() for an example - """ - return await self._request(client, f'covers/{cover_id}/comments/') - - async def get_series_url(self, link): - """Get the URL for a series - - Args: - link (str): Patchwork series ID - - Returns: - str: URL for the series page - """ - return f'{self.url}/project/{self.link_name}/list/?series={link}&state=*&archive=both' - - async def _get_patch_status(self, client, patch_id): - """Get the patch status - - Args: - client (aiohttp.ClientSession): Session to use - patch_id (int): Patch ID to look up in patchwork - - Return: - PATCH: Patch information - - Requests: - 1 for patch, 1 for patch comments - """ - data = await self.get_patch(client, patch_id) - state = data['state'] - comment_data = await self._get_patch_comments(client, patch_id) - - return Patch(patch_id, state, data, comment_data) - - async def get_series_cover(self, client, data): - """Get the cover information (including comments) - - Args: - client (aiohttp.ClientSession): Session to use - data (dict): Return value from self.get_series() - - Returns: - COVER object, or None if no cover letter - """ - # Patchwork should always provide this, but use get() so that we don't - # have to provide it in our fake patchwork _fake_patchwork_cser() - cover = data.get('cover_letter') - cover_id = None - if cover: - cover_id = cover['id'] - info = await self.get_cover_comments(client, cover_id) - cover = COVER(cover_id, len(info), cover['name'], info) - return cover - - async def series_get_state(self, client, link, read_comments, - read_cover_comments): - """Sync the series information against patchwork, to find patch status - - Args: - client (aiohttp.ClientSession): Session to use - link (str): Patchwork series ID - read_comments (bool): True to read the comments on the patches - read_cover_comments (bool): True to read the comments on the cover - letter - - Return: tuple: - COVER object, or None if none or not read_cover_comments - list of PATCH objects - """ - data = await self.get_series(client, link) - patch_list = list(data['patches']) - - count = len(patch_list) - patches = [] - if read_comments: - # Returns a list of Patch objects - tasks = [self._get_patch_status(client, patch_list[i]['id']) - for i in range(count)] - - patch_status = await asyncio.gather(*tasks) - for patch_data, status in zip(patch_list, patch_status): - status.series_data = patch_data - patches.append(status) - else: - for i in range(count): - info = patch_list[i] - pat = Patch(info['id'], series_data=info) - pat.raw_subject = info['name'] - patches.append(pat) - if self._show_progress: - terminal.print_clear() - - if read_cover_comments: - cover = await self.get_series_cover(client, data) - else: - cover = None - - return cover, patches diff --git a/tools/patman/patman.rst b/tools/patman/patman.rst deleted file mode 100644 index 549e203c254..00000000000 --- a/tools/patman/patman.rst +++ /dev/null @@ -1,1023 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0+ -.. Copyright (c) 2011 The Chromium OS Authors -.. Simon Glass <[email protected]> -.. Maxim Cournoyer <[email protected]> -.. v1, v2, 19-Oct-11 -.. revised v3 24-Nov-11 -.. revised v4 Independence Day 2020, with Patchwork integration - -Patman patch manager -==================== - -This tool is a Python script which: - -- Creates patch directly from your branch -- Cleans them up by removing unwanted tags -- Inserts a cover letter with change lists -- Runs the patches through checkpatch.pl and its own checks -- Optionally emails them out to selected people -- Links the series automatically to Patchwork once sent - -It also has some Patchwork features: - -- Manage local series and their status on patchwork -- Show review tags from Patchwork and allows them to be gathered into commits -- List comments received on a series - -It is intended to automate patch creation and make it a less -error-prone process. It is useful for U-Boot and Linux work so far, -since they use the checkpatch.pl script. - -It is configured almost entirely by tags it finds in your commits. -This means that you can work on a number of different branches at -once, and keep the settings with each branch rather than having to -git format-patch, git send-email, etc. with the correct parameters -each time. So for example if you put:: - - Series-to: [email protected] - -in one of your commits, the series will be sent there. - -In Linux and U-Boot this will also call get_maintainer.pl on each of your -patches automatically (unless you use -m to disable this). - - -Installation ------------- - -You can install patman using:: - - pip install patch-manager - -The name is chosen since patman conflicts with an existing package. - -If you are using patman within the U-Boot tree, it may be easiest to add a -symlink from your local `~/.bin` directory to `/path/to/tools/patman/patman`. - -How to use this tool --------------------- - -This tool requires a certain way of working: - -- Maintain a number of branches, one for each patch series you are - working on -- Add tags into the commits within each branch to indicate where the - series should be sent, cover letter, version, etc. Most of these are - normally in the top commit so it is easy to change them with 'git - commit --amend' -- Each branch tracks the upstream branch, so that this script can - automatically determine the number of commits in it (optional) -- Check out a branch, and run this script to create and send out your - patches. Weeks later, change the patches and repeat, knowing that you - will get a consistent result each time. - - -How to configure it -------------------- - -For most cases of using patman for U-Boot development, patman can use the -file 'doc/git-mailrc' in your U-Boot directory to supply the email aliases -you need. To make this work, tell git where to find the file by typing -this once:: - - git config sendemail.aliasesfile doc/git-mailrc - -For both Linux and U-Boot the 'scripts/get_maintainer.pl' handles -figuring out where to send patches pretty well. For other projects, -you may want to specify a different script to be run, for example via -a project-specific `.patman` file:: - - # .patman configuration file at the root of some project - - [settings] - get_maintainer_script: etc/teams.scm get-maintainer - -The `get_maintainer_script` option corresponds to the -`--get-maintainer-script` argument of the `send` command. It is -looked relatively to the root of the current git repository, as well -as on PATH. It can also be provided arguments, as shown above. The -contract is that the script should accept a patch file name and return -a list of email addresses, one per line, like `get_maintainer.pl` -does. - -During the first run patman creates a config file for you by taking the default -user name and email address from the global .gitconfig file. - -To add your own, create a file `~/.patman` like this:: - - # patman alias file - - [alias] - me: Simon Glass <[email protected]> - - u-boot: U-Boot Mailing List <[email protected]> - wolfgang: Wolfgang Denk <[email protected]> - others: Mike Frysinger <[email protected]>, Fred Bloggs <[email protected]> - -As hinted above, Patman will also look for a `.patman` configuration -file at the root of the current project git repository, which makes it -possible to override the `project` settings variable or anything else -in a project-specific way. The values of this "local" configuration -file take precedence over those of the "global" one. - -Aliases are recursive. - -The checkpatch.pl in the U-Boot tools/ subdirectory will be located and -used. Failing that you can put it into your path or ~/bin/checkpatch.pl - -If you want to avoid sending patches to email addresses that are picked up -by patman but are known to bounce you can add a [bounces] section to your -.patman file. Unlike the [alias] section these are simple key: value pairs -that are not recursive:: - - [bounces] - gonefishing: Fred Bloggs <[email protected]> - - -If you want to change the defaults for patman's command-line arguments, -you can add a [settings] section to your .patman file. This can be used -for any command line option by referring to the "dest" for the option in -patman.py. For reference, the useful ones (at the moment) shown below -(all with the non-default setting):: - - [settings] - ignore_errors: True - process_tags: False - verbose: True - smtp_server: /path/to/sendmail - patchwork_url: https://patchwork.ozlabs.org - -If you want to adjust settings (or aliases) that affect just a single -project you can add a section that looks like [project_settings] or -[project_alias]. If you want to use tags for your linux work, you could do:: - - [linux_settings] - process_tags: True - - -How to run it -------------- - -First do a dry run: - -.. code-block:: bash - - ./tools/patman/patman send -n - -If it can't detect the upstream branch, try telling it how many patches -there are in your series - -.. code-block:: bash - - ./tools/patman/patman -c5 send -n - -This will create patch files in your current directory and tell you who -it is thinking of sending them to. Take a look at the patch files: - -.. code-block:: bash - - ./tools/patman/patman -c5 -s1 send -n - -Similar to the above, but skip the first commit and take the next 5. This -is useful if your top commit is for setting up testing. - - -How to install it ------------------ - -The most up to date version of patman can be found in the U-Boot sources. -However to use it on other projects it may be more convenient to install it as -a standalone application. A distutils installer is included, this can be used -to install patman: - -.. code-block:: bash - - cd tools/patman && python setup.py install - - -How to add tags ---------------- - -To make this script useful you must add tags like the following into any -commit. Most can only appear once in the whole series. - -Series-to: email / alias - Email address / alias to send patch series to (you can add this - multiple times) - -Series-cc: email / alias, ... - Email address / alias to Cc patch series to (you can add this - multiple times) - -Series-version: n - Sets the version number of this patch series - -Series-prefix: prefix - Sets the subject prefix. Normally empty but it can be RFC for - RFC patches, or RESEND if you are being ignored. The patch subject - is like [RFC PATCH] or [RESEND PATCH]. - In the meantime, git format.subjectprefix option will be added as - well. If your format.subjectprefix is set to InternalProject, then - the patch shows like: [InternalProject][RFC/RESEND PATCH] - -Series-postfix: postfix - Sets the subject "postfix". Normally empty, but can be the name of a - tree such as net or net-next if that needs to be specified. The patch - subject is like [PATCH net] or [PATCH net-next]. - -Series-name: name - Sets the name of the series. You don't need to have a name, and - patman does not yet use it, but it is convenient to put the branch - name here to help you keep track of multiple upstreaming efforts. - -Series-links: [id | version:id]... - Set the ID of the series in patchwork. You can set this after you send - out the series and look in patchwork for the resulting series. The - URL you want is the one for the series itself, not any particular patch. - E.g. for http://patchwork.ozlabs.org/project/uboot/list/?series=187331 - the series ID is 187331. This property can have a list of series IDs, - one for each version of the series, e.g. - - :: - - Series-links: 1:187331 2:188434 189372 - - Patman always uses the one without a version, since it assumes this is - the latest one. When this tag is provided, patman can compare your local - branch against patchwork to see what new reviews your series has - collected ('patman status'). - -Series-patchwork-url: url - This allows specifying the Patchwork URL for a branch. This overrides - both the setting files ("patchwork_url") and the command-line argument. - The URL should include the protocol and web site, with no trailing slash, - for example 'https://patchwork.ozlabs.org/project' - -Cover-letter: - Sets the cover letter contents for the series. The first line - will become the subject of the cover letter:: - - Cover-letter: - This is the patch set title - blah blah - more blah blah - END - -Cover-letter-cc: email / alias - Additional email addresses / aliases to send cover letter to (you - can add this multiple times) - -Series-notes: - Sets some notes for the patch series, which you don't want in - the commit messages, but do want to send, The notes are joined - together and put after the cover letter. Can appear multiple - times:: - - Series-notes: - blah blah - blah blah - more blah blah - END - -Commit-notes: - Similar, but for a single commit (patch). These notes will appear - immediately below the ``---`` cut in the patch file:: - - Commit-notes: - blah blah - blah blah - more blah blah - -Signed-off-by: Their Name <email> - A sign-off is added automatically to your patches (this is - probably a bug). If you put this tag in your patches, it will - override the default signoff that patman automatically adds. - Multiple duplicate signoffs will be removed. - -Tested-by / Reviewed-by / Acked-by - These indicate that someone has tested/reviewed/acked your patch. - When you get this reply on the mailing list, you can add this - tag to the relevant commit and the script will include it when - you send out the next version. If 'Tested-by:' is set to - yourself, it will be removed. No one will believe you. - - Example:: - - Tested-by: Their Name <[email protected]> - Reviewed-by: Their Name <email> - Acked-by: Their Name <email> - -Series-changes: n - This can appear in any commit. It lists the changes for a - particular version n of that commit. The change list is - created based on this information. Each commit gets its own - change list and also the whole thing is repeated in the cover - letter (where duplicate change lines are merged). - - By adding your change lists into your commits it is easier to - keep track of what happened. When you amend a commit, remember - to update the log there and then, knowing that the script will - do the rest. - - Example:: - - Series-changes: n - - Guinea pig moved into its cage - - Other changes ending with a blank line - <blank line> - -Commit-changes: n - This tag is like Series-changes, except changes in this changelog will - only appear in the changelog of the commit this tag is in. This is - useful when you want to add notes which may not make sense in the cover - letter. For example, you can have short changes such as "New" or - "Lint". - - Example:: - - Commit-changes: n - - This line will not appear in the cover-letter changelog - <blank line> - -Cover-changes: n - This tag is like Series-changes, except changes in this changelog will - only appear in the cover-letter changelog. This is useful to summarize - changes made with Commit-changes, or to add additional context to - changes. - - Example:: - - Cover-changes: n - - This line will only appear in the cover letter - <blank line> - -Commit-added-in: n - Add a change noting the version this commit was added in. This is - equivalent to:: - - Commit-changes: n - - New - - Cover-changes: n - - <commit subject> - - It is a convenient shorthand for suppressing the '(no changes in vN)' - message. - -Patch-cc / Commit-cc: Their Name <email> - This copies a single patch to another email address. Note that the - Cc: used by git send-email is ignored by patman, but will be - interpreted by git send-email if you use it. - -Series-process-log: sort, uniq - This tells patman to sort and/or uniq the change logs. Changes may be - multiple lines long, as long as each subsequent line of a change begins - with a whitespace character. For example, - - Example:: - - - This change - continues onto the next line - - But this change is separate - - Use 'sort' to sort the entries, and 'uniq' to include only - unique entries. If omitted, no change log processing is done. - Separate each tag with a comma. - -Change-Id: - This tag is used to generate the Message-Id of the emails that - will be sent. When you keep the Change-Id the same you are - asserting that this is a slightly different version (but logically - the same patch) as other patches that have been sent out with the - same Change-Id. The Change-Id tag line is removed from outgoing - patches, unless the `keep_change_id` settings is set to `True`. - -Various other tags are silently removed, like these Chrome OS and -Gerrit tags:: - - BUG=... - TEST=... - Review URL: - Reviewed-on: - Commit-xxxx: (except Commit-notes) - -Exercise for the reader: Try adding some tags to one of your current -patch series and see how the patches turn out. - - -Where Patches Are Sent ----------------------- - -Once the patches are created, patman sends them using git send-email. The -whole series is sent to the recipients in Series-to: and Series-cc. -You can Cc individual patches to other people with the Patch-cc: tag. Tags -in the subject are also picked up to Cc patches. For example, a commit like -this:: - - commit 10212537b85ff9b6e09c82045127522c0f0db981 - Author: Mike Frysinger <[email protected]> - Date: Mon Nov 7 23:18:44 2011 -0500 - - x86: arm: add a git mailrc file for maintainers - - This should make sending out e-mails to the right people easier. - - Patch-cc: sandbox, mikef, ag - Patch-cc: afleming - -will create a patch which is copied to x86, arm, sandbox, mikef, ag and -afleming. - -If you have a cover letter it will get sent to the union of the Patch-cc -lists of all of the other patches. If you want to sent it to additional -people you can add a tag:: - - Cover-letter-cc: <list of addresses> - -These people will get the cover letter even if they are not on the To/Cc -list for any of the patches. - - -Patchwork Integration ---------------------- - -Patman has a very basic integration with Patchwork. If you point patman to -your series on patchwork it can show you what new reviews have appeared since -you sent your series. - -To set this up, add a Series-link tag to one of the commits in your series -(see above). - -Then you can type: - -.. code-block:: bash - - patman status - -and patman will show you each patch and what review tags have been collected, -for example:: - - ... - 21 x86: mtrr: Update the command to use the new mtrr - Reviewed-by: Wolfgang Wallner <[email protected]> - + Reviewed-by: Bin Meng <[email protected]> - 22 x86: mtrr: Restructure so command execution is in - Reviewed-by: Wolfgang Wallner <[email protected]> - + Reviewed-by: Bin Meng <[email protected]> - ... - -This shows that patch 21 and 22 were sent out with one review but have since -attracted another review each. If the series needs changes, you can update -these commits with the new review tag before sending the next version of the -series. - -To automatically pull into these tags into a new branch, use the -d option: - -.. code-block:: bash - - patman status -d mtrr4 - -This will create a new 'mtrr4' branch which is the same as your current branch -but has the new review tags in it. The tags are added in alphabetic order and -are placed immediately after any existing ack/review/test/fixes tags, or at the -end. You can check that this worked with: - -.. code-block:: bash - - patman -b mtrr4 status - -which should show that there are no new responses compared to this new branch. - -There is also a -C option to list the comments received for each patch. - - -Example Work Flow ------------------ - -The basic workflow is to create your commits, add some tags to the top -commit, and type 'patman' to check and send them. - -Here is an example workflow for a series of 4 patches. Let's say you have -these rather contrived patches in the following order in branch us-cmd in -your tree where 'us' means your upstreaming activity (newest to oldest as -output by git log --oneline):: - - 7c7909c wip - 89234f5 Don't include standard parser if hush is used - 8d640a7 mmc: sparc: Stop using builtin_run_command() - 0c859a9 Rename run_command2() to run_command() - a74443f sandbox: Rename run_command() to builtin_run_command() - -The first patch is some test things that enable your code to be compiled, -but that you don't want to submit because there is an existing patch for it -on the list. So you can tell patman to create and check some patches -(skipping the first patch) with: - -.. code-block:: bash - - patman -s1 send -n - -If you want to do all of them including the work-in-progress one, then -(if you are tracking an upstream branch): - -.. code-block:: bash - - patman send -n - -Let's say that patman reports an error in the second patch. Then: - -.. code-block:: bash - - git rebase -i HEAD~6 - # change 'pick' to 'edit' in 89234f5 - # use editor to make code changes - git add -u - git rebase --continue - -Now you have an updated patch series. To check it: - -.. code-block:: bash - - patman -s1 send -n - -Let's say it is now clean and you want to send it. Now you need to set up -the destination. So amend the top commit with: - -.. code-block:: bash - - git commit --amend - -Use your editor to add some tags, so that the whole commit message is:: - - The current run_command() is really only one of the options, with - hush providing the other. It really shouldn't be called directly - in case the hush parser is bring used, so rename this function to - better explain its purpose:: - - Series-to: u-boot - Series-cc: bfin, marex - Series-prefix: RFC - Cover-letter: - Unified command execution in one place - - At present two parsers have similar code to execute commands. Also - cmd_usage() is called all over the place. This series adds a single - function which processes commands called cmd_process(). - END - - Change-Id: Ica71a14c1f0ecb5650f771a32fecb8d2eb9d8a17 - - -You want this to be an RFC and Cc the whole series to the bfin alias and -to Marek. Two of the patches have tags (those are the bits at the front of -the subject that say mmc: sparc: and sandbox:), so 8d640a7 will be Cc'd to -mmc and sparc, and the last one to sandbox. - -Now to send the patches, take off the -n flag: - -.. code-block:: bash - - patman -s1 send - -The patches will be created, shown in your editor, and then sent along with -the cover letter. Note that patman's tags are automatically removed so that -people on the list don't see your secret info. - -Of course patches often attract comments and you need to make some updates. -Let's say one person sent comments and you get an Acked-by: on one patch. -Also, the patch on the list that you were waiting for has been merged, -so you can drop your wip commit. - -Take a look on patchwork and find out the URL of the series. This will be -something like `http://patchwork.ozlabs.org/project/uboot/list/?series=187331` -Add this to a tag in your top commit:: - - Series-links: 187331 - -You can use then patman to collect the Acked-by tag to the correct commit, -creating a new 'version 2' branch for us-cmd: - -.. code-block:: bash - - patman status -d us-cmd2 - git checkout us-cmd2 - -You can look at the comments in Patchwork or with: - -.. code-block:: bash - - patman status -C - -Then you can resync with upstream: - -.. code-block:: bash - - git fetch origin # or whatever upstream is called - git rebase origin/master - -and use git rebase -i to edit the commits, dropping the wip one. - -Then update the `Series-cc:` in the top commit to add the person who reviewed -the v1 series:: - - Series-cc: bfin, marex, Heiko Schocher <[email protected]> - -and remove the Series-prefix: tag since it it isn't an RFC any more. The -series is now version two, so the series info in the top commit looks like -this:: - - Series-to: u-boot - Series-cc: bfin, marex, Heiko Schocher <[email protected]> - Series-version: 2 - Cover-letter: - ... - -Finally, you need to add a change log to the two commits you changed. You -add change logs to each individual commit where the changes happened, like -this:: - - Series-changes: 2 - - Updated the command decoder to reduce code size - - Wound the torque propounder up a little more - -(note the blank line at the end of the list) - -When you run patman it will collect all the change logs from the different -commits and combine them into the cover letter, if you have one. So finally -you have a new series of commits:: - - faeb973 Don't include standard parser if hush is used - 1b2f2fe mmc: sparc: Stop using builtin_run_command() - cfbe330 Rename run_command2() to run_command() - 0682677 sandbox: Rename run_command() to builtin_run_command() - -so to send them: - -.. code-block:: bash - - patman - -and it will create and send the version 2 series. - - -Series Management ------------------ - -Sometimes you might have several series in flight at the same time. Each of -these receives comments and you want to create a new version of each series with -those comments addressed. - -Patman provides a few subcommands which are helpful for managing series. - -Series and branches -~~~~~~~~~~~~~~~~~~~ - -'patman series' works with the concept of a series. It maintains a local -database (.patman.db in your top-level git tree) and uses that to keep track of -series and patches. - -Each series goes through muliple versions. Patman requires that the first -version of your series is in a branch without a numeric suffix. Branch names -like 'serial' and 'video' are OK, but 'part3' is not. This is because Patman -uses the number at the end of the branch name to indicate the version. - -If your series name is 'video', then you can have a 'video' branch for version -1 of the series, 'video2' for version 2 and 'video3' for version 3. All three -branches are for the same series. Patman keeps track of these different -versions. It handles the branch naming automatically, but you need to be aware -of what it is doing. - -You will have an easier time if the branch names you use with 'patman series' -are short, no more than 15 characters. This is the amount of columnar space in -listings. You can add a longer description as the series description. If you -are used to having very descriptive branch names, remember that patman lets you -add metadata into commit which is automatically removed before sending. - -This documentation uses the term 'series' to mean all the versions of a series -and 'series/version' to mean a particular version of a series. - -Updating commits -~~~~~~~~~~~~~~~~ - -Since Patman provides quite a bit of automation, it updates your commits in -some cases, effectively doing a rebase of a branch in order to change the tags -in the commits. It never makes code changes. - -In extremis you can use 'git reflog' to revert something that Patman did. - - -Series subcommands -~~~~~~~~~~~~~~~~~~ - -Note that 'patman series ...' can be abbreviated as 'patman s' or 'patman ser'. - -Here is a short overview of the available subcommands: - - add - Add a new series. Use this on an existing branch to tell Patman about it. - - archive (ar) - Archive a series when you have finished upstreaming it. Archived series - are not shown by most commands. This creates a dated tag for each - version of the series, pointing to the series branch, then deletes the - branches. It puts the tag names in the database so that it can - 'unarchive' to restore things how they were. - - unarchive (unar) - Unarchive a series when you decide you need to do something more with - it. The branches are restored and tags deleted. - - autolink (au) - Search patchwork for the series link for your series, so Patman can - track the status - - autolink-all - Same but for all series - - inc - Increase the series number, effectively creating a new branch with the - next highest version number. The new branch is created based on the - existing branch. So if you use 'patman series inc' on branch 'video2' - it will create branch 'video3' and add v3 into its database - - dec - Decrease the series number, thus deleting the current branch and - removing that version from the data. If you use this comment on branch - 'video3' Patman will delete version 3 and branch 'video3'. - - get-link - Shows the Patchwork link for a series/version - - ls - Lists the series in the database - - mark - Mark a series with 'Change-Id' tags so that Patman can track patches - even when the subject changes. Unmarked patches just use the subject to - decided which is which. - - unmark - Remove 'Change-Id' tags from a series. - - open (o) - Open a series in Patchwork using your web browser - - patches - Show the patches in a particular series/version - - progress (p) - Show upstream progress for your series, or for all series - - rm - Remove a series entirely, including all versions - - rm-version (rmv) - Remove a particular version of a series. This is similar to 'dec' - except that any version can be removed, not just the latest one. - - scan - Scan the local branch and update the database with the set of patches - in that branch. This throws away the old patches. - - send - Send a series out as patches. This is similar to 'patman send' except - that it can send any series, not just the current branch. It also - waits a little for patchwork to see the cover letter, so it can find - out the patchwork link for the series. - - set-link - Sets the Patchwork link for a series-version manually. - - status (st) - Run 'patman status' on a series. This is similar to 'patman status' - except that it can get status on any series, not just the current - branch - - summary - Shows a quick summary of series with their status and description. - - sync - Sync the status of a series with Pathwork, so that - 'patman series progress' can show the right information. - - sync-all - Sync the status of all series. - - -Patman series workflow -~~~~~~~~~~~~~~~~~~~~~~ - -Here is a run-through of how to incorporate 'patman series' into your workflow. - -Firstly, set up your project:: - - patman patchwork set-project U-Boot - -This just tells Patman to look on the Patchwork server for a project of that -name. Internally Patman stores the ID and URL 'link-name' for the project, so it -can access it. - -If you need to use a different patchwork server, use the `--patchwork-url` -option or put the URL in your Patman-settings file. - -Now create a branch. For our example we are going to send out a series related -to video so the branch will be called 'video'. The upstream remove is called -'us':: - - git checkout -b video us/master - -We now have a branch and so we can do some commits:: - - <edit files> - git add ... - <edit files> - git add -u - git commit ... - git commit ... - -We now have a few commits in our 'video' branch. Let's tell patman about it:: - - patman series add - -Like most commands, if no series is given (`patman series -s video add`) then -the current branch is assumed. Since the branch is called 'video' patman knows -that it is version one of the video series. - -You'll likely get a warning that there is no cover letter. Let's add some tags -to the top commit:: - - Series-to: u-boot - Series-cc: ... - Cover-letter: - video: Improve syncing performance with cyclic - -Trying again:: - - patman series add - -You'll likely get a warning that the commits are unmarked. You can either let -patman add Change-Id values itself with the `-m` flag, or tell it not to worry -about it with `-M`. You must choose one or the other. Let's leave the commits -unmarked:: - - patman series add -M - -Congratulations, you've now got a patman database! - -Now let's send out the series. We will add tags to the top commit. - -To send it:: - - patman series send - -You should send 'git send-email' start up and you can confirm the sending of -each email. - -After that, patman waits a bit to see if it can find your new series appearing -on Patchwork. With a bit of luck this will only take 20 seconds or so. Then your -series is linked. - -To gather tags (Reviewed-by ...) for your series from patchwork:: - - patman series gather - -Now you can check your progress:: - - patman series progress - -Later on you get some comments, or perhaps you just decide to make a change on -your own. You have several options. - -The first option is that you can just create a new branch:: - - git checkout -b video2 video - -then you can add this 'v2' series to Patman with:: - - patman series add - -The second option is to get patman to create the new 'video2' branch in one -step:: - - patman inc - -The third option is to collect some tags using the 'patman status' command and -put them in a new branch:: - - patman status -d video2 - -One day the fourth option will be to ask patman to collect tags as part of the -'patman inc' command. - -Again, you do your edits, perhaps adding/removing patches, rebasing on -master -and so on. Then, send your v2:: - - patman series send - -Let's say the patches are accepted. You can use:: - - patch series gather - patch series progress - -to check, or:: - - patman series status -cC - -to see comments. You can now archive the series:: - - patman series archive - -At this point you have the basics. Some of the subcommands useful options, so -be sure to check out the help. - -Here is a sample 'progress' view: - -.. image:: pics/patman.jpg - :width: 800 - :alt: Patman showing the progress view - -General points --------------- - -#. When you change back to the us-cmd branch days or weeks later all your - information is still there, safely stored in the commits. You don't need - to remember what version you are up to, who you sent the last lot of patches - to, or anything about the change logs. -#. If you put tags in the subject, patman will Cc the maintainers - automatically in many cases. -#. If you want to keep the commits from each series you sent so that you can - compare change and see what you did, you can either create a new branch for - each version, or just tag the branch before you start changing it: - - .. code-block:: bash - - git tag sent/us-cmd-rfc - # ...later... - git tag sent/us-cmd-v2 - -#. If you want to modify the patches a little before sending, you can do - this in your editor, but be careful! -#. If you want to run git send-email yourself, use the -n flag which will - print out the command line patman would have used. -#. It is a good idea to add the change log info as you change the commit, - not later when you can't remember which patch you changed. You can always - go back and change or remove logs from commits. -#. Some mailing lists have size limits and when we add binary contents to - our patches it's easy to exceed the size limits. Use "--no-binary" to - generate patches without any binary contents. You are supposed to include - a link to a git repository in your "Commit-notes", "Series-notes" or - "Cover-letter" for maintainers to fetch the original commit. -#. Patches will have no changelog entries for revisions where they did not - change. For clarity, if there are no changes for this patch in the most - recent revision of the series, a note will be added. For example, a patch - with the following tags in the commit:: - - Series-version: 5 - Series-changes: 2 - - Some change - - Series-changes: 4 - - Another change - - would have a changelog of::: - - (no changes since v4) - - Changes in v4: - - Another change - - Changes in v2: - - Some change - - -Other thoughts --------------- - -This script has been split into sensible files but still needs work. -Most of these are indicated by a TODO in the code. - -It would be nice if this could handle the In-reply-to side of things. - -The tests are incomplete, as is customary. Use the 'test' subcommand to run -them: - -.. code-block:: bash - - $ tools/patman/patman test - -Note that since the test suite depends on data files only available in -the git checkout, the `test` command is hidden unless `patman` is -invoked from the U-Boot git repository. - -Alternatively, you can run the test suite via Pytest: - -.. code-block:: bash - - $ cd tools/patman && pytest - -Error handling doesn't always produce friendly error messages - e.g. -putting an incorrect tag in a commit may provide a confusing message. - -There might be a few other features not mentioned in this README. They -might be bugs. In particular, tags are case sensitive which is probably -a bad thing. diff --git a/tools/patman/project.py b/tools/patman/project.py deleted file mode 100644 index e633401e9d6..00000000000 --- a/tools/patman/project.py +++ /dev/null @@ -1,27 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# Copyright (c) 2012 The Chromium OS Authors. -# - -import os.path - -from u_boot_pylib import gitutil - -def detect_project(): - """Autodetect the name of the current project. - - This looks for signature files/directories that are unlikely to exist except - in the given project. - - Returns: - The name of the project, like "linux" or "u-boot". Returns "unknown" - if we can't detect the project. - """ - top_level = gitutil.get_top_level() - - if (not top_level or - os.path.exists(os.path.join(top_level, "include", "u-boot"))): - return "u-boot" - elif os.path.exists(os.path.join(top_level, "kernel")): - return "linux" - - return "unknown" diff --git a/tools/patman/pyproject.toml b/tools/patman/pyproject.toml deleted file mode 100644 index 0fc4b7d4ecd..00000000000 --- a/tools/patman/pyproject.toml +++ /dev/null @@ -1,29 +0,0 @@ -[build-system] -requires = ["setuptools>=78.1.1"] -build-backend = "setuptools.build_meta" - -[project] -name = "patch-manager" -version = "0.0.6" -authors = [ - { name="Simon Glass", email="[email protected]" }, -] -dependencies = ["u_boot_pylib >= 0.0.6", "aiohttp >= 3.9.1" ] -description = "Patman patch manager" -readme = "README.rst" -requires-python = ">=3.7" -classifiers = [ - "Programming Language :: Python :: 3", - "License :: OSI Approved :: GNU General Public License v2 or later (GPLv2+)", - "Operating System :: OS Independent", -] - -[project.urls] -"Homepage" = "https://docs.u-boot-project.org/en/latest/develop/patman.html" -"Bug Tracker" = "https://source.denx.de/groups/u-boot/-/issues" - -[project.scripts] -patman = "patman.__main__:run_patman" - -[tool.setuptools.package-data] -patman = ["*.rst"] diff --git a/tools/patman/pytest.ini b/tools/patman/pytest.ini deleted file mode 100644 index df3eb518d0f..00000000000 --- a/tools/patman/pytest.ini +++ /dev/null @@ -1,2 +0,0 @@ -[pytest] -addopts = --doctest-modules diff --git a/tools/patman/requirements.txt b/tools/patman/requirements.txt deleted file mode 100644 index d4fcb1061c2..00000000000 --- a/tools/patman/requirements.txt +++ /dev/null @@ -1,6 +0,0 @@ -aiohttp==3.10.11 -ConfigParser==7.1.0 -importlib_resources==6.5.2 -pygit2==1.14.1 -requests==2.32.4 -setuptools==78.1.1 diff --git a/tools/patman/send.py b/tools/patman/send.py deleted file mode 100644 index 08a916aff1a..00000000000 --- a/tools/patman/send.py +++ /dev/null @@ -1,197 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2025 Google LLC -# -"""Handles the 'send' subcommand -""" - -import os -import sys - -from patman import checkpatch -from patman import patchstream -from patman import settings -from u_boot_pylib import gitutil -from u_boot_pylib import terminal - - -def check_patches(series, patch_files, run_checkpatch, verbose, use_tree, cwd): - """Run some checks on a set of patches - - This santiy-checks the patman tags like Series-version and runs the patches - through checkpatch - - Args: - series (Series): Series object for this series (set of patches) - patch_files (list): List of patch filenames, each a string, e.g. - ['0001_xxx.patch', '0002_yyy.patch'] - run_checkpatch (bool): True to run checkpatch.pl - verbose (bool): True to print out every line of the checkpatch output as - it is parsed - use_tree (bool): If False we'll pass '--no-tree' to checkpatch. - cwd (str): Path to use for patch files (None to use current dir) - - Returns: - bool: True if the patches had no errors, False if they did - """ - # Do a few checks on the series - series.DoChecks() - - # Check the patches - if run_checkpatch: - ok = checkpatch.check_patches(verbose, patch_files, use_tree, cwd) - else: - ok = True - return ok - - -def email_patches(col, series, cover_fname, patch_files, process_tags, its_a_go, - ignore_bad_tags, add_maintainers, get_maintainer_script, limit, - dry_run, in_reply_to, thread, smtp_server, cwd=None): - """Email patches to the recipients - - This emails out the patches and cover letter using 'git send-email'. Each - patch is copied to recipients identified by the patch tag and output from - the get_maintainer.pl script. The cover letter is copied to all recipients - of any patch. - - To make this work a CC file is created holding the recipients for each patch - and the cover letter. See the main program 'cc_cmd' for this logic. - - Args: - col (terminal.Color): Colour output object - series (Series): Series object for this series (set of patches) - cover_fname (str): Filename of the cover letter as a string (None if - none) - patch_files (list): List of patch filenames, each a string, e.g. - ['0001_xxx.patch', '0002_yyy.patch'] - process_tags (bool): True to process subject tags in each patch, e.g. - for 'dm: spi: Add SPI support' this would be 'dm' and 'spi'. The - tags are looked up in the configured sendemail.aliasesfile and also - in ~/.patman (see README) - its_a_go (bool): True if we are going to actually send the patches, - False if the patches have errors and will not be sent unless - @ignore_errors - ignore_bad_tags (bool): True to just print a warning for unknown tags, - False to halt with an error - add_maintainers (bool): Run the get_maintainer.pl script for each patch - get_maintainer_script (str): The script used to retrieve which - maintainers to cc - limit (int): Limit on the number of people that can be cc'd on a single - patch or the cover letter (None if no limit) - dry_run (bool): Don't actually email the patches, just print out what - would be sent - in_reply_to (str): If not None we'll pass this to git as --in-reply-to. - Should be a message ID that this is in reply to. - thread (bool): True to add --thread to git send-email (make all patches - reply to cover-letter or first patch in series) - smtp_server (str): SMTP server to use to send patches (None for default) - cwd (str): Path to use for patch files (None to use current dir) - - Return: - Git command that was/would be run - """ - cc_file = series.MakeCcFile(process_tags, cover_fname, not ignore_bad_tags, - add_maintainers, limit, get_maintainer_script, - settings.alias, cwd) - - # Email the patches out (giving the user time to check / cancel) - cmd = '' - if its_a_go: - cmd = gitutil.email_patches( - series, cover_fname, patch_files, dry_run, not ignore_bad_tags, - cc_file, alias=settings.alias, in_reply_to=in_reply_to, - thread=thread, smtp_server=smtp_server, cwd=cwd) - else: - print(col.build(col.RED, "Not sending emails due to errors/warnings")) - - # For a dry run, just show our actions as a sanity check - if dry_run: - series.ShowActions(patch_files, cmd, process_tags, settings.alias) - if not its_a_go: - print(col.build(col.RED, "Email would not be sent")) - - os.remove(cc_file) - return cmd - - -def prepare_patches(col, branch, count, start, end, ignore_binary, signoff, - keep_change_id=False, git_dir=None, cwd=None): - """Figure out what patches to generate, then generate them - - The patch files are written to the current directory, e.g. 0001_xxx.patch - 0002_yyy.patch - - Args: - col (terminal.Color): Colour output object - branch (str): Branch to create patches from (None = current) - count (int): Number of patches to produce, or -1 to produce patches for - the current branch back to the upstream commit - start (int): Start patch to use (0=first / top of branch) - end (int): End patch to use (0=last one in series, 1=one before that, - etc.) - ignore_binary (bool): Don't generate patches for binary files - keep_change_id (bool): Preserve the Change-Id tag. - git_dir (str): Path to git repository (None to use default) - cwd (str): Path to use for git operations (None to use current dir) - - Returns: - Tuple: - Series object for this series (set of patches) - Filename of the cover letter as a string (None if none) - patch_files: List of patch filenames, each a string, e.g. - ['0001_xxx.patch', '0002_yyy.patch'] - """ - if count == -1: - # Work out how many patches to send if we can - count = (gitutil.count_commits_to_branch(branch, git_dir=git_dir) - - start) - - if not count: - msg = 'No commits found to process - please use -c flag, or run:\n' \ - ' git branch --set-upstream-to remote/branch' - sys.exit(col.build(col.RED, msg)) - - # Read the metadata from the commits - to_do = count - end - series = patchstream.get_metadata(branch, start, to_do, git_dir) - cover_fname, patch_files = gitutil.create_patches( - branch, start, to_do, ignore_binary, series, signoff, git_dir=git_dir, - cwd=cwd) - - # Fix up the patch files to our liking, and insert the cover letter - patchstream.fix_patches(series, patch_files, keep_change_id, - insert_base_commit=not cover_fname, cwd=cwd) - if cover_fname and series.get('cover'): - patchstream.insert_cover_letter(cover_fname, series, to_do, cwd=cwd) - return series, cover_fname, patch_files - - -def send(args, git_dir=None, cwd=None): - """Create, check and send patches by email - - Args: - args (argparse.Namespace): Arguments to patman - cwd (str): Path to use for git operations - - Return: - bool: True if the patches were likely sent, else False - """ - col = terminal.Color() - series, cover_fname, patch_files = prepare_patches( - col, args.branch, args.count, args.start, args.end, - args.ignore_binary, args.add_signoff, - keep_change_id=args.keep_change_id, git_dir=git_dir, cwd=cwd) - ok = check_patches(series, patch_files, args.check_patch, - args.verbose, args.check_patch_use_tree, cwd) - - ok = ok and gitutil.check_suppress_cc_config() - - its_a_go = ok or args.ignore_errors - cmd = email_patches( - col, series, cover_fname, patch_files, args.process_tags, - its_a_go, args.ignore_bad_tags, args.add_maintainers, - args.get_maintainer_script, args.limit, args.dry_run, - args.in_reply_to, args.thread, args.smtp_server, cwd=cwd) - - return cmd and its_a_go and not args.dry_run diff --git a/tools/patman/setup.py b/tools/patman/setup.py deleted file mode 100644 index bcaad69a1c2..00000000000 --- a/tools/patman/setup.py +++ /dev/null @@ -1,11 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -from setuptools import setup -setup(name='patman', - version='1.0', - scripts=['patman'], - packages=['patman'], - package_dir={'patman': ''}, - package_data={'patman': ['README.rst']}, - classifiers=['Environment :: Console', - 'Topic :: Software Development']) diff --git a/tools/patman/status.py b/tools/patman/status.py deleted file mode 100644 index 967fef3ad6e..00000000000 --- a/tools/patman/status.py +++ /dev/null @@ -1,405 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2020 Google LLC -# -"""Talks to the patchwork service to figure out what patches have been reviewed -and commented on. Provides a way to display review tags and comments. -Allows creation of a new branch based on the old but with the review tags -collected from patchwork. -""" - -import asyncio -from collections import defaultdict -import concurrent.futures -from itertools import repeat - -import aiohttp -import pygit2 - -from u_boot_pylib import terminal -from u_boot_pylib import tout -from patman import patchstream -from patman import patchwork - - -def process_reviews(content, comment_data, base_rtags): - """Process and return review data - - Args: - content (str): Content text of the patch itself - see pwork.get_patch() - comment_data (list of dict): Comments for the patch - see - pwork._get_patch_comments() - base_rtags (dict): base review tags (before any comments) - key: Response tag (e.g. 'Reviewed-by') - value: Set of people who gave that response, each a name/email - string - - Return: tuple: - dict: new review tags (noticed since the base_rtags) - key: Response tag (e.g. 'Reviewed-by') - value: Set of people who gave that response, each a name/email - string - list of patchwork.Review: reviews received on the patch - """ - pstrm = patchstream.PatchStream.process_text(content, True) - rtags = defaultdict(set) - for response, people in pstrm.commit.rtags.items(): - rtags[response].update(people) - - reviews = [] - for comment in comment_data: - pstrm = patchstream.PatchStream.process_text(comment['content'], True) - if pstrm.snippets: - submitter = comment['submitter'] - person = f"{submitter['name']} <{submitter['email']}>" - reviews.append(patchwork.Review(person, pstrm.snippets)) - for response, people in pstrm.commit.rtags.items(): - rtags[response].update(people) - - # Find the tags that are not in the commit - new_rtags = defaultdict(set) - for tag, people in rtags.items(): - for who in people: - is_new = (tag not in base_rtags or - who not in base_rtags[tag]) - if is_new: - new_rtags[tag].add(who) - return new_rtags, reviews - - -def compare_with_series(series, patches): - """Compare a list of patches with a series it came from - - This prints any problems as warnings - - Args: - series (Series): Series to compare against - patches (list of Patch): list of Patch objects to compare with - - Returns: - tuple - dict: - key: Commit number (0...n-1) - value: Patch object for that commit - dict: - key: Patch number (0...n-1) - value: Commit object for that patch - """ - # Check the names match - warnings = [] - patch_for_commit = {} - all_patches = set(patches) - for seq, cmt in enumerate(series.commits): - pmatch = [p for p in all_patches if p.subject == cmt.subject] - if len(pmatch) == 1: - patch_for_commit[seq] = pmatch[0] - all_patches.remove(pmatch[0]) - elif len(pmatch) > 1: - warnings.append("Multiple patches match commit %d ('%s'):\n %s" % - (seq + 1, cmt.subject, - '\n '.join([p.subject for p in pmatch]))) - else: - warnings.append("Cannot find patch for commit %d ('%s')" % - (seq + 1, cmt.subject)) - - # Check the names match - commit_for_patch = {} - all_commits = set(series.commits) - for seq, patch in enumerate(patches): - cmatch = [c for c in all_commits if c.subject == patch.subject] - if len(cmatch) == 1: - commit_for_patch[seq] = cmatch[0] - all_commits.remove(cmatch[0]) - elif len(cmatch) > 1: - warnings.append("Multiple commits match patch %d ('%s'):\n %s" % - (seq + 1, patch.subject, - '\n '.join([c.subject for c in cmatch]))) - else: - warnings.append("Cannot find commit for patch %d ('%s')" % - (seq + 1, patch.subject)) - - return patch_for_commit, commit_for_patch, warnings - - -def show_responses(col, rtags, indent, is_new): - """Show rtags collected - - Args: - col (terminal.Colour): Colour object to use - rtags (dict): review tags to show - key: Response tag (e.g. 'Reviewed-by') - value: Set of people who gave that response, each a name/email string - indent (str): Indentation string to write before each line - is_new (bool): True if this output should be highlighted - - Returns: - int: Number of review tags displayed - """ - count = 0 - for tag in sorted(rtags.keys()): - people = rtags[tag] - for who in sorted(people): - terminal.tprint(indent + '%s %s: ' % ('+' if is_new else ' ', tag), - newline=False, colour=col.GREEN, bright=is_new, - col=col) - terminal.tprint(who, colour=col.WHITE, bright=is_new, col=col) - count += 1 - return count - -def create_branch(series, new_rtag_list, branch, dest_branch, overwrite, - repo=None): - """Create a new branch with review tags added - - Args: - series (Series): Series object for the existing branch - new_rtag_list (list): List of review tags to add, one for each commit, - each a dict: - key: Response tag (e.g. 'Reviewed-by') - value: Set of people who gave that response, each a name/email - string - branch (str): Existing branch to update - dest_branch (str): Name of new branch to create - overwrite (bool): True to force overwriting dest_branch if it exists - repo (pygit2.Repository): Repo to use (use None unless testing) - - Returns: - int: Total number of review tags added across all commits - - Raises: - ValueError: if the destination branch name is the same as the original - branch, or it already exists and @overwrite is False - """ - if branch == dest_branch: - raise ValueError( - 'Destination branch must not be the same as the original branch') - if not repo: - repo = pygit2.Repository('.') - count = len(series.commits) - new_br = repo.branches.get(dest_branch) - if new_br: - if not overwrite: - raise ValueError("Branch '%s' already exists (-f to overwrite)" % - dest_branch) - new_br.delete() - if not branch: - branch = 'HEAD' - target = repo.revparse_single('%s~%d' % (branch, count)) - repo.branches.local.create(dest_branch, target) - - num_added = 0 - for seq in range(count): - parent = repo.branches.get(dest_branch) - cherry = repo.revparse_single('%s~%d' % (branch, count - seq - 1)) - - repo.merge_base(cherry.oid, parent.target) - base_tree = cherry.parents[0].tree - - index = repo.merge_trees(base_tree, parent, cherry) - tree_id = index.write_tree(repo) - - lines = [] - if new_rtag_list[seq]: - for tag, people in new_rtag_list[seq].items(): - for who in people: - lines.append('%s: %s' % (tag, who)) - num_added += 1 - message = patchstream.insert_tags(cherry.message.rstrip(), - sorted(lines)) - - repo.create_commit( - parent.name, cherry.author, cherry.committer, message, tree_id, - [parent.target]) - return num_added - - -def check_patch_count(num_commits, num_patches): - """Check the number of commits and patches agree - - Args: - num_commits (int): Number of commits - num_patches (int): Number of patches - """ - if num_patches != num_commits: - tout.warning(f'Warning: Patchwork reports {num_patches} patches, ' - f'series has {num_commits}') - - -def do_show_status(series, cover, patches, show_comments, show_cover_comments, - col, warnings_on_stderr=True): - """Check the status of a series on Patchwork - - This finds review tags and comments for a series in Patchwork, displaying - them to show what is new compared to the local series. - - Args: - series (Series): Series object for the existing branch - cover (COVER): Cover letter info, or None if none - patches (list of Patch): Patches sorted by sequence number - show_comments (bool): True to show the comments on each patch - show_cover_comments (bool): True to show the comments on the - letter - col (terminal.Colour): Colour object - - Return: tuple: - int: Number of new review tags to add - list: List of review tags to add, one item for each commit, each a - dict: - key: Response tag (e.g. 'Reviewed-by') - value: Set of people who gave that response, each a name/email - string - """ - compare = [] - for pw_patch in patches: - patch = patchwork.Patch(pw_patch.id) - patch.parse_subject(pw_patch.series_data['name']) - compare.append(patch) - - count = len(series.commits) - new_rtag_list = [None] * count - review_list = [None] * count - - with terminal.pager(): - patch_for_commit, _, warnings = compare_with_series(series, compare) - for warn in warnings: - tout.do_output(tout.WARNING if warnings_on_stderr else tout.INFO, - warn) - - for seq, pw_patch in enumerate(patches): - compare[seq].patch = pw_patch - - for i in range(count): - pat = patch_for_commit.get(i) - if pat: - patch_data = pat.patch.data - comment_data = pat.patch.comments - new_rtag_list[i], review_list[i] = process_reviews( - patch_data['content'], comment_data, - series.commits[i].rtags) - num_to_add = _do_show_status( - series, cover, patch_for_commit, show_comments, - show_cover_comments, new_rtag_list, review_list, col) - - return num_to_add, new_rtag_list - - -def _do_show_status(series, cover, patch_for_commit, show_comments, - show_cover_comments, new_rtag_list, review_list, col): - if cover and show_cover_comments: - terminal.tprint(f'Cov {cover.name}', colour=col.BLACK, col=col, - bright=False, back=col.YELLOW) - for seq, comment in enumerate(cover.comments): - submitter = comment['submitter'] - person = '%s <%s>' % (submitter['name'], submitter['email']) - terminal.tprint(f"From: {person}: {comment['date']}", - colour=col.RED, col=col) - print(comment['content']) - print() - - num_to_add = 0 - for seq, cmt in enumerate(series.commits): - patch = patch_for_commit.get(seq) - if not patch: - continue - terminal.tprint('%3d %s' % (patch.seq, patch.subject[:50]), - colour=col.YELLOW, col=col) - cmt = series.commits[seq] - base_rtags = cmt.rtags - new_rtags = new_rtag_list[seq] - - indent = ' ' * 2 - show_responses(col, base_rtags, indent, False) - num_to_add += show_responses(col, new_rtags, indent, True) - if show_comments: - for review in review_list[seq]: - terminal.tprint('Review: %s' % review.meta, colour=col.RED, - col=col) - for snippet in review.snippets: - for line in snippet: - quoted = line.startswith('>') - terminal.tprint( - f' {line}', - colour=col.MAGENTA if quoted else None, col=col) - terminal.tprint() - return num_to_add - - -def show_status(series, branch, dest_branch, force, cover, patches, - show_comments, show_cover_comments, test_repo=None): - """Check the status of a series on Patchwork - - This finds review tags and comments for a series in Patchwork, displaying - them to show what is new compared to the local series. - - Args: - client (aiohttp.ClientSession): Session to use - series (Series): Series object for the existing branch - branch (str): Existing branch to update, or None - dest_branch (str): Name of new branch to create, or None - force (bool): True to force overwriting dest_branch if it exists - cover (COVER): Cover letter info, or None if none - patches (list of Patch): Patches sorted by sequence number - show_comments (bool): True to show the comments on each patch - show_cover_comments (bool): True to show the comments on the letter - test_repo (pygit2.Repository): Repo to use (use None unless testing) - """ - col = terminal.Color() - check_patch_count(len(series.commits), len(patches)) - num_to_add, new_rtag_list = do_show_status( - series, cover, patches, show_comments, show_cover_comments, col) - - if not dest_branch and num_to_add: - msg = ' (use -d to write them to a new branch)' - else: - msg = '' - terminal.tprint( - f"{num_to_add} new response{'s' if num_to_add != 1 else ''} " - f'available in patchwork{msg}') - - if dest_branch: - num_added = create_branch(series, new_rtag_list, branch, - dest_branch, force, test_repo) - terminal.tprint( - f"{num_added} response{'s' if num_added != 1 else ''} added " - f"from patchwork into new branch '{dest_branch}'") - - -async def check_status(link, pwork, read_comments=False, - read_cover_comments=False): - """Set up an HTTP session and get the required state - - Args: - link (str): Patch series ID number - pwork (Patchwork): Patchwork object to use for reading - read_comments (bool): True to read comments and state for each patch - - Return: tuple: - COVER object, or None if none or not read_cover_comments - list of PATCH objects - """ - async with aiohttp.ClientSession() as client: - return await pwork.series_get_state(client, link, read_comments, - read_cover_comments) - - -def check_and_show_status(series, link, branch, dest_branch, force, - show_comments, show_cover_comments, pwork, - test_repo=None): - """Read the series status from patchwork and show it to the user - - Args: - series (Series): Series object for the existing branch - link (str): Patch series ID number - branch (str): Existing branch to update, or None - dest_branch (str): Name of new branch to create, or None - force (bool): True to force overwriting dest_branch if it exists - show_comments (bool): True to show the comments on each patch - show_cover_comments (bool): True to show the comments on the letter - pwork (Patchwork): Patchwork object to use for reading - test_repo (pygit2.Repository): Repo to use (use None unless testing) - """ - loop = asyncio.get_event_loop() - cover, patches = loop.run_until_complete(check_status( - link, pwork, True, show_cover_comments)) - - show_status(series, branch, dest_branch, force, cover, patches, - show_comments, show_cover_comments, test_repo=test_repo) diff --git a/tools/patman/test/0000-cover-letter.patch b/tools/patman/test/0000-cover-letter.patch deleted file mode 100644 index c99e635623f..00000000000 --- a/tools/patman/test/0000-cover-letter.patch +++ /dev/null @@ -1,23 +0,0 @@ -From 5ab48490f03051875ab13d288a4bf32b507d76fd Mon Sep 17 00:00:00 2001 -From: Simon Glass <[email protected]> -Date: Sat, 27 May 2017 20:52:11 -0600 -Subject: [RFC 0/2] *** SUBJECT HERE *** -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -*** BLURB HERE *** - -Simon Glass (2): - pci: Correct cast for sandbox - fdt: Correct cast for sandbox in fdtdec_setup_mem_size_base() - - cmd/pci.c | 3 ++- - fs/fat/fat.c | 1 + - lib/efi_loader/efi_memory.c | 1 + - lib/fdtdec.c | 3 ++- - 4 files changed, 6 insertions(+), 2 deletions(-) - --- -2.7.4 - diff --git a/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch b/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch deleted file mode 100644 index 038943c2c9b..00000000000 --- a/tools/patman/test/0001-pci-Correct-cast-for-sandbox.patch +++ /dev/null @@ -1,51 +0,0 @@ -From b9da5f937bd5ea4931ea17459bf79b2905d9594d Mon Sep 17 00:00:00 2001 -From: Simon Glass <[email protected]> -Date: Sat, 15 Apr 2017 15:39:08 -0600 -Subject: [RFC 1/2] pci: Correct cast for sandbox -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This gives a warning with some native compilers: - -cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type - ‘long long unsigned int’, but argument 3 has type - ‘u64 {aka long unsigned int}’ [-Wformat=] - -Fix it with a cast. - -Signed-off-by: Simon Glass <[email protected]> -Commit-changes: 2 -- Changes only for this commit - -Series-notes: -some notes -about some things -from the first commit -END - -Commit-notes: -Some notes about -the first commit -END ---- - cmd/pci.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/cmd/pci.c b/cmd/pci.c -index 41b4fff..fe27b4f 100644 ---- a/cmd/pci.c -+++ b/cmd/pci.c -@@ -150,7 +150,8 @@ int pci_bar_show(struct udevice *dev) - if ((!is_64 && size_low) || (is_64 && size)) { - size = ~size + 1; - printf(" %d %#016llx %#016llx %d %s %s\n", -- bar_id, base, size, is_64 ? 64 : 32, -+ bar_id, (unsigned long long)base, -+ (unsigned long long)size, is_64 ? 64 : 32, - is_io ? "I/O" : "MEM", - prefetchable ? "Prefetchable" : ""); - } --- -2.7.4 - diff --git a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch b/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch deleted file mode 100644 index 48ea1793b47..00000000000 --- a/tools/patman/test/0002-fdt-Correct-cast-for-sandbox-in-fdtdec_setup_mem_siz.patch +++ /dev/null @@ -1,85 +0,0 @@ -From 5ab48490f03051875ab13d288a4bf32b507d76fd Mon Sep 17 00:00:00 2001 -From: Simon Glass <[email protected]> -Date: Sat, 15 Apr 2017 15:39:08 -0600 -Subject: [RFC 2/2] fdt: Correct cast for sandbox in fdtdec_setup_mem_size_base() -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This gives a warning with some native compilers: - -lib/fdtdec.c:1203:8: warning: format ‘%llx’ expects argument of type - ‘long long unsigned int’, but argument 3 has type - ‘long unsigned int’ [-Wformat=] - -Fix it with a cast. - -Signed-off-by: Simon Glass <[email protected]> -Series-to: u-boot -Series-prefix: RFC -Series-cc: Stefan Brüns <[email protected]> -Cover-letter-cc: Lord Mëlchett <[email protected]> -Series-version: 3 -Patch-cc: fred -Commit-cc: joe -Series-process-log: sort, uniq -Commit-added-in: 4 -Series-changes: 4 -- Some changes -- Multi - line - change - -Commit-changes: 2 -- Changes only for this commit - -Cover-changes: 4 -- Some notes for the cover letter - -Cover-letter: -test: A test patch series -This is a test of how the cover -letter -works -END ---- - fs/fat/fat.c | 1 + - lib/efi_loader/efi_memory.c | 1 + - lib/fdtdec.c | 3 ++- - 3 files changed, 4 insertions(+), 1 deletion(-) - -diff --git a/fs/fat/fat.c b/fs/fat/fat.c -index a71bad1..ba169dc 100644 ---- a/fs/fat/fat.c -+++ b/fs/fat/fat.c -@@ -1,3 +1,4 @@ -+ - /* - * fat.c - * -diff --git a/lib/efi_loader/efi_memory.c b/lib/efi_loader/efi_memory.c -index db2ae19..05f75d1 100644 ---- a/lib/efi_loader/efi_memory.c -+++ b/lib/efi_loader/efi_memory.c -@@ -1,3 +1,4 @@ -+ - /* - * EFI application memory management - * -diff --git a/lib/fdtdec.c b/lib/fdtdec.c -index c072e54..942244f 100644 ---- a/lib/fdtdec.c -+++ b/lib/fdtdec.c -@@ -1200,7 +1200,8 @@ int fdtdec_setup_mem_size_base(void) - } - - gd->ram_size = (phys_size_t)(res.end - res.start + 1); -- debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size); -+ debug("%s: Initial DRAM size %llx\n", __func__, -+ (unsigned long long)gd->ram_size); - - return 0; - } --- -2.7.4 - diff --git a/tools/patman/test/test01.txt b/tools/patman/test/test01.txt deleted file mode 100644 index b2d73c5972c..00000000000 --- a/tools/patman/test/test01.txt +++ /dev/null @@ -1,72 +0,0 @@ -commit b9da5f937bd5ea4931ea17459bf79b2905d9594d -Author: Simon Glass <[email protected]> -Date: Sat Apr 15 15:39:08 2017 -0600 - - pci: Correct cast for sandbox - - This gives a warning with some native compilers: - - cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type - ‘long long unsigned int’, but argument 3 has type - ‘u64 {aka long unsigned int}’ [-Wformat=] - - Fix it with a cast. - - Signed-off-by: Simon Glass <[email protected]> - Commit-changes: 2 - - second revision change - - Series-notes: - some notes - about some things - from the first commit - END - - Commit-notes: - Some notes about - the first commit - END - -commit 5ab48490f03051875ab13d288a4bf32b507d76fd -Author: Simon Glass <[email protected]> -Date: Sat Apr 15 15:39:08 2017 -0600 - - fdt: Correct cast for sandbox in fdtdec_setup_mem_size_base() - - This gives a warning with some native compilers: - - lib/fdtdec.c:1203:8: warning: format ‘%llx’ expects argument of type - ‘long long unsigned int’, but argument 3 has type - ‘long unsigned int’ [-Wformat=] - - Fix it with a cast. - - Signed-off-by: Simon Glass <[email protected]> - Series-to: u-boot - Series-prefix: RFC - Series-postfix: some-branch - Series-cc: Stefan Brüns <[email protected]> - Cover-letter-cc: Lord Mëlchett <[email protected]> - Series-version: 3 - Patch-cc: fred - Commit-cc: joe - Series-process-log: sort, uniq - Commit-added-in: 4 - Series-changes: 4 - - Some changes - - Multi - line - change - - Commit-changes: 2 - - Changes only for this commit - - Cover-changes: 4 - - Some notes for the cover letter - - Cover-letter: - test: A test patch series - This is a test of how the cover - letter - works - END diff --git a/tools/patman/test_checkpatch.py b/tools/patman/test_checkpatch.py deleted file mode 100644 index b4722330f86..00000000000 --- a/tools/patman/test_checkpatch.py +++ /dev/null @@ -1,526 +0,0 @@ -# -*- coding: utf-8 -*- -# SPDX-License-Identifier: GPL-2.0+ -# -# Tests for U-Boot-specific checkpatch.pl features -# -# Copyright (c) 2011 The Chromium OS Authors. -# - -import os -import tempfile -import unittest - -from patman import checkpatch -from patman import patchstream -from patman import series -from patman import commit -from u_boot_pylib import gitutil - - -class Line: - """Single changed line in one file in a patch - - Args: - fname (str): Filename containing the added line - text (str): Text of the added line - """ - def __init__(self, fname, text): - self.fname = fname - self.text = text - - -class PatchMaker: - """Makes a patch for checking with checkpatch.pl - - The idea here is to create a patch which adds one line in one file, - intended to provoke a checkpatch error or warning. The base patch is empty - (i.e. invalid), so you should call add_line() to add at least one line. - """ - def __init__(self): - """Set up the PatchMaker object - - Properties: - lines (list of Line): List of lines to add to the patch. Note that - each line has both a file and some text associated with it, - since for simplicity we just add a single line for each file - """ - self.lines = [] - - def add_line(self, fname, text): - """Add to the list of filename/line pairs""" - self.lines.append(Line(fname, text)) - - def get_patch_text(self): - """Build the patch text - - Takes a base patch and adds a diffstat and patch for each filename/line - pair in the list. - - Returns: - str: Patch text ready for submission to checkpatch - """ - base = '''From 125b77450f4c66b8fd9654319520bbe795c9ef31 Mon Sep 17 00:00:00 2001 -From: Simon Glass <[email protected]> -Date: Sun, 14 Jun 2020 09:45:14 -0600 -Subject: [PATCH] Test commit - -This is a test commit. - -Signed-off-by: Simon Glass <[email protected]> ---- - -''' - lines = base.splitlines() - - # Create the diffstat - change = 0 - insert = 0 - for line in self.lines: - lines.append(' %s | 1 +' % line.fname) - change += 1 - insert += 1 - lines.append(' %d files changed, %d insertions(+)' % (change, insert)) - lines.append('') - - # Create the patch info for each file - for line in self.lines: - lines.append('diff --git a/%s b/%s' % (line.fname, line.fname)) - lines.append('index 7837d459f18..5ba7840f68e 100644') - lines.append('--- a/%s' % line.fname) - lines.append('+++ b/%s' % line.fname) - lines += ('''@@ -121,6 +121,7 @@ enum uclass_id { - UCLASS_W1, /* Dallas 1-Wire bus */ - UCLASS_W1_EEPROM, /* one-wire EEPROMs */ - UCLASS_WDT, /* Watchdog Timer driver */ -+%s - - UCLASS_COUNT, - UCLASS_INVALID = -1, -''' % line.text).splitlines() - lines.append('---') - lines.append('2.17.1') - - return '\n'.join(lines) - - def get_patch(self): - """Get the patch text and write it into a temporary file - - Returns: - str: Filename containing the patch - """ - inhandle, inname = tempfile.mkstemp() - infd = os.fdopen(inhandle, 'w') - infd.write(self.get_patch_text()) - infd.close() - return inname - - def run_checkpatch(self): - """Run checkpatch on the patch file - - Returns: - namedtuple containing: - ok: False=failure, True=ok - problems: List of problems, each a dict: - 'type'; error or warning - 'msg': text message - 'file' : filename - 'line': line number - errors: Number of errors - warnings: Number of warnings - checks: Number of checks - lines: Number of lines - stdout: Full output of checkpatch - """ - return checkpatch.check_patch(self.get_patch(), show_types=True) - - -class TestPatch(unittest.TestCase): - """Test the u_boot_line() function in checkpatch.pl""" - - def test_filter(self): - """Test basic filter operation""" - data=''' - -From 656c9a8c31fa65859d924cd21da920d6ba537fad Mon Sep 17 00:00:00 2001 -From: Simon Glass <[email protected]> -Date: Thu, 28 Apr 2011 09:58:51 -0700 -Subject: [PATCH (resend) 3/7] Tegra2: Add more clock support - -This adds functions to enable/disable clocks and reset to on-chip peripherals. - -cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type - ‘long long unsigned int’, but argument 3 has type - ‘u64 {aka long unsigned int}’ [-Wformat=] - -BUG=chromium-os:13875 -TEST=build U-Boot for Seaboard, boot - -Change-Id: I80fe1d0c0b7dd10aa58ce5bb1d9290b6664d5413 - -Review URL: http://codereview.chromium.org/6900006 - -Signed-off-by: Simon Glass <[email protected]> ---- - arch/arm/cpu/armv7/tegra2/Makefile | 2 +- - arch/arm/cpu/armv7/tegra2/ap20.c | 57 ++---- - arch/arm/cpu/armv7/tegra2/clock.c | 163 +++++++++++++++++ -''' - expected='''Message-Id: <19991231235959.0.I80fe1d0c0b7dd10aa58ce5bb1d9290b6664d5413@changeid> - - -From 656c9a8c31fa65859d924cd21da920d6ba537fad Mon Sep 17 00:00:00 2001 -From: Simon Glass <[email protected]> -Date: Thu, 28 Apr 2011 09:58:51 -0700 -Subject: [PATCH (resend) 3/7] Tegra2: Add more clock support - -This adds functions to enable/disable clocks and reset to on-chip peripherals. - -cmd/pci.c:152:11: warning: format ‘%llx’ expects argument of type - ‘long long unsigned int’, but argument 3 has type - ‘u64 {aka long unsigned int}’ [-Wformat=] - -Signed-off-by: Simon Glass <[email protected]> ---- - - arch/arm/cpu/armv7/tegra2/Makefile | 2 +- - arch/arm/cpu/armv7/tegra2/ap20.c | 57 ++---- - arch/arm/cpu/armv7/tegra2/clock.c | 163 +++++++++++++++++ -''' - out = '' - inhandle, inname = tempfile.mkstemp() - infd = os.fdopen(inhandle, 'w', encoding='utf-8') - infd.write(data) - infd.close() - - exphandle, expname = tempfile.mkstemp() - expfd = os.fdopen(exphandle, 'w', encoding='utf-8') - expfd.write(expected) - expfd.close() - - # Normally by the time we call fix_patch we've already collected - # metadata. Here, we haven't, but at least fake up something. - # Set the "count" to -1 which tells fix_patch to use a bogus/fixed - # time for generating the Message-Id. - com = commit.Commit('') - com.change_id = 'I80fe1d0c0b7dd10aa58ce5bb1d9290b6664d5413' - com.count = -1 - - patchstream.fix_patch(None, inname, series.Series(), com) - - rc = os.system('diff -u %s %s' % (inname, expname)) - self.assertEqual(rc, 0) - os.remove(inname) - - # Test whether the keep_change_id settings works. - inhandle, inname = tempfile.mkstemp() - infd = os.fdopen(inhandle, 'w', encoding='utf-8') - infd.write(data) - infd.close() - - patchstream.fix_patch(None, inname, series.Series(), com, - keep_change_id=True) - - with open(inname, 'r') as f: - content = f.read() - self.assertIn( - 'Change-Id: I80fe1d0c0b7dd10aa58ce5bb1d9290b6664d5413', - content) - - os.remove(inname) - os.remove(expname) - - def get_data(self, data_type): - data='''From 4924887af52713cabea78420eff03badea8f0035 Mon Sep 17 00:00:00 2001 -From: Simon Glass <[email protected]> -Date: Thu, 7 Apr 2011 10:14:41 -0700 -Subject: [PATCH 1/4] Add microsecond boot time measurement - -This defines the basics of a new boot time measurement feature. This allows -logging of very accurate time measurements as the boot proceeds, by using -an available microsecond counter. - -%s ---- - README | 11 ++++++++ - MAINTAINERS | 3 ++ - common/bootstage.c | 50 ++++++++++++++++++++++++++++++++++++ - include/bootstage.h | 71 +++++++++++++++++++++++++++++++++++++++++++++++++++ - include/common.h | 8 ++++++ - 5 files changed, 141 insertions(+), 0 deletions(-) - create mode 100644 common/bootstage.c - create mode 100644 include/bootstage.h - -diff --git a/README b/README -index 6f3748d..f9e4e65 100644 ---- a/README -+++ b/README -@@ -2026,6 +2026,17 @@ The following options need to be configured: - example, some LED's) on your board. At the moment, - the following checkpoints are implemented: - -+- Time boot progress -+ CONFIG_BOOTSTAGE -+ -+ Define this option to enable microsecond boot stage timing -+ on supported platforms. For this to work your platform -+ needs to define a function timer_get_us() which returns the -+ number of microseconds since reset. This would normally -+ be done in your SOC or board timer.c file. -+ -+ You can add calls to bootstage_mark() to set time markers. -+ - - Standalone program support: - CONFIG_STANDALONE_LOAD_ADDR - -diff --git a/MAINTAINERS b/MAINTAINERS -index b167b028ec..beb7dc634f 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -474,3 +474,8 @@ S: Maintained - T: git git://git.denx.de/u-boot.git - F: * - F: */ -+ -+BOOTSTAGE -+M: Simon Glass <[email protected]> -+L: [email protected] -+F: common/bootstage.c -diff --git a/common/bootstage.c b/common/bootstage.c -new file mode 100644 -index 0000000..2234c87 ---- /dev/null -+++ b/common/bootstage.c -@@ -0,0 +1,37 @@ -+%s -+/* -+ * Copyright (c) 2011, Google Inc. All rights reserved. -+ * -+ */ -+ -+/* -+ * This module records the progress of boot and arbitrary commands, and -+ * permits accurate timestamping of each. The records can optionally be -+ * passed to kernel in the ATAGs -+ */ -+ -+#include <config.h> -+ -+struct bootstage_record { -+ u32 time_us; -+ const char *name; -+}; -+ -+static struct bootstage_record record[BOOTSTAGE_COUNT]; -+ -+u32 bootstage_mark(enum bootstage_id id, const char *name) -+{ -+ struct bootstage_record *rec = &record[id]; -+ -+ /* Only record the first event for each */ -+%sif (!rec->name) { -+ rec->time_us = (u32)timer_get_us(); -+ rec->name = name; -+ } -+ if (!rec->name && -+ %ssomething_else) { -+ rec->time_us = (u32)timer_get_us(); -+ rec->name = name; -+ } -+%sreturn rec->time_us; -+} --- -1.7.3.1 -''' - signoff = 'Signed-off-by: Simon Glass <[email protected]>\n' - license = '// SPDX-License-Identifier: GPL-2.0+' - tab = ' ' - indent = ' ' - if data_type == 'good': - pass - elif data_type == 'no-signoff': - signoff = '' - elif data_type == 'no-license': - license = '' - elif data_type == 'spaces': - tab = ' ' - elif data_type == 'indent': - indent = tab - else: - print('not implemented') - return data % (signoff, license, tab, indent, tab) - - def setup_data(self, data_type): - inhandle, inname = tempfile.mkstemp() - infd = os.fdopen(inhandle, 'w') - data = self.get_data(data_type) - infd.write(data) - infd.close() - return inname - - def test_good(self): - """Test checkpatch operation""" - inf = self.setup_data('good') - result = checkpatch.check_patch(inf) - self.assertEqual(result.ok, True) - self.assertEqual(result.problems, []) - self.assertEqual(result.errors, 0) - self.assertEqual(result.warnings, 0) - self.assertEqual(result.checks, 0) - self.assertEqual(result.lines, 62) - os.remove(inf) - - def test_no_signoff(self): - inf = self.setup_data('no-signoff') - result = checkpatch.check_patch(inf) - self.assertEqual(result.ok, False) - self.assertEqual(len(result.problems), 1) - self.assertEqual(result.errors, 1) - self.assertEqual(result.warnings, 0) - self.assertEqual(result.checks, 0) - self.assertEqual(result.lines, 62) - os.remove(inf) - - def test_no_license(self): - inf = self.setup_data('no-license') - result = checkpatch.check_patch(inf) - self.assertEqual(result.ok, False) - self.assertEqual(len(result.problems), 1) - self.assertEqual(result.errors, 0) - self.assertEqual(result.warnings, 1) - self.assertEqual(result.checks, 0) - self.assertEqual(result.lines, 62) - os.remove(inf) - - def test_spaces(self): - inf = self.setup_data('spaces') - result = checkpatch.check_patch(inf) - self.assertEqual(result.ok, False) - self.assertEqual(len(result.problems), 3) - self.assertEqual(result.errors, 0) - self.assertEqual(result.warnings, 3) - self.assertEqual(result.checks, 0) - self.assertEqual(result.lines, 62) - os.remove(inf) - - def test_indent(self): - inf = self.setup_data('indent') - result = checkpatch.check_patch(inf) - self.assertEqual(result.ok, False) - self.assertEqual(len(result.problems), 1) - self.assertEqual(result.errors, 0) - self.assertEqual(result.warnings, 0) - self.assertEqual(result.checks, 1) - self.assertEqual(result.lines, 62) - os.remove(inf) - - def check_single_message(self, pm, msg, pmtype = 'warning'): - """Helper function to run checkpatch and check the result - - Args: - pm: PatchMaker object to use - msg: Expected message (e.g. 'LIVETREE') - pmtype: Type of problem ('error', 'warning') - """ - result = pm.run_checkpatch() - if pmtype == 'warning': - self.assertEqual(result.warnings, 1) - elif pmtype == 'error': - self.assertEqual(result.errors, 1) - if len(result.problems) != 1: - print(result.problems) - self.assertEqual(len(result.problems), 1) - self.assertIn(msg, result.problems[0]['cptype']) - - def test_uclass(self): - """Test for possible new uclass""" - pm = PatchMaker() - pm.add_line('include/dm/uclass-id.h', 'UCLASS_WIBBLE,') - self.check_single_message(pm, 'NEW_UCLASS') - - def test_livetree(self): - """Test for using the livetree API""" - pm = PatchMaker() - pm.add_line('common/main.c', 'fdtdec_do_something()') - self.check_single_message(pm, 'LIVETREE') - - def test_new_command(self): - """Test for adding a new command""" - pm = PatchMaker() - pm.add_line('common/main.c', 'do_wibble(struct cmd_tbl *cmd_tbl)') - self.check_single_message(pm, 'CMD_TEST') - - def test_prefer_if(self): - """Test for using #ifdef""" - pm = PatchMaker() - pm.add_line('common/main.c', '#ifdef CONFIG_YELLOW') - pm.add_line('common/init.h', '#ifdef CONFIG_YELLOW') - pm.add_line('fred.dtsi', '#ifdef CONFIG_YELLOW') - self.check_single_message(pm, "PREFER_IF") - - def test_command_use_defconfig(self): - """Test for enabling/disabling commands using preprocesor""" - pm = PatchMaker() - pm.add_line('common/main.c', '#undef CONFIG_CMD_WHICH') - self.check_single_message(pm, 'DEFINE_CONFIG_SYM', 'error') - - def test_barred_include_in_hdr(self): - """Test for using a barred include in a header file""" - pm = PatchMaker() - pm.add_line('include/myfile.h', '#include <dm.h>') - self.check_single_message(pm, 'BARRED_INCLUDE_IN_HDR', 'error') - - def test_barred_include_common_h(self): - """Test for adding common.h to a file""" - pm = PatchMaker() - pm.add_line('include/myfile.h', '#include <common.h>') - self.check_single_message(pm, 'BARRED_INCLUDE_COMMON_H', 'error') - - def test_config_is_enabled_config(self): - """Test for accidental CONFIG_IS_ENABLED(CONFIG_*) calls""" - pm = PatchMaker() - pm.add_line('common/main.c', 'if (CONFIG_IS_ENABLED(CONFIG_CLK))') - self.check_single_message(pm, 'CONFIG_IS_ENABLED_CONFIG', 'error') - - def check_struct(self, auto, suffix, warning): - """Check one of the warnings for struct naming - - Args: - auto: Auto variable name, e.g. 'per_child_auto' - suffix: Suffix to expect on member, e.g. '_priv' - warning: Warning name, e.g. 'PRIV_AUTO' - """ - pm = PatchMaker() - pm.add_line('common/main.c', '.%s = sizeof(struct(fred)),' % auto) - pm.add_line('common/main.c', '.%s = sizeof(struct(mary%s)),' % - (auto, suffix)) - self.check_single_message( - pm, warning, "struct 'fred' should have a %s suffix" % suffix) - - def test_dm_driver_auto(self): - """Check for the correct suffix on 'struct driver' auto members""" - self.check_struct('priv_auto', '_priv', 'PRIV_AUTO') - self.check_struct('plat_auto', '_plat', 'PLAT_AUTO') - self.check_struct('per_child_auto', '_priv', 'CHILD_PRIV_AUTO') - self.check_struct('per_child_plat_auto', '_plat', 'CHILD_PLAT_AUTO') - - def test_dm_uclass_auto(self): - """Check for the correct suffix on 'struct uclass' auto members""" - # Some of these are omitted since they match those from struct driver - self.check_struct('per_device_auto', '_priv', 'DEVICE_PRIV_AUTO') - self.check_struct('per_device_plat_auto', '_plat', 'DEVICE_PLAT_AUTO') - - def check_strl(self, func): - """Check one of the checks for strn(cpy|cat)""" - pm = PatchMaker() - pm.add_line('common/main.c', "strn%s(foo, bar, sizeof(foo));" % func) - self.check_single_message(pm, "STRL", - "strl%s is preferred over strn%s because it always produces a nul-terminated string\n" - % (func, func)) - - def test_strl(self): - """Check for uses of strn(cat|cpy)""" - self.check_strl("cat"); - self.check_strl("cpy"); - -if __name__ == "__main__": - unittest.main() diff --git a/tools/patman/test_common.py b/tools/patman/test_common.py deleted file mode 100644 index 7da995dda22..00000000000 --- a/tools/patman/test_common.py +++ /dev/null @@ -1,254 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright 2025 Simon Glass <[email protected]> -# -"""Functional tests for checking that patman behaves correctly""" - -import os -import shutil -import tempfile - -import pygit2 - -from u_boot_pylib import gitutil -from u_boot_pylib import terminal -from u_boot_pylib import tools -from u_boot_pylib import tout - - -class TestCommon: - """Contains common test functions""" - leb = (b'Lord Edmund Blackadd\xc3\xabr <[email protected]>'. - decode('utf-8')) - - # Fake patchwork project ID for U-Boot - PROJ_ID = 6 - PROJ_LINK_NAME = 'uboot' - SERIES_ID_FIRST_V3 = 31 - SERIES_ID_SECOND_V1 = 456 - SERIES_ID_SECOND_V2 = 457 - TITLE_SECOND = 'Series for my board' - - verbosity = False - preserve_outdirs = False - - @classmethod - def setup_test_args(cls, preserve_indir=False, preserve_outdirs=False, - toolpath=None, verbosity=None, no_capture=False): - """Accept arguments controlling test execution - - Args: - preserve_indir (bool): not used by patman - preserve_outdirs (bool): Preserve the output directories used by - tests. Each test has its own, so this is normally only useful - when running a single test. - toolpath (str): not used by patman - verbosity (int): verbosity to use (0 means tout.INIT, 1 means means - tout.DEBUG) - no_capture (bool): True to output all captured text after capturing - completes - """ - del preserve_indir - cls.preserve_outdirs = preserve_outdirs - cls.toolpath = toolpath - cls.verbosity = verbosity - cls.no_capture = no_capture - - def __init__(self): - super().__init__() - self.repo = None - self.tmpdir = None - self.gitdir = None - - def setUp(self): - """Set up the test temporary dir and git dir""" - self.tmpdir = tempfile.mkdtemp(prefix='patman.') - self.gitdir = os.path.join(self.tmpdir, '.git') - tout.init(tout.DEBUG if self.verbosity else tout.INFO, - allow_colour=False) - - def tearDown(self): - """Delete the temporary dir""" - if self.preserve_outdirs: - print(f'Output dir: {self.tmpdir}') - else: - shutil.rmtree(self.tmpdir) - terminal.set_print_test_mode(False) - - def make_commit_with_file(self, subject, body, fname, text): - """Create a file and add it to the git repo with a new commit - - Args: - subject (str): Subject for the commit - body (str): Body text of the commit - fname (str): Filename of file to create - text (str): Text to put into the file - """ - path = os.path.join(self.tmpdir, fname) - tools.write_file(path, text, binary=False) - index = self.repo.index - index.add(fname) - # pylint doesn't seem to find this - # pylint: disable=E1101 - author = pygit2.Signature('Test user', '[email protected]') - committer = author - tree = index.write_tree() - message = subject + '\n' + body - self.repo.create_commit('HEAD', author, committer, message, tree, - [self.repo.head.target]) - - def make_git_tree(self): - """Make a simple git tree suitable for testing - - It has four branches: - 'base' has two commits: PCI, main - 'first' has base as upstream and two more commits: I2C, SPI - 'second' has base as upstream and three more: video, serial, bootm - 'third4' has second as upstream and four more: usb, main, test, lib - - Returns: - pygit2.Repository: repository - """ - os.environ['GIT_CONFIG_GLOBAL'] = '/dev/null' - os.environ['GIT_CONFIG_SYSTEM'] = '/dev/null' - - repo = pygit2.init_repository(self.gitdir) - self.repo = repo - new_tree = repo.TreeBuilder().write() - - common = ['git', f'--git-dir={self.gitdir}', 'config'] - tools.run(*(common + ['user.name', 'Dummy']), cwd=self.gitdir) - tools.run(*(common + ['user.email', '[email protected]']), - cwd=self.gitdir) - - # pylint doesn't seem to find this - # pylint: disable=E1101 - author = pygit2.Signature('Test user', '[email protected]') - committer = author - _ = repo.create_commit('HEAD', author, committer, 'Created master', - new_tree, []) - - self.make_commit_with_file('Initial commit', ''' -Add a README - -''', 'README', '''This is the README file -describing this project -in very little detail''') - - self.make_commit_with_file('pci: PCI implementation', ''' -Here is a basic PCI implementation - -''', 'pci.c', '''This is a file -it has some contents -and some more things''') - self.make_commit_with_file('main: Main program', ''' -Hello here is the second commit. -''', 'main.c', '''This is the main file -there is very little here -but we can always add more later -if we want to - -Series-to: u-boot -Series-cc: Barry Crump <[email protected]> -''') - base_target = repo.revparse_single('HEAD') - self.make_commit_with_file('i2c: I2C things', ''' -This has some stuff to do with I2C -''', 'i2c.c', '''And this is the file contents -with some I2C-related things in it''') - self.make_commit_with_file('spi: SPI fixes', f''' -SPI needs some fixes -and here they are - -Signed-off-by: {self.leb} - -Series-to: u-boot -Commit-notes: -title of the series -This is the cover letter for the series -with various details -END -''', 'spi.c', '''Some fixes for SPI in this -file to make SPI work -better than before''') - first_target = repo.revparse_single('HEAD') - - target = repo.revparse_single('HEAD~2') - # pylint doesn't seem to find this - # pylint: disable=E1101 - repo.reset(target.oid, pygit2.enums.ResetMode.HARD) - self.make_commit_with_file('video: Some video improvements', ''' -Fix up the video so that -it looks more purple. Purple is -a very nice colour. -''', 'video.c', '''More purple here -Purple and purple -Even more purple -Could not be any more purple''') - self.make_commit_with_file('serial: Add a serial driver', f''' -Here is the serial driver -for my chip. - -Cover-letter: -{self.TITLE_SECOND} -This series implements support -for my glorious board. -END -Series-to: u-boot -Series-links: {self.SERIES_ID_SECOND_V1} -''', 'serial.c', '''The code for the -serial driver is here''') - self.make_commit_with_file('bootm: Make it boot', ''' -This makes my board boot -with a fix to the bootm -command -''', 'bootm.c', '''Fix up the bootm -command to make the code as -complicated as possible''') - second_target = repo.revparse_single('HEAD') - - self.make_commit_with_file('usb: Try out the new DMA feature', ''' -This is just a fix that -ensures that DMA is enabled -''', 'usb-uclass.c', '''Here is the USB -implementation and as you can see it -it very nice''') - self.make_commit_with_file('main: Change to the main program', ''' -Here we adjust the main -program just a little bit -''', 'main.c', '''This is the text of the main program''') - self.make_commit_with_file('test: Check that everything works', ''' -This checks that all the -various things we've been -adding actually work. -''', 'test.c', '''Here is the test code and it seems OK''') - self.make_commit_with_file('lib: Sort out the extra library', ''' -The extra library is currently -broken. Fix it so that we can -use it in various place. -''', 'lib.c', '''Some library code is here -and a little more''') - third_target = repo.revparse_single('HEAD') - - repo.branches.local.create('first', first_target) - repo.config.set_multivar('branch.first.remote', '', '.') - repo.config.set_multivar('branch.first.merge', '', 'refs/heads/base') - - repo.branches.local.create('second', second_target) - repo.config.set_multivar('branch.second.remote', '', '.') - repo.config.set_multivar('branch.second.merge', '', 'refs/heads/base') - - repo.branches.local.create('base', base_target) - - repo.branches.local.create('third4', third_target) - repo.config.set_multivar('branch.third4.remote', '', '.') - repo.config.set_multivar('branch.third4.merge', '', - 'refs/heads/second') - - target = repo.lookup_reference('refs/heads/first') - repo.checkout(target, strategy=pygit2.GIT_CHECKOUT_FORCE) - target = repo.revparse_single('HEAD') - repo.reset(target.oid, pygit2.enums.ResetMode.HARD) - - self.assertFalse(gitutil.check_dirty(self.gitdir, self.tmpdir)) - return repo diff --git a/tools/patman/test_cseries.py b/tools/patman/test_cseries.py deleted file mode 100644 index 4c211c8ee89..00000000000 --- a/tools/patman/test_cseries.py +++ /dev/null @@ -1,3684 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ - -# Copyright 2025 Simon Glass <[email protected]> -# -"""Functional tests for checking that patman behaves correctly""" - -import asyncio -from datetime import datetime -import os -import re -import unittest -from unittest import mock - -import pygit2 - -from u_boot_pylib import cros_subprocess -from u_boot_pylib import gitutil -from u_boot_pylib import terminal -from u_boot_pylib import tools -from patman import cmdline -from patman import control -from patman import cser_helper -from patman import cseries -from patman.database import Pcommit -from patman import database -from patman import patchstream -from patman.patchwork import Patchwork -from patman.test_common import TestCommon - -HASH_RE = r'[0-9a-f]+' -#pylint: disable=protected-access - -class Namespace: - """Simple namespace for use instead of argparse in tests""" - def __init__(self, **kwargs): - self.__dict__.update(kwargs) - - -class TestCseries(unittest.TestCase, TestCommon): - """Test cases for the Cseries class - - In some cases there are tests for both direct Cseries calls and for - accessing the feature via the cmdline. It is possible to do this with mocks - but it is a bit painful to catch all cases that way. The approach here is - to create a check_...() function which yields back to the test routines to - make the call or run the command. The check_...() function typically yields - a Cseries while it is working and False when it is done, allowing the test - to check that everything is finished. - - Some subcommands don't have command tests, if it would be duplicative. Some - tests avoid using the check_...() function and just write the test out - twice, if it would be too confusing to use a coroutine. - - Note the -N flag which sort-of disables capturing of output, although in - fact it is still captured, just output at the end. When debugging the code - you may need to temporarily comment out the 'with terminal.capture()' - parts. - """ - def setUp(self): - TestCommon.setUp(self) - self.autolink_extra = None - self.loop = asyncio.get_event_loop() - self.cser = None - - def tearDown(self): - TestCommon.tearDown(self) - - class _Stage: - def __init__(self, name): - self.name = name - - def __enter__(self): - if not terminal.USE_CAPTURE: - print(f"--- starting '{self.name}'") - - def __exit__(self, exc_type, exc_val, exc_tb): - if not terminal.USE_CAPTURE: - print(f"--- finished '{self.name}'\n") - - def stage(self, name): - """Context manager to count requests across a range of patchwork calls - - Args: - name (str): Stage name - - Return: - _Stage: contect object - - Usage: - with self.stage('name'): - ...do things - - Note that the output only appears if the -N flag is used - """ - return self._Stage(name) - - def assert_finished(self, itr): - """Assert that an iterator is finished - - Args: - itr (iter): Iterator to check - """ - self.assertFalse(list(itr)) - - def test_database_setup(self): - """Check setting up of the series database""" - cser = cseries.Cseries(self.tmpdir) - with terminal.capture() as (_, err): - cser.open_database() - self.assertEqual(f'Creating new database {self.tmpdir}/.patman.db', - err.getvalue().strip()) - res = cser.db.execute("SELECT name FROM series") - self.assertTrue(res) - cser.close_database() - - def get_database(self): - """Open the database and silence the warning output - - Return: - Cseries: Resulting Cseries object - """ - cser = cseries.Cseries(self.tmpdir, terminal.COLOR_NEVER) - with terminal.capture() as _: - cser.open_database() - self.cser = cser - return cser - - def get_cser(self): - """Set up a git tree and database - - Return: - Cseries: object - """ - self.make_git_tree() - return self.get_database() - - def db_close(self): - """Close the database if open""" - if self.cser and self.cser.db.cur: - self.cser.close_database() - return True - return False - - def db_open(self): - """Open the database if closed""" - if self.cser and not self.cser.db.cur: - self.cser.open_database() - - def run_args(self, *argv, expect_ret=0, pwork=None, cser=None): - """Run patman with the given arguments - - Args: - argv (list of str): List of arguments, excluding 'patman' - expect_ret (int): Expected return code, used to check errors - pwork (Patchwork): Patchwork object to use when executing the - command, or None to create one - cser (Cseries): Cseries object to use when executing the command, - or None to create one - """ - was_open = self.db_close() - args = cmdline.parse_args(['-D'] + list(argv), config_fname=False) - exit_code = control.do_patman(args, self.tmpdir, pwork, cser) - self.assertEqual(expect_ret, exit_code) - if was_open: - self.db_open() - - def test_series_add(self): - """Test adding a new cseries""" - cser = self.get_cser() - self.assertFalse(cser.db.series_get_dict()) - - with terminal.capture() as (out, _): - cser.add('first', 'my description', allow_unmarked=True) - lines = out.getvalue().strip().splitlines() - self.assertEqual( - "Adding series 'first' v1: mark False allow_unmarked True", - lines[0]) - self.assertEqual("Added series 'first' v1 (2 commits)", lines[1]) - self.assertEqual(2, len(lines)) - - slist = cser.db.series_get_dict() - self.assertEqual(1, len(slist)) - self.assertEqual('first', slist['first'].name) - self.assertEqual('my description', slist['first'].desc) - - svlist = cser.get_ser_ver_list() - self.assertEqual(1, len(svlist)) - self.assertEqual(1, svlist[0].idnum) - self.assertEqual(1, svlist[0].series_id) - self.assertEqual(1, svlist[0].version) - - pclist = cser.get_pcommit_dict() - self.assertEqual(2, len(pclist)) - self.assertIn(1, pclist) - self.assertEqual( - Pcommit(1, 0, 'i2c: I2C things', 1, None, None, None, None), - pclist[1]) - self.assertEqual( - Pcommit(2, 1, 'spi: SPI fixes', 1, None, None, None, None), - pclist[2]) - - def test_series_not_checked_out(self): - """Test adding a new cseries when a different one is checked out""" - cser = self.get_cser() - self.assertFalse(cser.db.series_get_dict()) - - with terminal.capture() as (out, _): - cser.add('second', allow_unmarked=True) - lines = out.getvalue().strip().splitlines() - self.assertEqual( - "Adding series 'second' v1: mark False allow_unmarked True", - lines[0]) - self.assertEqual("Added series 'second' v1 (3 commits)", lines[1]) - self.assertEqual(2, len(lines)) - - def test_series_add_manual(self): - """Test adding a new cseries with a version number""" - cser = self.get_cser() - self.assertFalse(cser.db.series_get_dict()) - - repo = pygit2.init_repository(self.gitdir) - first_target = repo.revparse_single('first') - repo.branches.local.create('first2', first_target) - repo.config.set_multivar('branch.first2.remote', '', '.') - repo.config.set_multivar('branch.first2.merge', '', 'refs/heads/base') - - with terminal.capture() as (out, _): - cser.add('first2', 'description', allow_unmarked=True) - lines = out.getvalue().splitlines() - self.assertEqual( - "Adding series 'first' v2: mark False allow_unmarked True", - lines[0]) - self.assertEqual("Added series 'first' v2 (2 commits)", lines[1]) - self.assertEqual(2, len(lines)) - - slist = cser.db.series_get_dict() - self.assertEqual(1, len(slist)) - self.assertEqual('first', slist['first'].name) - - # We should have just one entry, with version 2 - svlist = cser.get_ser_ver_list() - self.assertEqual(1, len(svlist)) - self.assertEqual(1, svlist[0].idnum) - self.assertEqual(1, svlist[0].series_id) - self.assertEqual(2, svlist[0].version) - - def add_first2(self, checkout): - """Add a new first2 branch, a copy of first""" - repo = pygit2.init_repository(self.gitdir) - first_target = repo.revparse_single('first') - repo.branches.local.create('first2', first_target) - repo.config.set_multivar('branch.first2.remote', '', '.') - repo.config.set_multivar('branch.first2.merge', '', 'refs/heads/base') - - if checkout: - target = repo.lookup_reference('refs/heads/first2') - repo.checkout(target, strategy=pygit2.enums.CheckoutStrategy.FORCE) - - def test_series_add_different(self): - """Test adding a different version of a series from that checked out""" - cser = self.get_cser() - - self.add_first2(True) - - # Add first2 initially - with terminal.capture() as (out, _): - cser.add(None, 'description', allow_unmarked=True) - lines = out.getvalue().splitlines() - self.assertEqual( - "Adding series 'first' v2: mark False allow_unmarked True", - lines[0]) - self.assertEqual("Added series 'first' v2 (2 commits)", lines[1]) - self.assertEqual(2, len(lines)) - - # Now add first: it should be added as a new version - with terminal.capture() as (out, _): - cser.add('first', 'description', allow_unmarked=True) - lines = out.getvalue().splitlines() - self.assertEqual( - "Adding series 'first' v1: mark False allow_unmarked True", - lines[0]) - self.assertEqual( - "Added v1 to existing series 'first' (2 commits)", lines[1]) - self.assertEqual(2, len(lines)) - - slist = cser.db.series_get_dict() - self.assertEqual(1, len(slist)) - self.assertEqual('first', slist['first'].name) - - # We should have two entries, one of each version - svlist = cser.get_ser_ver_list() - self.assertEqual(2, len(svlist)) - self.assertEqual(1, svlist[0].idnum) - self.assertEqual(1, svlist[0].series_id) - self.assertEqual(2, svlist[0].version) - - self.assertEqual(2, svlist[1].idnum) - self.assertEqual(1, svlist[1].series_id) - self.assertEqual(1, svlist[1].version) - - def test_series_add_dup(self): - """Test adding a series twice""" - cser = self.get_cser() - with terminal.capture() as (out, _): - cser.add(None, 'description', allow_unmarked=True) - - with terminal.capture() as (out, _): - cser.add(None, 'description', allow_unmarked=True) - self.assertIn("Series 'first' v1 already exists", - out.getvalue().strip()) - - self.add_first2(False) - - with terminal.capture() as (out, _): - cser.add('first2', 'description', allow_unmarked=True) - lines = out.getvalue().splitlines() - self.assertEqual( - "Added v2 to existing series 'first' (2 commits)", lines[1]) - - def test_series_add_dup_reverse(self): - """Test adding a series twice, v2 then v1""" - cser = self.get_cser() - self.add_first2(True) - with terminal.capture() as (out, _): - cser.add(None, 'description', allow_unmarked=True) - self.assertIn("Added series 'first' v2", out.getvalue().strip()) - - with terminal.capture() as (out, _): - cser.add('first', 'description', allow_unmarked=True) - self.assertIn("Added v1 to existing series 'first'", - out.getvalue().strip()) - - def test_series_add_dup_reverse_cmdline(self): - """Test adding a series twice, v2 then v1""" - cser = self.get_cser() - self.add_first2(True) - with terminal.capture() as (out, _): - self.run_args('series', 'add', '-M', '-D', 'description', - pwork=True) - self.assertIn("Added series 'first' v2 (2 commits)", - out.getvalue().strip()) - - with terminal.capture() as (out, _): - self.run_args('series', '-s', 'first', 'add', '-M', - '-D', 'description', pwork=True) - cser.add('first', 'description', allow_unmarked=True) - self.assertIn("Added v1 to existing series 'first'", - out.getvalue().strip()) - - def test_series_add_skip_version(self): - """Test adding a series which is v4 but has no earlier version""" - cser = self.get_cser() - with terminal.capture() as (out, _): - cser.add('third4', 'The glorious third series', mark=False, - allow_unmarked=True) - lines = out.getvalue().splitlines() - self.assertEqual( - "Adding series 'third' v4: mark False allow_unmarked True", - lines[0]) - self.assertEqual("Added series 'third' v4 (4 commits)", lines[1]) - self.assertEqual(2, len(lines)) - - sdict = cser.db.series_get_dict() - self.assertIn('third', sdict) - chk = sdict['third'] - self.assertEqual('third', chk['name']) - self.assertEqual('The glorious third series', chk['desc']) - - svid = cser.get_series_svid(chk['idnum'], 4) - self.assertEqual(4, len(cser.get_pcommit_dict(svid))) - - # Remove the series and add it again with just two commits - with terminal.capture(): - cser.remove('third4') - - with terminal.capture() as (out, _): - cser.add('third4', 'The glorious third series', mark=False, - allow_unmarked=True, end='third4~2') - lines = out.getvalue().splitlines() - self.assertEqual( - "Adding series 'third' v4: mark False allow_unmarked True", - lines[0]) - self.assertRegex( - lines[1], - 'Ending before .* main: Change to the main program') - self.assertEqual("Added series 'third' v4 (2 commits)", lines[2]) - - sdict = cser.db.series_get_dict() - self.assertIn('third', sdict) - chk = sdict['third'] - self.assertEqual('third', chk['name']) - self.assertEqual('The glorious third series', chk['desc']) - - svid = cser.get_series_svid(chk['idnum'], 4) - self.assertEqual(2, len(cser.get_pcommit_dict(svid))) - - def test_series_add_wrong_version(self): - """Test adding a series with an incorrect branch name or version - - This updates branch 'first' to have version 2, then tries to add it. - """ - cser = self.get_cser() - self.assertFalse(cser.db.series_get_dict()) - - with terminal.capture(): - _, ser, max_vers, _ = cser.prep_series('first') - cser.update_series('first', ser, max_vers, None, False, - add_vers=2) - - with self.assertRaises(ValueError) as exc: - with terminal.capture(): - cser.add('first', 'my description', allow_unmarked=True) - self.assertEqual( - "Series name 'first' suggests version 1 but Series-version tag " - 'indicates 2 (see --force-version)', str(exc.exception)) - - # Now try again with --force-version which should force version 1 - with terminal.capture() as (out, _): - cser.add('first', 'my description', allow_unmarked=True, - force_version=True) - itr = iter(out.getvalue().splitlines()) - self.assertEqual( - "Adding series 'first' v1: mark False allow_unmarked True", - next(itr)) - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual( - "Processing 2 commits from branch 'first'", next(itr)) - self.assertRegex(next(itr), - f'- {HASH_RE} as {HASH_RE} i2c: I2C things') - self.assertRegex(next(itr), - f'- rm v1: {HASH_RE} as {HASH_RE} spi: SPI fixes') - self.assertRegex(next(itr), - f'Updating branch first from {HASH_RE} to {HASH_RE}') - self.assertEqual("Added series 'first' v1 (2 commits)", next(itr)) - try: - self.assertEqual('extra line', next(itr)) - except StopIteration: - pass - - # Since this is v1 the Series-version tag should have been removed - series = patchstream.get_metadata('first', 0, 2, git_dir=self.gitdir) - self.assertNotIn('version', series) - - def _fake_patchwork_cser(self, subpath): - """Fake Patchwork server for the function below - - This handles accessing various things used by the tests below. It has - hard-coded data, about from self.autolink_extra which can be adjusted - by the test. - - Args: - subpath (str): URL subpath to use - """ - # Get a list of projects - if subpath == 'projects/': - return [ - {'id': self.PROJ_ID, 'name': 'U-Boot', - 'link_name': self.PROJ_LINK_NAME}, - {'id': 9, 'name': 'other', 'link_name': 'other'} - ] - - # Search for series by their cover-letter name - re_search = re.match(r'series/\?project=(\d+)&q=.*$', subpath) - if re_search: - result = [ - {'id': 56, 'name': 'contains first name', 'version': 1}, - {'id': 43, 'name': 'has first in it', 'version': 1}, - {'id': 1234, 'name': 'first series', 'version': 1}, - {'id': self.SERIES_ID_SECOND_V1, 'name': self.TITLE_SECOND, - 'version': 1}, - {'id': self.SERIES_ID_SECOND_V2, 'name': self.TITLE_SECOND, - 'version': 2}, - {'id': 12345, 'name': 'i2c: I2C things', 'version': 1}, - ] - if self.autolink_extra: - result += [self.autolink_extra] - return result - - # Read information about a series, given its link (patchwork series ID) - m_series = re.match(r'series/(\d+)/$', subpath) - series_id = int(m_series.group(1)) if m_series else '' - if series_id: - if series_id == self.SERIES_ID_SECOND_V1: - # series 'second' - return { - 'patches': [ - {'id': '10', - 'name': '[PATCH,1/3] video: Some video improvements', - 'content': ''}, - {'id': '11', - 'name': '[PATCH,2/3] serial: Add a serial driver', - 'content': ''}, - {'id': '12', 'name': '[PATCH,3/3] bootm: Make it boot', - 'content': ''}, - ], - 'cover_letter': { - 'id': 39, - 'name': 'The name of the cover letter', - } - } - if series_id == self.SERIES_ID_SECOND_V2: - # series 'second2' - return { - 'patches': [ - {'id': '110', - 'name': - '[PATCH,v2,1/3] video: Some video improvements', - 'content': ''}, - {'id': '111', - 'name': '[PATCH,v2,2/3] serial: Add a serial driver', - 'content': ''}, - {'id': '112', - 'name': '[PATCH,v2,3/3] bootm: Make it boot', - 'content': ''}, - ], - 'cover_letter': { - 'id': 139, - 'name': 'The name of the cover letter', - } - } - if series_id == self.SERIES_ID_FIRST_V3: - # series 'first3' - return { - 'patches': [ - {'id': 20, 'name': '[PATCH,v3,1/2] i2c: I2C things', - 'content': ''}, - {'id': 21, 'name': '[PATCH,v3,2/2] spi: SPI fixes', - 'content': ''}, - ], - 'cover_letter': { - 'id': 29, - 'name': 'Cover letter for first', - } - } - if series_id == 123: - return { - 'patches': [ - {'id': 20, 'name': '[PATCH,1/2] i2c: I2C things', - 'content': ''}, - {'id': 21, 'name': '[PATCH,2/2] spi: SPI fixes', - 'content': ''}, - ], - } - if series_id == 1234: - return { - 'patches': [ - {'id': 20, 'name': '[PATCH,v2,1/2] i2c: I2C things', - 'content': ''}, - {'id': 21, 'name': '[PATCH,v2,2/2] spi: SPI fixes', - 'content': ''}, - ], - } - raise ValueError(f'Fake Patchwork unknown series_id: {series_id}') - - # Read patch status - m_pat = re.search(r'patches/(\d*)/$', subpath) - patch_id = int(m_pat.group(1)) if m_pat else '' - if patch_id: - if patch_id in [10, 110]: - return {'state': 'accepted', - 'content': - 'Reviewed-by: Fred Bloggs <[email protected]>'} - if patch_id in [11, 111]: - return {'state': 'changes-requested', 'content': ''} - if patch_id in [12, 112]: - return {'state': 'rejected', - 'content': "I don't like this at all, sorry"} - if patch_id == 20: - return {'state': 'awaiting-upstream', 'content': ''} - if patch_id == 21: - return {'state': 'not-applicable', 'content': ''} - raise ValueError(f'Fake Patchwork unknown patch_id: {patch_id}') - - # Read comments a from patch - m_comm = re.search(r'patches/(\d*)/comments/', subpath) - patch_id = int(m_comm.group(1)) if m_comm else '' - if patch_id: - if patch_id in [10, 110]: - return [ - {'id': 1, 'content': ''}, - {'id': 2, - 'content': - '''On some date Mary Smith <[email protected]> wrote: -> This was my original patch -> which is being quoted - -I like the approach here and I would love to see more of it. - -Reviewed-by: Fred Bloggs <[email protected]> -''', - 'submitter': { - 'name': 'Fred Bloggs', - 'email': '[email protected]', - } - }, - ] - if patch_id in [11, 111]: - return [] - if patch_id in [12, 112]: - return [ - {'id': 4, 'content': ''}, - {'id': 5, 'content': ''}, - {'id': 6, 'content': ''}, - ] - if patch_id == 20: - return [ - {'id': 7, 'content': - '''On some date Alex Miller <[email protected]> wrote: - -> Sometimes we need to create a patch. -> This is one of those times - -Tested-by: Mary Smith <[email protected]> # yak -'''}, - {'id': 8, 'content': ''}, - ] - if patch_id == 21: - return [] - raise ValueError( - f'Fake Patchwork does not understand patch_id {patch_id}: ' - f'{subpath}') - - # Read comments from a cover letter - m_cover_id = re.search(r'covers/(\d*)/comments/', subpath) - cover_id = int(m_cover_id.group(1)) if m_cover_id else '' - if cover_id: - if cover_id in [39, 139]: - return [ - {'content': 'some comment', - 'submitter': { - 'name': 'A user', - 'email': '[email protected]', - }, - 'date': 'Sun 13 Apr 14:06:02 MDT 2025', - }, - {'content': 'another comment', - 'submitter': { - 'name': 'Ghenkis Khan', - 'email': '[email protected]', - }, - 'date': 'Sun 13 Apr 13:06:02 MDT 2025', - }, - ] - if cover_id == 29: - return [] - - raise ValueError(f'Fake Patchwork unknown cover_id: {cover_id}') - - raise ValueError(f'Fake Patchwork does not understand: {subpath}') - - def setup_second(self, do_sync=True): - """Set up the 'second' series synced with the fake patchwork - - Args: - do_sync (bool): True to sync the series - - Return: tuple: - Cseries: New Cseries object - pwork: Patchwork object - """ - with self.stage('setup second'): - cser = self.get_cser() - pwork = Patchwork.for_testing(self._fake_patchwork_cser) - pwork.project_set(self.PROJ_ID, self.PROJ_LINK_NAME) - - with terminal.capture() as (out, _): - cser.add('first', '', allow_unmarked=True) - cser.add('second', allow_unmarked=True) - - series = patchstream.get_metadata_for_list('second', self.gitdir, - 3) - self.assertEqual('456', series.links) - - with terminal.capture() as (out, _): - cser.increment('second') - - series = patchstream.get_metadata_for_list('second', self.gitdir, - 3) - self.assertEqual('456', series.links) - - series = patchstream.get_metadata_for_list('second2', self.gitdir, - 3) - self.assertEqual('1:456', series.links) - - if do_sync: - with terminal.capture() as (out, _): - cser.link_auto(pwork, 'second', 2, True) - with terminal.capture() as (out, _): - cser.gather(pwork, 'second', 2, False, True, False) - lines = out.getvalue().splitlines() - self.assertEqual( - "Updating series 'second' version 2 from link '457'", - lines[0]) - self.assertEqual( - '3 patches and cover letter updated (8 requests)', - lines[1]) - self.assertEqual(2, len(lines)) - - return cser, pwork - - def test_series_add_no_cover(self): - """Test patchwork when adding a series which has no cover letter""" - cser = self.get_cser() - pwork = Patchwork.for_testing(self._fake_patchwork_cser) - pwork.project_set(self.PROJ_ID, self.PROJ_LINK_NAME) - - with terminal.capture() as (out, _): - cser.add('first', 'my name for this', mark=False, - allow_unmarked=True) - self.assertIn("Added series 'first' v1 (2 commits)", out.getvalue()) - - with terminal.capture() as (out, _): - cser.link_auto(pwork, 'first', 1, True) - self.assertIn("Setting link for series 'first' v1 to 12345", - out.getvalue()) - - def test_series_list(self): - """Test listing cseries""" - self.setup_second() - - self.db_close() - args = Namespace(subcmd='ls') - with terminal.capture() as (out, _): - control.do_series(args, test_db=self.tmpdir, pwork=True) - lines = out.getvalue().splitlines() - self.assertEqual(5, len(lines)) - self.assertEqual( - 'Name Description ' - 'Accepted Versions', lines[0]) - self.assertTrue(lines[1].startswith('--')) - self.assertEqual( - 'first ' - ' -/2 1', lines[2]) - self.assertEqual( - 'second Series for my board ' - ' 1/3 1 2', lines[3]) - self.assertTrue(lines[4].startswith('--')) - - def test_do_series_add(self): - """Add a new cseries""" - self.make_git_tree() - args = Namespace(subcmd='add', desc='my-description', series='first', - mark=False, allow_unmarked=True, upstream=None, - dry_run=False) - with terminal.capture() as (out, _): - control.do_series(args, test_db=self.tmpdir, pwork=True) - - cser = self.get_database() - slist = cser.db.series_get_dict() - self.assertEqual(1, len(slist)) - ser = slist.get('first') - self.assertTrue(ser) - self.assertEqual('first', ser.name) - self.assertEqual('my-description', ser.desc) - - self.db_close() - args.subcmd = 'ls' - with terminal.capture() as (out, _): - control.do_series(args, test_db=self.tmpdir, pwork=True) - lines = out.getvalue().splitlines() - self.assertEqual(4, len(lines)) - self.assertTrue(lines[1].startswith('--')) - self.assertEqual( - 'first my-description ' - '-/2 1', lines[2]) - - def test_do_series_add_cmdline(self): - """Add a new cseries using the cmdline""" - self.make_git_tree() - with terminal.capture(): - self.run_args('series', '-s', 'first', 'add', '-M', - '-D', 'my-description', pwork=True) - - cser = self.get_database() - slist = cser.db.series_get_dict() - self.assertEqual(1, len(slist)) - ser = slist.get('first') - self.assertTrue(ser) - self.assertEqual('first', ser.name) - self.assertEqual('my-description', ser.desc) - - def test_do_series_add_auto(self): - """Add a new cseries without any arguments""" - self.make_git_tree() - - # Use the 'second' branch, which has a cover letter - gitutil.checkout('second', self.gitdir, work_tree=self.tmpdir, - force=True) - args = Namespace(subcmd='add', series=None, mark=False, - allow_unmarked=True, upstream=None, dry_run=False, - desc=None) - with terminal.capture(): - control.do_series(args, test_db=self.tmpdir, pwork=True) - - cser = self.get_database() - slist = cser.db.series_get_dict() - self.assertEqual(1, len(slist)) - ser = slist.get('second') - self.assertTrue(ser) - self.assertEqual('second', ser.name) - self.assertEqual('Series for my board', ser.desc) - cser.close_database() - - def _check_inc(self, out): - """Check output from an 'increment' operation - - Args: - out (StringIO): Text to check - """ - itr = iter(out.getvalue().splitlines()) - - self.assertEqual("Increment 'first' v1: 2 patches", next(itr)) - self.assertRegex(next(itr), 'Checking out upstream commit .*') - self.assertEqual("Processing 2 commits from branch 'first2'", - next(itr)) - self.assertRegex(next(itr), - f'- {HASH_RE} as {HASH_RE} i2c: I2C things') - self.assertRegex(next(itr), - f'- add v2: {HASH_RE} as {HASH_RE} spi: SPI fixes') - self.assertRegex( - next(itr), f'Updating branch first2 from {HASH_RE} to {HASH_RE}') - self.assertEqual('Added new branch first2', next(itr)) - return itr - - def test_series_link(self): - """Test adding a patchwork link to a cseries""" - cser = self.get_cser() - - repo = pygit2.init_repository(self.gitdir) - first = repo.lookup_branch('first').peel( - pygit2.enums.ObjectType.COMMIT).oid - base = repo.lookup_branch('base').peel( - pygit2.enums.ObjectType.COMMIT).oid - - gitutil.checkout('first', self.gitdir, work_tree=self.tmpdir, - force=True) - - with terminal.capture() as (out, _): - cser.add('first', '', allow_unmarked=True) - - with self.assertRaises(ValueError) as exc: - cser.link_set('first', 2, '1234', True) - self.assertEqual("Series 'first' does not have a version 2", - str(exc.exception)) - - self.assertEqual('first', gitutil.get_branch(self.gitdir)) - with terminal.capture() as (out, _): - cser.increment('first') - self.assertTrue(repo.lookup_branch('first2')) - - with terminal.capture() as (out, _): - cser.link_set('first', 2, '2345', True) - - lines = out.getvalue().splitlines() - self.assertEqual(6, len(lines)) - self.assertRegex( - lines[0], 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual("Processing 2 commits from branch 'first2'", - lines[1]) - self.assertRegex( - lines[2], - f'- {HASH_RE} as {HASH_RE} i2c: I2C things') - self.assertRegex( - lines[3], - f"- add v2 links '2:2345': {HASH_RE} as {HASH_RE} spi: SPI fixes") - self.assertRegex( - lines[4], f'Updating branch first2 from {HASH_RE} to {HASH_RE}') - self.assertEqual("Setting link for series 'first' v2 to 2345", - lines[5]) - - self.assertEqual('2345', cser.link_get('first', 2)) - - series = patchstream.get_metadata_for_list('first2', self.gitdir, 2) - self.assertEqual('2:2345', series.links) - - self.assertEqual('first2', gitutil.get_branch(self.gitdir)) - - # Check the original series was left alone - self.assertEqual( - first, repo.lookup_branch('first').peel( - pygit2.enums.ObjectType.COMMIT).oid) - count = 2 - series1 = patchstream.get_metadata_for_list('first', self.gitdir, - count) - self.assertFalse('links' in series1) - self.assertFalse('version' in series1) - - # Check that base is left alone - self.assertEqual( - base, repo.lookup_branch('base').peel( - pygit2.enums.ObjectType.COMMIT).oid) - series1 = patchstream.get_metadata_for_list('base', self.gitdir, count) - self.assertFalse('links' in series1) - self.assertFalse('version' in series1) - - # Check out second and try to update first - gitutil.checkout('second', self.gitdir, work_tree=self.tmpdir, - force=True) - with terminal.capture(): - cser.link_set('first', 1, '16', True) - - # Overwrite the link - with terminal.capture(): - cser.link_set('first', 1, '17', True) - - series2 = patchstream.get_metadata_for_list('first', self.gitdir, - count) - self.assertEqual('1:17', series2.links) - - def test_series_link_cmdline(self): - """Test adding a patchwork link to a cseries using the cmdline""" - cser = self.get_cser() - - gitutil.checkout('first', self.gitdir, work_tree=self.tmpdir, - force=True) - - with terminal.capture() as (out, _): - cser.add('first', '', allow_unmarked=True) - - with terminal.capture() as (out, _): - self.run_args('series', '-s', 'first', '-V', '4', 'set-link', '-u', - '1234', expect_ret=1, pwork=True) - self.assertIn("Series 'first' does not have a version 4", - out.getvalue()) - - with self.assertRaises(ValueError) as exc: - cser.link_get('first', 4) - self.assertEqual("Series 'first' does not have a version 4", - str(exc.exception)) - - with terminal.capture() as (out, _): - cser.increment('first') - - with self.assertRaises(ValueError) as exc: - cser.link_get('first', 4) - self.assertEqual("Series 'first' does not have a version 4", - str(exc.exception)) - - with terminal.capture() as (out, _): - cser.increment('first') - cser.increment('first') - - with terminal.capture() as (out, _): - self.run_args('series', '-s', 'first', '-V', '4', 'set-link', '-u', - '1234', pwork=True) - lines = out.getvalue().splitlines() - self.assertRegex( - lines[-3], - f"- add v4 links '4:1234': {HASH_RE} as {HASH_RE} spi: SPI fixes") - self.assertEqual("Setting link for series 'first' v4 to 1234", - lines[-1]) - - with terminal.capture() as (out, _): - self.run_args('series', '-s', 'first', '-V', '4', 'get-link', - pwork=True) - self.assertIn('1234', out.getvalue()) - - series = patchstream.get_metadata_for_list('first4', self.gitdir, 1) - self.assertEqual('4:1234', series.links) - - with terminal.capture() as (out, _): - self.run_args('series', '-s', 'first', '-V', '5', 'get-link', - expect_ret=1, pwork=True) - - self.assertIn("Series 'first' does not have a version 5", - out.getvalue()) - - # Checkout 'first' and try to get the link from 'first4' - gitutil.checkout('first', self.gitdir, work_tree=self.tmpdir, - force=True) - - with terminal.capture() as (out, _): - self.run_args('series', '-s', 'first4', 'get-link', pwork=True) - self.assertIn('1234', out.getvalue()) - - # This should get the link for 'first' - with terminal.capture() as (out, _): - self.run_args('series', 'get-link', pwork=True) - self.assertIn('None', out.getvalue()) - - # Checkout 'first4' again; this should get the link for 'first4' - gitutil.checkout('first4', self.gitdir, work_tree=self.tmpdir, - force=True) - - with terminal.capture() as (out, _): - self.run_args('series', 'get-link', pwork=True) - self.assertIn('1234', out.getvalue()) - - def test_series_link_auto_version(self): - """Test finding the patchwork link for a cseries automatically""" - cser = self.get_cser() - - with terminal.capture() as (out, _): - cser.add('second', allow_unmarked=True) - - # Make sure that the link is there - count = 3 - series = patchstream.get_metadata('second', 0, count, - git_dir=self.gitdir) - self.assertEqual(f'{self.SERIES_ID_SECOND_V1}', series.links) - - # Set link with detected version - with terminal.capture() as (out, _): - cser.link_set('second', None, f'{self.SERIES_ID_SECOND_V1}', True) - self.assertEqual( - "Setting link for series 'second' v1 to 456", - out.getvalue().splitlines()[-1]) - - # Make sure that the link was set - series = patchstream.get_metadata('second', 0, count, - git_dir=self.gitdir) - self.assertEqual(f'1:{self.SERIES_ID_SECOND_V1}', series.links) - - with terminal.capture(): - cser.increment('second') - - # Make sure that the new series gets the same link - series = patchstream.get_metadata('second2', 0, 3, - git_dir=self.gitdir) - - pwork = Patchwork.for_testing(self._fake_patchwork_cser) - pwork.project_set(self.PROJ_ID, self.PROJ_LINK_NAME) - self.assertFalse(cser.project_get()) - cser.project_set(pwork, 'U-Boot', quiet=True) - - self.assertEqual( - (self.SERIES_ID_SECOND_V1, None, 'second', 1, - 'Series for my board'), - cser.link_search(pwork, 'second', 1)) - - with terminal.capture(): - cser.increment('second') - - self.assertEqual((457, None, 'second', 2, 'Series for my board'), - cser.link_search(pwork, 'second', 2)) - - def test_series_link_auto_name(self): - """Test finding the patchwork link for a cseries with auto name""" - cser = self.get_cser() - - with terminal.capture() as (out, _): - cser.add('first', '', allow_unmarked=True) - - # Set link with detected name - with self.assertRaises(ValueError) as exc: - cser.link_set(None, 2, '2345', True) - self.assertEqual( - "Series 'first' does not have a version 2", str(exc.exception)) - - with terminal.capture(): - cser.increment('first') - - with terminal.capture() as (out, _): - cser.link_set(None, 2, '2345', True) - self.assertEqual( - "Setting link for series 'first' v2 to 2345", - out.getvalue().splitlines()[-1]) - - svlist = cser.get_ser_ver_list() - self.assertEqual(2, len(svlist)) - self.assertEqual(1, svlist[0].idnum) - self.assertEqual(1, svlist[0].series_id) - self.assertEqual(1, svlist[0].version) - self.assertIsNone(svlist[0].link) - - self.assertEqual(2, svlist[1].idnum) - self.assertEqual(1, svlist[1].series_id) - self.assertEqual(2, svlist[1].version) - self.assertEqual('2345', svlist[1].link) - - def test_series_link_auto_name_version(self): - """Find patchwork link for a cseries with auto name + version""" - cser = self.get_cser() - - with terminal.capture() as (out, _): - cser.add('first', '', allow_unmarked=True) - - # Set link with detected name and version - with terminal.capture() as (out, _): - cser.link_set(None, None, '1234', True) - self.assertEqual( - "Setting link for series 'first' v1 to 1234", - out.getvalue().splitlines()[-1]) - - with terminal.capture(): - cser.increment('first') - - with terminal.capture() as (out, _): - cser.link_set(None, None, '2345', True) - self.assertEqual( - "Setting link for series 'first' v2 to 2345", - out.getvalue().splitlines()[-1]) - - svlist = cser.get_ser_ver_list() - self.assertEqual(2, len(svlist)) - self.assertEqual(1, svlist[0].idnum) - self.assertEqual(1, svlist[0].series_id) - self.assertEqual(1, svlist[0].version) - self.assertEqual('1234', svlist[0].link) - - self.assertEqual(2, svlist[1].idnum) - self.assertEqual(1, svlist[1].series_id) - self.assertEqual(2, svlist[1].version) - self.assertEqual('2345', svlist[1].link) - - def test_series_link_missing(self): - """Test finding patchwork link for a cseries but it is missing""" - cser = self.get_cser() - - with terminal.capture(): - cser.add('second', allow_unmarked=True) - - with terminal.capture(): - cser.increment('second') - cser.increment('second') - - pwork = Patchwork.for_testing(self._fake_patchwork_cser) - pwork.project_set(self.PROJ_ID, self.PROJ_LINK_NAME) - self.assertFalse(cser.project_get()) - cser.project_set(pwork, 'U-Boot', quiet=True) - - self.assertEqual( - (self.SERIES_ID_SECOND_V1, None, 'second', 1, - 'Series for my board'), - cser.link_search(pwork, 'second', 1)) - self.assertEqual((457, None, 'second', 2, 'Series for my board'), - cser.link_search(pwork, 'second', 2)) - res = cser.link_search(pwork, 'second', 3) - self.assertEqual( - (None, - [{'id': self.SERIES_ID_SECOND_V1, 'name': 'Series for my board', - 'version': 1}, - {'id': 457, 'name': 'Series for my board', 'version': 2}], - 'second', 3, 'Series for my board'), - res) - - def check_series_autolink(self): - """Common code for autolink tests""" - cser = self.get_cser() - - with self.stage('setup'): - pwork = Patchwork.for_testing(self._fake_patchwork_cser) - pwork.project_set(self.PROJ_ID, self.PROJ_LINK_NAME) - self.assertFalse(cser.project_get()) - cser.project_set(pwork, 'U-Boot', quiet=True) - - with terminal.capture(): - cser.add('first', '', allow_unmarked=True) - cser.add('second', allow_unmarked=True) - - with self.stage('autolink unset'): - with terminal.capture() as (out, _): - yield cser, pwork - self.assertEqual( - "Setting link for series 'second' v1 to " - f'{self.SERIES_ID_SECOND_V1}', - out.getvalue().splitlines()[-1]) - - svlist = cser.get_ser_ver_list() - self.assertEqual(2, len(svlist)) - self.assertEqual(1, svlist[0].idnum) - self.assertEqual(1, svlist[0].series_id) - self.assertEqual(1, svlist[0].version) - self.assertEqual(2, svlist[1].idnum) - self.assertEqual(2, svlist[1].series_id) - self.assertEqual(1, svlist[1].version) - self.assertEqual(str(self.SERIES_ID_SECOND_V1), svlist[1].link) - yield None - - def test_series_autolink(self): - """Test linking a cseries to its patchwork series by description""" - cor = self.check_series_autolink() - cser, pwork = next(cor) - - with self.assertRaises(ValueError) as exc: - cser.link_auto(pwork, 'first', None, True) - self.assertIn("Series 'first' has an empty description", - str(exc.exception)) - - # autolink unset - cser.link_auto(pwork, 'second', None, True) - - self.assertFalse(next(cor)) - cor.close() - - def test_series_autolink_cmdline(self): - """Test linking to patchwork series by description on cmdline""" - cor = self.check_series_autolink() - _, pwork = next(cor) - - with terminal.capture() as (out, _): - self.run_args('series', '-s', 'first', 'autolink', expect_ret=1, - pwork=pwork) - self.assertEqual( - "patman: ValueError: Series 'first' has an empty description", - out.getvalue().strip()) - - # autolink unset - self.run_args('series', '-s', 'second', 'autolink', '-u', pwork=pwork) - - self.assertFalse(next(cor)) - cor.close() - - def _autolink_setup(self): - """Set things up for autolink tests - - Return: tuple: - Cseries object - Patchwork object - """ - cser = self.get_cser() - - pwork = Patchwork.for_testing(self._fake_patchwork_cser) - pwork.project_set(self.PROJ_ID, self.PROJ_LINK_NAME) - self.assertFalse(cser.project_get()) - cser.project_set(pwork, 'U-Boot', quiet=True) - - with terminal.capture(): - cser.add('first', 'first series', allow_unmarked=True) - cser.add('second', allow_unmarked=True) - cser.increment('first') - return cser, pwork - - def test_series_link_auto_all(self): - """Test linking all cseries to their patchwork series by description""" - cser, pwork = self._autolink_setup() - with terminal.capture() as (out, _): - summary = cser.link_auto_all(pwork, update_commit=True, - link_all_versions=True, - replace_existing=False, dry_run=True, - show_summary=False) - self.assertEqual(3, len(summary)) - items = iter(summary.values()) - linked = next(items) - self.assertEqual( - ('first', 1, None, 'first series', 'linked:1234'), linked) - self.assertEqual( - ('first', 2, None, 'first series', 'not found'), next(items)) - self.assertEqual( - ('second', 1, f'{self.SERIES_ID_SECOND_V1}', 'Series for my board', - f'already:{self.SERIES_ID_SECOND_V1}'), - next(items)) - self.assertEqual('Dry run completed', out.getvalue().splitlines()[-1]) - - # A second dry run should do exactly the same thing - with terminal.capture() as (out2, _): - summary2 = cser.link_auto_all(pwork, update_commit=True, - link_all_versions=True, - replace_existing=False, dry_run=True, - show_summary=False) - self.assertEqual(out.getvalue(), out2.getvalue()) - self.assertEqual(summary, summary2) - - # Now do it for real - with terminal.capture(): - summary = cser.link_auto_all(pwork, update_commit=True, - link_all_versions=True, - replace_existing=False, dry_run=False, - show_summary=False) - - # Check the link was updated - pdict = cser.get_ser_ver_dict() - svid = list(summary)[0] - self.assertEqual('1234', pdict[svid].link) - - series = patchstream.get_metadata_for_list('first', self.gitdir, 2) - self.assertEqual('1:1234', series.links) - - def test_series_autolink_latest(self): - """Test linking the lastest versions""" - cser, pwork = self._autolink_setup() - with terminal.capture(): - summary = cser.link_auto_all(pwork, update_commit=True, - link_all_versions=False, - replace_existing=False, dry_run=False, - show_summary=False) - self.assertEqual(2, len(summary)) - items = iter(summary.values()) - self.assertEqual( - ('first', 2, None, 'first series', 'not found'), next(items)) - self.assertEqual( - ('second', 1, f'{self.SERIES_ID_SECOND_V1}', 'Series for my board', - f'already:{self.SERIES_ID_SECOND_V1}'), - next(items)) - - def test_series_autolink_no_update(self): - """Test linking the lastest versions without updating commits""" - cser, pwork = self._autolink_setup() - with terminal.capture(): - cser.link_auto_all(pwork, update_commit=False, - link_all_versions=True, replace_existing=False, - dry_run=False, - show_summary=False) - - series = patchstream.get_metadata_for_list('first', self.gitdir, 2) - self.assertNotIn('links', series) - - def test_series_autolink_replace(self): - """Test linking the lastest versions without updating commits""" - cser, pwork = self._autolink_setup() - with terminal.capture(): - summary = cser.link_auto_all(pwork, update_commit=True, - link_all_versions=True, - replace_existing=True, dry_run=False, - show_summary=False) - self.assertEqual(3, len(summary)) - items = iter(summary.values()) - linked = next(items) - self.assertEqual( - ('first', 1, None, 'first series', 'linked:1234'), linked) - self.assertEqual( - ('first', 2, None, 'first series', 'not found'), next(items)) - self.assertEqual( - ('second', 1, f'{self.SERIES_ID_SECOND_V1}', 'Series for my board', - f'linked:{self.SERIES_ID_SECOND_V1}'), - next(items)) - - def test_series_autolink_extra(self): - """Test command-line operation - - This just uses mocks for now since we can rely on the direct tests for - the actual operation. - """ - _, pwork = self._autolink_setup() - with (mock.patch.object(cseries.Cseries, 'link_auto_all', - return_value=None) as method): - self.run_args('series', 'autolink-all', pwork=True) - method.assert_called_once_with(True, update_commit=False, - link_all_versions=False, - replace_existing=False, dry_run=False, - show_summary=True) - - with (mock.patch.object(cseries.Cseries, 'link_auto_all', - return_value=None) as method): - self.run_args('series', 'autolink-all', '-a', pwork=True) - method.assert_called_once_with(True, update_commit=False, - link_all_versions=True, - replace_existing=False, dry_run=False, - show_summary=True) - - with (mock.patch.object(cseries.Cseries, 'link_auto_all', - return_value=None) as method): - self.run_args('series', 'autolink-all', '-a', '-r', pwork=True) - method.assert_called_once_with(True, update_commit=False, - link_all_versions=True, - replace_existing=True, dry_run=False, - show_summary=True) - - with (mock.patch.object(cseries.Cseries, 'link_auto_all', - return_value=None) as method): - self.run_args('series', '-n', 'autolink-all', '-r', pwork=True) - method.assert_called_once_with(True, update_commit=False, - link_all_versions=False, - replace_existing=True, dry_run=True, - show_summary=True) - - with (mock.patch.object(cseries.Cseries, 'link_auto_all', - return_value=None) as method): - self.run_args('series', 'autolink-all', '-u', pwork=True) - method.assert_called_once_with(True, update_commit=True, - link_all_versions=False, - replace_existing=False, dry_run=False, - show_summary=True) - - # Now do a real one to check the patchwork handling and output - with terminal.capture() as (out, _): - self.run_args('series', 'autolink-all', '-a', pwork=pwork) - itr = iter(out.getvalue().splitlines()) - self.assertEqual( - '1 series linked, 1 already linked, 1 not found (3 requests)', - next(itr)) - self.assertEqual('', next(itr)) - self.assertEqual( - 'Name Version Description ' - ' Result', next(itr)) - self.assertTrue(next(itr).startswith('--')) - self.assertEqual( - 'first 1 first series ' - ' linked:1234', next(itr)) - self.assertEqual( - 'first 2 first series ' - ' not found', next(itr)) - self.assertEqual( - 'second 1 Series for my board ' - f' already:{self.SERIES_ID_SECOND_V1}', - next(itr)) - self.assertTrue(next(itr).startswith('--')) - self.assert_finished(itr) - - def check_series_archive(self): - """Coroutine to run the archive test""" - cser = self.get_cser() - with self.stage('setup'): - with terminal.capture(): - cser.add('first', '', allow_unmarked=True) - - # Check the series is visible in the list - slist = cser.db.series_get_dict() - self.assertEqual(1, len(slist)) - self.assertEqual('first', slist['first'].name) - - # Add a second branch - with terminal.capture(): - cser.increment('first') - - cser.fake_now = datetime(24, 9, 14) - repo = pygit2.init_repository(self.gitdir) - with self.stage('archive'): - expected_commit1 = repo.revparse_single('first') - expected_commit2 = repo.revparse_single('first2') - expected_tag1 = 'first-14sep24' - expected_tag2 = 'first2-14sep24' - - # Archive it and make sure it is invisible - yield cser - slist = cser.db.series_get_dict() - self.assertFalse(slist) - - # ...unless we include archived items - slist = cser.db.series_get_dict(include_archived=True) - self.assertEqual(1, len(slist)) - first = slist['first'] - self.assertEqual('first', first.name) - - # Make sure the branches have been tagged - svlist = cser.db.ser_ver_get_for_series(first.idnum) - self.assertEqual(expected_tag1, svlist[0].archive_tag) - self.assertEqual(expected_tag2, svlist[1].archive_tag) - - # Check that the tags were created and point to old branch commits - target1 = repo.revparse_single(expected_tag1) - self.assertEqual(expected_commit1, target1.get_object()) - target2 = repo.revparse_single(expected_tag2) - self.assertEqual(expected_commit2, target2.get_object()) - - # The branches should be deleted - self.assertFalse('first' in repo.branches) - self.assertFalse('first2' in repo.branches) - - with self.stage('unarchive'): - # or we unarchive it - yield cser - slist = cser.db.series_get_dict() - self.assertEqual(1, len(slist)) - - # Make sure the branches have been restored - branch1 = repo.branches['first'] - branch2 = repo.branches['first2'] - self.assertEqual(expected_commit1.oid, branch1.target) - self.assertEqual(expected_commit2.oid, branch2.target) - - # Make sure the tags were deleted - try: - target1 = repo.revparse_single(expected_tag1) - self.fail('target1 is still present') - except KeyError: - pass - try: - target1 = repo.revparse_single(expected_tag2) - self.fail('target2 is still present') - except KeyError: - pass - - # Make sure the tag information has been removed - svlist = cser.db.ser_ver_get_for_series(first.idnum) - self.assertFalse(svlist[0].archive_tag) - self.assertFalse(svlist[1].archive_tag) - - yield False - - def test_series_archive(self): - """Test marking a series as archived""" - cor = self.check_series_archive() - cser = next(cor) - - # Archive it and make sure it is invisible - cser.archive('first') - cser = next(cor) - cser.unarchive('first') - self.assertFalse(next(cor)) - cor.close() - - def test_series_archive_cmdline(self): - """Test marking a series as archived with cmdline""" - cor = self.check_series_archive() - cser = next(cor) - - # Archive it and make sure it is invisible - self.run_args('series', '-s', 'first', 'archive', pwork=True, - cser=cser) - next(cor) - self.run_args('series', '-s', 'first', 'unarchive', pwork=True, - cser=cser) - self.assertFalse(next(cor)) - cor.close() - - def check_series_inc(self): - """Coroutine to run the increment test""" - cser = self.get_cser() - - with self.stage('setup'): - gitutil.checkout('first', self.gitdir, work_tree=self.tmpdir, - force=True) - with terminal.capture() as (out, _): - cser.add('first', '', allow_unmarked=True) - - with self.stage('increment'): - with terminal.capture() as (out, _): - yield cser - self._check_inc(out) - - slist = cser.db.series_get_dict() - self.assertEqual(1, len(slist)) - - svlist = cser.get_ser_ver_list() - self.assertEqual(2, len(svlist)) - self.assertEqual(1, svlist[0].idnum) - self.assertEqual(1, svlist[0].series_id) - self.assertEqual(1, svlist[0].version) - - self.assertEqual(2, svlist[1].idnum) - self.assertEqual(1, svlist[1].series_id) - self.assertEqual(2, svlist[1].version) - - series = patchstream.get_metadata_for_list('first2', self.gitdir, - 1) - self.assertEqual('2', series.version) - - series = patchstream.get_metadata_for_list('first', self.gitdir, 1) - self.assertNotIn('version', series) - - self.assertEqual('first2', gitutil.get_branch(self.gitdir)) - yield None - - def test_series_inc(self): - """Test incrementing the version""" - cor = self.check_series_inc() - cser = next(cor) - - cser.increment('first') - self.assertFalse(next(cor)) - - cor.close() - - def test_series_inc_cmdline(self): - """Test incrementing the version with cmdline""" - cor = self.check_series_inc() - next(cor) - - self.run_args('series', '-s', 'first', 'inc', pwork=True) - self.assertFalse(next(cor)) - cor.close() - - def test_series_inc_no_upstream(self): - """Increment a series which has no upstream branch""" - cser = self.get_cser() - - gitutil.checkout('first', self.gitdir, work_tree=self.tmpdir, - force=True) - with terminal.capture(): - cser.add('first', '', allow_unmarked=True) - - repo = pygit2.init_repository(self.gitdir) - upstream = repo.lookup_branch('base') - upstream.delete() - with terminal.capture(): - cser.increment('first') - - slist = cser.db.series_get_dict() - self.assertEqual(1, len(slist)) - - def test_series_inc_dryrun(self): - """Test incrementing the version with cmdline""" - cser = self.get_cser() - - gitutil.checkout('first', self.gitdir, work_tree=self.tmpdir, - force=True) - with terminal.capture() as (out, _): - cser.add('first', '', allow_unmarked=True) - - with terminal.capture() as (out, _): - cser.increment('first', dry_run=True) - itr = self._check_inc(out) - self.assertEqual('Dry run completed', next(itr)) - - # Make sure that nothing was added - svlist = cser.get_ser_ver_list() - self.assertEqual(1, len(svlist)) - self.assertEqual(1, svlist[0].idnum) - self.assertEqual(1, svlist[0].series_id) - self.assertEqual(1, svlist[0].version) - - # We should still be on the same branch - self.assertEqual('first', gitutil.get_branch(self.gitdir)) - - def test_series_dec(self): - """Test decrementing the version""" - cser = self.get_cser() - - gitutil.checkout('first', self.gitdir, work_tree=self.tmpdir, - force=True) - with terminal.capture() as (out, _): - cser.add('first', '', allow_unmarked=True) - - pclist = cser.get_pcommit_dict() - self.assertEqual(2, len(pclist)) - - # Try decrementing when there is only one version - with self.assertRaises(ValueError) as exc: - cser.decrement('first') - self.assertEqual("Series 'first' only has one version", - str(exc.exception)) - - # Add a version; now there should be two - with terminal.capture() as (out, _): - cser.increment('first') - svdict = cser.get_ser_ver_dict() - self.assertEqual(2, len(svdict)) - - pclist = cser.get_pcommit_dict() - self.assertEqual(4, len(pclist)) - - # Remove version two, using dry run (i.e. no effect) - with terminal.capture() as (out, _): - cser.decrement('first', dry_run=True) - svdict = cser.get_ser_ver_dict() - self.assertEqual(2, len(svdict)) - - repo = pygit2.init_repository(self.gitdir) - branch = repo.lookup_branch('first2') - self.assertTrue(branch) - branch_oid = branch.peel(pygit2.enums.ObjectType.COMMIT).oid - - pclist = cser.get_pcommit_dict() - self.assertEqual(4, len(pclist)) - - # Now remove version two for real - with terminal.capture() as (out, _): - cser.decrement('first') - lines = out.getvalue().splitlines() - self.assertEqual(2, len(lines)) - self.assertEqual("Removing series 'first' v2", lines[0]) - self.assertEqual( - f"Deleted branch 'first2' {str(branch_oid)[:10]}", lines[1]) - - svdict = cser.get_ser_ver_dict() - self.assertEqual(1, len(svdict)) - - pclist = cser.get_pcommit_dict() - self.assertEqual(2, len(pclist)) - - branch = repo.lookup_branch('first2') - self.assertFalse(branch) - - # Removing the only version should not be allowed - with self.assertRaises(ValueError) as exc: - cser.decrement('first', dry_run=True) - self.assertEqual("Series 'first' only has one version", - str(exc.exception)) - - def test_upstream_add(self): - """Test adding an upsream""" - cser = self.get_cser() - - cser.upstream_add('us', 'https://one') - ulist = cser.get_upstream_dict() - self.assertEqual(1, len(ulist)) - self.assertEqual(('https://one', None), ulist['us']) - - cser.upstream_add('ci', 'git@two') - ulist = cser.get_upstream_dict() - self.assertEqual(2, len(ulist)) - self.assertEqual(('https://one', None), ulist['us']) - self.assertEqual(('git@two', None), ulist['ci']) - - # Try to add a duplicate - with self.assertRaises(ValueError) as exc: - cser.upstream_add('ci', 'git@three') - self.assertEqual("Upstream 'ci' already exists", str(exc.exception)) - - with terminal.capture() as (out, _): - cser.upstream_list() - lines = out.getvalue().splitlines() - self.assertEqual(2, len(lines)) - self.assertEqual('us https://one', lines[0]) - self.assertEqual('ci git@two', lines[1]) - - def test_upstream_add_cmdline(self): - """Test adding an upsream with cmdline""" - with terminal.capture(): - self.run_args('upstream', 'add', 'us', 'https://one') - - with terminal.capture() as (out, _): - self.run_args('upstream', 'list') - lines = out.getvalue().splitlines() - self.assertEqual(1, len(lines)) - self.assertEqual('us https://one', lines[0]) - - def test_upstream_default(self): - """Operation of the default upstream""" - cser = self.get_cser() - - with self.assertRaises(ValueError) as exc: - cser.upstream_set_default('us') - self.assertEqual("No such upstream 'us'", str(exc.exception)) - - cser.upstream_add('us', 'https://one') - cser.upstream_add('ci', 'git@two') - - self.assertIsNone(cser.upstream_get_default()) - - cser.upstream_set_default('us') - self.assertEqual('us', cser.upstream_get_default()) - - cser.upstream_set_default('us') - - cser.upstream_set_default('ci') - self.assertEqual('ci', cser.upstream_get_default()) - - with terminal.capture() as (out, _): - cser.upstream_list() - lines = out.getvalue().splitlines() - self.assertEqual(2, len(lines)) - self.assertEqual('us https://one', lines[0]) - self.assertEqual('ci default git@two', lines[1]) - - cser.upstream_set_default(None) - self.assertIsNone(cser.upstream_get_default()) - - def test_upstream_default_cmdline(self): - """Operation of the default upstream on cmdline""" - with terminal.capture() as (out, _): - self.run_args('upstream', 'default', 'us', expect_ret=1) - self.assertEqual("patman: ValueError: No such upstream 'us'", - out.getvalue().strip().splitlines()[-1]) - - self.run_args('upstream', 'add', 'us', 'https://one') - self.run_args('upstream', 'add', 'ci', 'git@two') - - with terminal.capture() as (out, _): - self.run_args('upstream', 'default') - self.assertEqual('unset', out.getvalue().strip()) - - self.run_args('upstream', 'default', 'us') - with terminal.capture() as (out, _): - self.run_args('upstream', 'default') - self.assertEqual('us', out.getvalue().strip()) - - self.run_args('upstream', 'default', 'ci') - with terminal.capture() as (out, _): - self.run_args('upstream', 'default') - self.assertEqual('ci', out.getvalue().strip()) - - with terminal.capture() as (out, _): - self.run_args('upstream', 'default', '--unset') - self.assertFalse(out.getvalue().strip()) - - with terminal.capture() as (out, _): - self.run_args('upstream', 'default') - self.assertEqual('unset', out.getvalue().strip()) - - def test_upstream_delete(self): - """Test operation of the default upstream""" - cser = self.get_cser() - - with self.assertRaises(ValueError) as exc: - cser.upstream_delete('us') - self.assertEqual("No such upstream 'us'", str(exc.exception)) - - cser.upstream_add('us', 'https://one') - cser.upstream_add('ci', 'git@two') - - cser.upstream_set_default('us') - cser.upstream_delete('us') - self.assertIsNone(cser.upstream_get_default()) - - cser.upstream_delete('ci') - ulist = cser.get_upstream_dict() - self.assertFalse(ulist) - - def test_upstream_delete_cmdline(self): - """Test deleting an upstream""" - with terminal.capture() as (out, _): - self.run_args('upstream', 'delete', 'us', expect_ret=1) - self.assertEqual("patman: ValueError: No such upstream 'us'", - out.getvalue().strip().splitlines()[-1]) - - self.run_args('us', 'add', 'us', 'https://one') - self.run_args('us', 'add', 'ci', 'git@two') - - self.run_args('upstream', 'default', 'us') - self.run_args('upstream', 'delete', 'us') - with terminal.capture() as (out, _): - self.run_args('upstream', 'default', 'us', expect_ret=1) - self.assertEqual("patman: ValueError: No such upstream 'us'", - out.getvalue().strip()) - - self.run_args('upstream', 'delete', 'ci') - with terminal.capture() as (out, _): - self.run_args('upstream', 'list') - self.assertFalse(out.getvalue().strip()) - - def test_series_add_mark(self): - """Test marking a cseries with Change-Id fields""" - cser = self.get_cser() - - with terminal.capture(): - cser.add('first', '', mark=True) - - pcdict = cser.get_pcommit_dict() - - series = patchstream.get_metadata('first', 0, 2, git_dir=self.gitdir) - self.assertEqual(2, len(series.commits)) - self.assertIn(1, pcdict) - self.assertEqual(1, pcdict[1].idnum) - self.assertEqual('i2c: I2C things', pcdict[1].subject) - self.assertEqual(1, pcdict[1].svid) - self.assertEqual(series.commits[0].change_id, pcdict[1].change_id) - - self.assertIn(2, pcdict) - self.assertEqual(2, pcdict[2].idnum) - self.assertEqual('spi: SPI fixes', pcdict[2].subject) - self.assertEqual(1, pcdict[2].svid) - self.assertEqual(series.commits[1].change_id, pcdict[2].change_id) - - def test_series_add_mark_fail(self): - """Test marking a cseries when the tree is dirty""" - cser = self.get_cser() - - tools.write_file(os.path.join(self.tmpdir, 'fname'), b'123') - with terminal.capture(): - cser.add('first', '', mark=True) - - tools.write_file(os.path.join(self.tmpdir, 'i2c.c'), b'123') - with self.assertRaises(ValueError) as exc: - with terminal.capture(): - cser.add('first', '', mark=True) - self.assertEqual( - "Modified files exist: use 'git status' to check: [' M i2c.c']", - str(exc.exception)) - - def test_series_add_mark_dry_run(self): - """Test marking a cseries with Change-Id fields""" - cser = self.get_cser() - - with terminal.capture() as (out, _): - cser.add('first', '', mark=True, dry_run=True) - itr = iter(out.getvalue().splitlines()) - self.assertEqual( - "Adding series 'first' v1: mark True allow_unmarked False", - next(itr)) - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual("Processing 2 commits from branch 'first'", - next(itr)) - self.assertRegex( - next(itr), f'- marked: {HASH_RE} as {HASH_RE} i2c: I2C things') - self.assertRegex( - next(itr), f'- marked: {HASH_RE} as {HASH_RE} spi: SPI fixes') - self.assertRegex( - next(itr), f'Updating branch first from {HASH_RE} to {HASH_RE}') - self.assertEqual("Added series 'first' v1 (2 commits)", - next(itr)) - self.assertEqual('Dry run completed', next(itr)) - - # Doing another dry run should produce the same result - with terminal.capture() as (out2, _): - cser.add('first', '', mark=True, dry_run=True) - self.assertEqual(out.getvalue(), out2.getvalue()) - - tools.write_file(os.path.join(self.tmpdir, 'i2c.c'), b'123') - with terminal.capture() as (out, _): - with self.assertRaises(ValueError) as exc: - cser.add('first', '', mark=True, dry_run=True) - self.assertEqual( - "Modified files exist: use 'git status' to check: [' M i2c.c']", - str(exc.exception)) - - pcdict = cser.get_pcommit_dict() - self.assertFalse(pcdict) - - def test_series_add_mark_cmdline(self): - """Test marking a cseries with Change-Id fields using the cmdline""" - cser = self.get_cser() - - with terminal.capture(): - self.run_args('series', '-s', 'first', 'add', '-m', - '-D', 'my-description', pwork=True) - - pcdict = cser.get_pcommit_dict() - self.assertTrue(pcdict[1].change_id) - self.assertTrue(pcdict[2].change_id) - - def test_series_add_unmarked_cmdline(self): - """Test adding an unmarked cseries using the command line""" - cser = self.get_cser() - - with terminal.capture(): - self.run_args('series', '-s', 'first', 'add', '-M', - '-D', 'my-description', pwork=True) - - pcdict = cser.get_pcommit_dict() - self.assertFalse(pcdict[1].change_id) - self.assertFalse(pcdict[2].change_id) - - def test_series_add_unmarked_bad_cmdline(self): - """Test failure to add an unmarked cseries using a bad command line""" - self.get_cser() - - with terminal.capture() as (out, _): - self.run_args('series', '-s', 'first', 'add', - '-D', 'my-description', expect_ret=1, pwork=True) - last_line = out.getvalue().splitlines()[-2] - self.assertEqual( - 'patman: ValueError: 2 commit(s) are unmarked; ' - 'please use -m or -M', last_line) - - def check_series_unmark(self): - """Checker for unmarking tests""" - cser = self.get_cser() - with self.stage('unmarked commits'): - yield cser - - with self.stage('mark commits'): - with terminal.capture() as (out, _): - yield cser - - with self.stage('unmark: dry run'): - with terminal.capture() as (out, _): - yield cser - - itr = iter(out.getvalue().splitlines()) - self.assertEqual( - "Unmarking series 'first': allow_unmarked False", - next(itr)) - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual("Processing 2 commits from branch 'first'", - next(itr)) - self.assertRegex( - next(itr), - f'- unmarked: {HASH_RE} as {HASH_RE} i2c: I2C things') - self.assertRegex( - next(itr), - f'- unmarked: {HASH_RE} as {HASH_RE} spi: SPI fixes') - self.assertRegex( - next(itr), f'Updating branch first from {HASH_RE} to {HASH_RE}') - self.assertEqual('Dry run completed', next(itr)) - - with self.stage('unmark'): - with terminal.capture() as (out, _): - yield cser - self.assertIn('- unmarked', out.getvalue()) - - with self.stage('unmark: allow unmarked'): - with terminal.capture() as (out, _): - yield cser - self.assertIn('- no mark', out.getvalue()) - - yield None - - def test_series_unmark(self): - """Test unmarking a cseries, i.e. removing Change-Id fields""" - cor = self.check_series_unmark() - cser = next(cor) - - # check the allow_unmarked flag - with terminal.capture(): - with self.assertRaises(ValueError) as exc: - cser.unmark('first', dry_run=True) - self.assertEqual('Unmarked commits 2/2', str(exc.exception)) - - # mark commits - cser = next(cor) - cser.add('first', '', mark=True) - - # unmark: dry run - cser = next(cor) - cser.unmark('first', dry_run=True) - - # unmark - cser = next(cor) - cser.unmark('first') - - # unmark: allow unmarked - cser = next(cor) - cser.unmark('first', allow_unmarked=True) - - self.assertFalse(next(cor)) - - def test_series_unmark_cmdline(self): - """Test the unmark command""" - cor = self.check_series_unmark() - next(cor) - - # check the allow_unmarked flag - with terminal.capture() as (out, _): - self.run_args('series', 'unmark', expect_ret=1, pwork=True) - self.assertIn('Unmarked commits 2/2', out.getvalue()) - - # mark commits - next(cor) - self.run_args('series', '-s', 'first', 'add', '-D', '', '--mark', - pwork=True) - - # unmark: dry run - next(cor) - self.run_args('series', '-s', 'first', '-n', 'unmark', pwork=True) - - # unmark - next(cor) - self.run_args('series', '-s', 'first', 'unmark', pwork=True) - - # unmark: allow unmarked - next(cor) - self.run_args('series', '-s', 'first', 'unmark', '--allow-unmarked', - pwork=True) - - self.assertFalse(next(cor)) - - def test_series_unmark_middle(self): - """Test unmarking with Change-Id fields not last in the commit""" - cser = self.get_cser() - with terminal.capture(): - cser.add('first', '', allow_unmarked=True) - - # Add some change IDs in the middle of the commit message - with terminal.capture(): - name, ser, _, _ = cser.prep_series('first') - old_msgs = [] - for vals in cser.process_series(name, ser): - old_msgs.append(vals.msg) - lines = vals.msg.splitlines() - change_id = cser.make_change_id(vals.commit) - extra = [f'{cser_helper.CHANGE_ID_TAG}: {change_id}'] - vals.msg = '\n'.join(lines[:2] + extra + lines[2:]) + '\n' - - with terminal.capture(): - cser.unmark('first') - - # We should get back the original commit message - series = patchstream.get_metadata('first', 0, 2, git_dir=self.gitdir) - self.assertEqual(old_msgs[0], series.commits[0].msg) - self.assertEqual(old_msgs[1], series.commits[1].msg) - - def check_series_mark(self): - """Checker for marking tests""" - cser = self.get_cser() - yield cser - - # Start with a dry run, which should do nothing - with self.stage('dry run'): - with terminal.capture(): - yield cser - - series = patchstream.get_metadata_for_list('first', self.gitdir, 2) - self.assertEqual(2, len(series.commits)) - self.assertFalse(series.commits[0].change_id) - self.assertFalse(series.commits[1].change_id) - - # Now do a real run - with self.stage('real run'): - with terminal.capture(): - yield cser - - series = patchstream.get_metadata_for_list('first', self.gitdir, 2) - self.assertEqual(2, len(series.commits)) - self.assertTrue(series.commits[0].change_id) - self.assertTrue(series.commits[1].change_id) - - # Try to mark again, which should fail - with self.stage('mark twice'): - with terminal.capture(): - with self.assertRaises(ValueError) as exc: - cser.mark('first', dry_run=False) - self.assertEqual('Marked commits 2/2', str(exc.exception)) - - # Use the --marked flag to make it succeed - with self.stage('mark twice with --marked'): - with terminal.capture(): - yield cser - self.assertEqual('Marked commits 2/2', str(exc.exception)) - - series2 = patchstream.get_metadata_for_list('first', self.gitdir, - 2) - self.assertEqual(2, len(series2.commits)) - self.assertEqual(series.commits[0].change_id, - series2.commits[0].change_id) - self.assertEqual(series.commits[1].change_id, - series2.commits[1].change_id) - - yield None - - def test_series_mark(self): - """Test marking a cseries, i.e. adding Change-Id fields""" - cor = self.check_series_mark() - cser = next(cor) - - # Start with a dry run, which should do nothing - cser = next(cor) - cser.mark('first', dry_run=True) - - # Now do a real run - cser = next(cor) - cser.mark('first', dry_run=False) - - # Try to mark again, which should fail - with terminal.capture(): - with self.assertRaises(ValueError) as exc: - cser.mark('first', dry_run=False) - self.assertEqual('Marked commits 2/2', str(exc.exception)) - - # Use the --allow-marked flag to make it succeed - cser = next(cor) - cser.mark('first', allow_marked=True, dry_run=False) - - self.assertFalse(next(cor)) - - def test_series_mark_cmdline(self): - """Test marking a cseries, i.e. adding Change-Id fields""" - cor = self.check_series_mark() - next(cor) - - # Start with a dry run, which should do nothing - next(cor) - self.run_args('series', '-n', '-s', 'first', 'mark', pwork=True) - - # Now do a real run - next(cor) - self.run_args('series', '-s', 'first', 'mark', pwork=True) - - # Try to mark again, which should fail - with terminal.capture() as (out, _): - self.run_args('series', '-s', 'first', 'mark', expect_ret=1, - pwork=True) - self.assertIn('Marked commits 2/2', out.getvalue()) - - # Use the --allow-marked flag to make it succeed - next(cor) - self.run_args('series', '-s', 'first', 'mark', '--allow-marked', - pwork=True) - self.assertFalse(next(cor)) - - def test_series_remove(self): - """Test removing a series""" - cser = self.get_cser() - - with self.stage('remove non-existent series'): - with self.assertRaises(ValueError) as exc: - cser.remove('first') - self.assertEqual("No such series 'first'", str(exc.exception)) - - with self.stage('add'): - with terminal.capture() as (out, _): - cser.add('first', '', mark=True) - self.assertTrue(cser.db.series_get_dict()) - pclist = cser.get_pcommit_dict() - self.assertEqual(2, len(pclist)) - - with self.stage('remove'): - with terminal.capture() as (out, _): - cser.remove('first') - self.assertEqual("Removed series 'first'", out.getvalue().strip()) - self.assertFalse(cser.db.series_get_dict()) - - pclist = cser.get_pcommit_dict() - self.assertFalse(len(pclist)) - - def test_series_remove_cmdline(self): - """Test removing a series using the command line""" - cser = self.get_cser() - - with self.stage('remove non-existent series'): - with terminal.capture() as (out, _): - self.run_args('series', '-s', 'first', 'rm', expect_ret=1, - pwork=True) - self.assertEqual("patman: ValueError: No such series 'first'", - out.getvalue().strip()) - - with self.stage('add'): - with terminal.capture() as (out, _): - cser.add('first', '', mark=True) - self.assertTrue(cser.db.series_get_dict()) - - with self.stage('remove'): - with terminal.capture() as (out, _): - cser.remove('first') - self.assertEqual("Removed series 'first'", out.getvalue().strip()) - self.assertFalse(cser.db.series_get_dict()) - - def check_series_remove_multiple(self): - """Check for removing a series with more than one version""" - cser = self.get_cser() - - with self.stage('setup'): - self.add_first2(True) - - with terminal.capture() as (out, _): - cser.add(None, '', mark=True) - cser.add('first', '', mark=True) - self.assertTrue(cser.db.series_get_dict()) - pclist = cser.get_pcommit_dict() - self.assertEqual(4, len(pclist)) - - # Do a dry-run removal - with self.stage('dry run'): - with terminal.capture() as (out, _): - yield cser - self.assertEqual("Removed version 1 from series 'first'\n" - 'Dry run completed', out.getvalue().strip()) - self.assertEqual({'first'}, cser.db.series_get_dict().keys()) - - svlist = cser.get_ser_ver_list() - self.assertEqual(2, len(svlist)) - self.assertEqual(1, svlist[0].idnum) - self.assertEqual(1, svlist[0].series_id) - self.assertEqual(2, svlist[0].version) - - self.assertEqual(2, svlist[1].idnum) - self.assertEqual(1, svlist[1].series_id) - self.assertEqual(1, svlist[1].version) - - # Now remove for real - with self.stage('real'): - with terminal.capture() as (out, _): - yield cser - self.assertEqual("Removed version 1 from series 'first'", - out.getvalue().strip()) - self.assertEqual({'first'}, cser.db.series_get_dict().keys()) - plist = cser.get_ser_ver_list() - self.assertEqual(1, len(plist)) - pclist = cser.get_pcommit_dict() - self.assertEqual(2, len(pclist)) - - with self.stage('remove only version'): - yield cser - self.assertEqual({'first'}, cser.db.series_get_dict().keys()) - - svlist = cser.get_ser_ver_list() - self.assertEqual(1, len(svlist)) - self.assertEqual(1, svlist[0].idnum) - self.assertEqual(1, svlist[0].series_id) - self.assertEqual(2, svlist[0].version) - - with self.stage('remove series (dry run'): - with terminal.capture() as (out, _): - yield cser - self.assertEqual("Removed series 'first'\nDry run completed", - out.getvalue().strip()) - self.assertTrue(cser.db.series_get_dict()) - self.assertTrue(cser.get_ser_ver_list()) - - with self.stage('remove series'): - with terminal.capture() as (out, _): - yield cser - self.assertEqual("Removed series 'first'", out.getvalue().strip()) - self.assertFalse(cser.db.series_get_dict()) - self.assertFalse(cser.get_ser_ver_list()) - - yield False - - def test_series_remove_multiple(self): - """Test removing a series with more than one version""" - cor = self.check_series_remove_multiple() - cser = next(cor) - - # Do a dry-run removal - cser.version_remove('first', 1, dry_run=True) - cser = next(cor) - - # Now remove for real - cser.version_remove('first', 1) - cser = next(cor) - - # Remove only version - with self.assertRaises(ValueError) as exc: - cser.version_remove('first', 2, dry_run=True) - self.assertEqual( - "Series 'first' only has one version: remove the series", - str(exc.exception)) - cser = next(cor) - - # Remove series (dry run) - cser.remove('first', dry_run=True) - cser = next(cor) - - # Remove series (real) - cser.remove('first') - - self.assertFalse(next(cor)) - cor.close() - - def test_series_remove_multiple_cmdline(self): - """Test removing a series with more than one version on cmdline""" - cor = self.check_series_remove_multiple() - next(cor) - - # Do a dry-run removal - self.run_args('series', '-n', '-s', 'first', '-V', '1', 'rm-version', - pwork=True) - next(cor) - - # Now remove for real - self.run_args('series', '-s', 'first', '-V', '1', 'rm-version', - pwork=True) - next(cor) - - # Remove only version - with terminal.capture() as (out, _): - self.run_args('series', '-n', '-s', 'first', '-V', '2', - 'rm-version', expect_ret=1, pwork=True) - self.assertIn( - "Series 'first' only has one version: remove the series", - out.getvalue().strip()) - next(cor) - - # Remove series (dry run) - self.run_args('series', '-n', '-s', 'first', 'rm', pwork=True) - next(cor) - - # Remove series (real) - self.run_args('series', '-s', 'first', 'rm', pwork=True) - - self.assertFalse(next(cor)) - cor.close() - - def test_patchwork_set_project(self): - """Test setting the project ID""" - cser = self.get_cser() - pwork = Patchwork.for_testing(self._fake_patchwork_cser) - with terminal.capture() as (out, _): - cser.project_set(pwork, 'U-Boot') - self.assertEqual( - f"Project 'U-Boot' patchwork-ID {self.PROJ_ID} link-name uboot", - out.getvalue().strip()) - - def test_patchwork_project_get(self): - """Test setting the project ID""" - cser = self.get_cser() - pwork = Patchwork.for_testing(self._fake_patchwork_cser) - self.assertFalse(cser.project_get()) - with terminal.capture() as (out, _): - cser.project_set(pwork, 'U-Boot') - self.assertEqual( - f"Project 'U-Boot' patchwork-ID {self.PROJ_ID} link-name uboot", - out.getvalue().strip()) - - name, pwid, link_name = cser.project_get() - self.assertEqual('U-Boot', name) - self.assertEqual(self.PROJ_ID, pwid) - self.assertEqual('uboot', link_name) - - def test_patchwork_project_get_cmdline(self): - """Test setting the project ID""" - cser = self.get_cser() - - self.assertFalse(cser.project_get()) - - pwork = Patchwork.for_testing(self._fake_patchwork_cser) - with terminal.capture() as (out, _): - self.run_args('-P', 'https://url', 'patchwork', 'set-project', - 'U-Boot', pwork=pwork) - self.assertEqual( - f"Project 'U-Boot' patchwork-ID {self.PROJ_ID} link-name uboot", - out.getvalue().strip()) - - name, pwid, link_name = cser.project_get() - self.assertEqual('U-Boot', name) - self.assertEqual(6, pwid) - self.assertEqual('uboot', link_name) - - with terminal.capture() as (out, _): - self.run_args('-P', 'https://url', 'patchwork', 'get-project') - self.assertEqual( - f"Project 'U-Boot' patchwork-ID {self.PROJ_ID} link-name uboot", - out.getvalue().strip()) - - def check_series_list_patches(self): - """Test listing the patches for a series""" - cser = self.get_cser() - - with self.stage('setup'): - with terminal.capture() as (out, _): - cser.add(None, '', allow_unmarked=True) - cser.add('second', allow_unmarked=True) - target = self.repo.lookup_reference('refs/heads/second') - self.repo.checkout( - target, strategy=pygit2.enums.CheckoutStrategy.FORCE) - cser.increment('second') - - with self.stage('list first'): - with terminal.capture() as (out, _): - yield cser - itr = iter(out.getvalue().splitlines()) - self.assertEqual("Branch 'first' (total 2): 2:unknown", next(itr)) - self.assertIn('PatchId', next(itr)) - self.assertRegex(next(itr), r' 0 .* i2c: I2C things') - self.assertRegex(next(itr), r' 1 .* spi: SPI fixes') - - with self.stage('list second2'): - with terminal.capture() as (out, _): - yield cser - itr = iter(out.getvalue().splitlines()) - self.assertEqual( - "Branch 'second2' (total 3): 3:unknown", next(itr)) - self.assertIn('PatchId', next(itr)) - self.assertRegex( - next(itr), ' 0 .* video: Some video improvements') - self.assertRegex(next(itr), ' 1 .* serial: Add a serial driver') - self.assertRegex(next(itr), ' 2 .* bootm: Make it boot') - - yield None - - def test_series_list_patches(self): - """Test listing the patches for a series""" - cor = self.check_series_list_patches() - cser = next(cor) - - # list first - cser.list_patches('first', 1) - cser = next(cor) - - # list second2 - cser.list_patches('second2', 2) - self.assertFalse(next(cor)) - cor.close() - - def test_series_list_patches_cmdline(self): - """Test listing the patches for a series using the cmdline""" - cor = self.check_series_list_patches() - next(cor) - - # list first - self.run_args('series', '-s', 'first', 'patches', pwork=True) - next(cor) - - # list second2 - self.run_args('series', '-s', 'second', '-V', '2', 'patches', - pwork=True) - self.assertFalse(next(cor)) - cor.close() - - def test_series_list_patches_detail(self): - """Test listing the patches for a series""" - cser = self.get_cser() - with terminal.capture(): - cser.add(None, '', allow_unmarked=True) - cser.add('second', allow_unmarked=True) - target = self.repo.lookup_reference('refs/heads/second') - self.repo.checkout( - target, strategy=pygit2.enums.CheckoutStrategy.FORCE) - cser.increment('second') - - with terminal.capture() as (out, _): - cser.list_patches('first', 1, show_commit=True) - expect = r'''Branch 'first' (total 2): 2:unknown -Seq State Com PatchId Commit Subject - 0 unknown - .* i2c: I2C things - -commit .* -Author: Test user <[email protected]> -Date: .* - - i2c: I2C things - - This has some stuff to do with I2C - - i2c.c | 2 ++ - 1 file changed, 2 insertions(+) - - - 1 unknown - .* spi: SPI fixes - -commit .* -Author: Test user <[email protected]> -Date: .* - - spi: SPI fixes - - SPI needs some fixes - and here they are - - Signed-off-by: Lord Edmund Blackaddër <[email protected]> - - Series-to: u-boot - Commit-notes: - title of the series - This is the cover letter for the series - with various details - END - - spi.c | 3 +++ - 1 file changed, 3 insertions(+) -''' - itr = iter(out.getvalue().splitlines()) - for seq, eline in enumerate(expect.splitlines()): - line = next(itr).rstrip() - if '*' in eline: - self.assertRegex(line, eline, f'line {seq + 1}') - else: - self.assertEqual(eline, line, f'line {seq + 1}') - - # Show just the patch; this should exclude the commit message - with terminal.capture() as (out, _): - cser.list_patches('first', 1, show_patch=True) - chk = out.getvalue() - self.assertIn('SPI fixes', chk) # subject - self.assertNotIn('SPI needs some fixes', chk) # commit body - self.assertIn('make SPI work', chk) # patch body - - # Show both - with terminal.capture() as (out, _): - cser.list_patches('first', 1, show_commit=True, show_patch=True) - chk = out.getvalue() - self.assertIn('SPI fixes', chk) # subject - self.assertIn('SPI needs some fixes', chk) # commit body - self.assertIn('make SPI work', chk) # patch body - - def check_series_gather(self): - """Checker for gathering tags for a series""" - cser = self.get_cser() - with self.stage('setup'): - pwork = Patchwork.for_testing(self._fake_patchwork_cser) - self.assertFalse(cser.project_get()) - cser.project_set(pwork, 'U-Boot', quiet=True) - - with terminal.capture() as (out, _): - cser.add('second', 'description', allow_unmarked=True) - - ser = cser.get_series_by_name('second') - pwid = cser.get_series_svid(ser.idnum, 1) - - # First do a dry run - with self.stage('gather: dry run'): - with terminal.capture() as (out, _): - yield cser, pwork - lines = out.getvalue().splitlines() - self.assertEqual( - f"Updating series 'second' version 1 from link " - f"'{self.SERIES_ID_SECOND_V1}'", - lines[0]) - self.assertEqual('3 patches updated (7 requests)', lines[1]) - self.assertEqual('Dry run completed', lines[2]) - self.assertEqual(3, len(lines)) - - pwc = cser.get_pcommit_dict(pwid) - self.assertIsNone(pwc[0].state) - self.assertIsNone(pwc[1].state) - self.assertIsNone(pwc[2].state) - - # Now try it again, gathering tags - with self.stage('gather: dry run'): - with terminal.capture() as (out, _): - yield cser, pwork - lines = out.getvalue().splitlines() - itr = iter(lines) - self.assertEqual( - f"Updating series 'second' version 1 from link " - f"'{self.SERIES_ID_SECOND_V1}'", - next(itr)) - self.assertEqual(' 1 video: Some video improvements', next(itr)) - self.assertEqual(' + Reviewed-by: Fred Bloggs <[email protected]>', - next(itr)) - self.assertEqual(' 2 serial: Add a serial driver', next(itr)) - self.assertEqual(' 3 bootm: Make it boot', next(itr)) - - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual("Processing 3 commits from branch 'second'", - next(itr)) - self.assertRegex( - next(itr), - f'- added 1 tag: {HASH_RE} as {HASH_RE} ' - 'video: Some video improvements') - self.assertRegex( - next(itr), - f"- upd links '1:456': {HASH_RE} as {HASH_RE} " - 'serial: Add a serial driver') - self.assertRegex( - next(itr), - f'- {HASH_RE} as {HASH_RE} ' - 'bootm: Make it boot') - self.assertRegex( - next(itr), - f'Updating branch second from {HASH_RE} to {HASH_RE}') - self.assertEqual('3 patches updated (7 requests)', next(itr)) - self.assertEqual('Dry run completed', next(itr)) - self.assert_finished(itr) - - # Make sure that no tags were added to the branch - series = patchstream.get_metadata_for_list('second', self.gitdir, - 3) - for cmt in series.commits: - self.assertFalse(cmt.rtags, - 'Commit {cmt.subject} rtags {cmt.rtags}') - - # Now do it for real - with self.stage('gather: real'): - with terminal.capture() as (out, _): - yield cser, pwork - lines2 = out.getvalue().splitlines() - self.assertEqual(lines2, lines[:-1]) - - # Make sure that the tags were added to the branch - series = patchstream.get_metadata_for_list('second', self.gitdir, - 3) - self.assertEqual( - {'Reviewed-by': {'Fred Bloggs <[email protected]>'}}, - series.commits[0].rtags) - self.assertFalse(series.commits[1].rtags) - self.assertFalse(series.commits[2].rtags) - - # Make sure the status was updated - pwc = cser.get_pcommit_dict(pwid) - self.assertEqual('accepted', pwc[0].state) - self.assertEqual('changes-requested', pwc[1].state) - self.assertEqual('rejected', pwc[2].state) - - yield None - - def test_series_gather(self): - """Test gathering tags for a series""" - cor = self.check_series_gather() - cser, pwork = next(cor) - - # sync (dry_run) - cser.gather(pwork, 'second', None, False, False, False, dry_run=True) - cser, pwork = next(cor) - - # gather (dry_run) - cser.gather(pwork, 'second', None, False, False, True, dry_run=True) - cser, pwork = next(cor) - - # gather (real) - cser.gather(pwork, 'second', None, False, False, True) - - self.assertFalse(next(cor)) - - def test_series_gather_cmdline(self): - """Test gathering tags for a series with cmdline""" - cor = self.check_series_gather() - _, pwork = next(cor) - - # sync (dry_run) - self.run_args( - 'series', '-n', '-s', 'second', 'gather', '-G', pwork=pwork) - - # gather (dry_run) - _, pwork = next(cor) - self.run_args('series', '-n', '-s', 'second', 'gather', pwork=pwork) - - # gather (real) - _, pwork = next(cor) - self.run_args('series', '-s', 'second', 'gather', pwork=pwork) - - self.assertFalse(next(cor)) - - def check_series_gather_all(self): - """Gather all series at once""" - with self.stage('setup'): - cser, pwork = self.setup_second(False) - - with terminal.capture(): - cser.add('first', 'description', allow_unmarked=True) - cser.increment('first') - cser.increment('first') - cser.link_set('first', 1, '123', True) - cser.link_set('first', 2, '1234', True) - cser.link_set('first', 3, f'{self.SERIES_ID_FIRST_V3}', True) - cser.link_auto(pwork, 'second', 2, True) - - with self.stage('no options'): - with terminal.capture() as (out, _): - yield cser, pwork - self.assertEqual( - "Syncing 'first' v3\n" - "Syncing 'second' v2\n" - '\n' - '5 patches and 2 cover letters updated, 0 missing links ' - '(14 requests)\n' - 'Dry run completed', - out.getvalue().strip()) - - with self.stage('gather'): - with terminal.capture() as (out, _): - yield cser, pwork - lines = out.getvalue().splitlines() - itr = iter(lines) - self.assertEqual("Syncing 'first' v3", next(itr)) - self.assertEqual(' 1 i2c: I2C things', next(itr)) - self.assertEqual( - ' + Tested-by: Mary Smith <[email protected]> # yak', - next(itr)) - self.assertEqual(' 2 spi: SPI fixes', next(itr)) - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual( - "Processing 2 commits from branch 'first3'", next(itr)) - self.assertRegex( - next(itr), - f'- added 1 tag: {HASH_RE} as {HASH_RE} i2c: I2C things') - self.assertRegex( - next(itr), - f"- upd links '3:31': {HASH_RE} as {HASH_RE} spi: SPI fixes") - self.assertRegex( - next(itr), - f'Updating branch first3 from {HASH_RE} to {HASH_RE}') - self.assertEqual('', next(itr)) - - self.assertEqual("Syncing 'second' v2", next(itr)) - self.assertEqual(' 1 video: Some video improvements', next(itr)) - self.assertEqual( - ' + Reviewed-by: Fred Bloggs <[email protected]>', next(itr)) - self.assertEqual(' 2 serial: Add a serial driver', next(itr)) - self.assertEqual(' 3 bootm: Make it boot', next(itr)) - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual( - "Processing 3 commits from branch 'second2'", next(itr)) - self.assertRegex( - next(itr), - f'- added 1 tag: {HASH_RE} as {HASH_RE} ' - 'video: Some video improvements') - self.assertRegex( - next(itr), - f"- upd links '2:457 1:456': {HASH_RE} as {HASH_RE} " - 'serial: Add a serial driver') - self.assertRegex( - next(itr), - f'- {HASH_RE} as {HASH_RE} ' - 'bootm: Make it boot') - self.assertRegex( - next(itr), - f'Updating branch second2 from {HASH_RE} to {HASH_RE}') - self.assertEqual('', next(itr)) - self.assertEqual( - '5 patches and 2 cover letters updated, 0 missing links ' - '(14 requests)', - next(itr)) - self.assertEqual('Dry run completed', next(itr)) - self.assert_finished(itr) - - with self.stage('gather, patch comments,!dry_run'): - with terminal.capture() as (out, _): - yield cser, pwork - lines = out.getvalue().splitlines() - itr = iter(lines) - self.assertEqual("Syncing 'first' v1", next(itr)) - self.assertEqual(' 1 i2c: I2C things', next(itr)) - self.assertEqual( - ' + Tested-by: Mary Smith <[email protected]> # yak', - next(itr)) - self.assertEqual(' 2 spi: SPI fixes', next(itr)) - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual( - "Processing 2 commits from branch 'first'", next(itr)) - self.assertRegex( - next(itr), - f'- added 1 tag: {HASH_RE} as {HASH_RE} i2c: I2C things') - self.assertRegex( - next(itr), - f"- upd links '1:123': {HASH_RE} as {HASH_RE} spi: SPI fixes") - self.assertRegex( - next(itr), - f'Updating branch first from {HASH_RE} to {HASH_RE}') - self.assertEqual('', next(itr)) - - self.assertEqual("Syncing 'first' v2", next(itr)) - self.assertEqual(' 1 i2c: I2C things', next(itr)) - self.assertEqual( - ' + Tested-by: Mary Smith <[email protected]> # yak', - next(itr)) - self.assertEqual(' 2 spi: SPI fixes', next(itr)) - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual( - "Processing 2 commits from branch 'first2'", next(itr)) - self.assertRegex( - next(itr), - f'- added 1 tag: {HASH_RE} as {HASH_RE} ' - 'i2c: I2C things') - self.assertRegex( - next(itr), - f"- upd links '2:1234': {HASH_RE} as {HASH_RE} spi: SPI fixes") - self.assertRegex( - next(itr), - f'Updating branch first2 from {HASH_RE} to {HASH_RE}') - self.assertEqual('', next(itr)) - self.assertEqual("Syncing 'first' v3", next(itr)) - self.assertEqual(' 1 i2c: I2C things', next(itr)) - self.assertEqual( - ' + Tested-by: Mary Smith <[email protected]> # yak', - next(itr)) - self.assertEqual(' 2 spi: SPI fixes', next(itr)) - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual( - "Processing 2 commits from branch 'first3'", next(itr)) - self.assertRegex( - next(itr), - f'- added 1 tag: {HASH_RE} as {HASH_RE} i2c: I2C things') - self.assertRegex( - next(itr), - f"- upd links '3:31': {HASH_RE} as {HASH_RE} spi: SPI fixes") - self.assertRegex( - next(itr), - f'Updating branch first3 from {HASH_RE} to {HASH_RE}') - self.assertEqual('', next(itr)) - - self.assertEqual("Syncing 'second' v1", next(itr)) - self.assertEqual(' 1 video: Some video improvements', next(itr)) - self.assertEqual( - ' + Reviewed-by: Fred Bloggs <[email protected]>', next(itr)) - self.assertEqual( - 'Review: Fred Bloggs <[email protected]>', next(itr)) - self.assertEqual(' > This was my original patch', next(itr)) - self.assertEqual(' > which is being quoted', next(itr)) - self.assertEqual( - ' I like the approach here and I would love to see more ' - 'of it.', next(itr)) - self.assertEqual('', next(itr)) - self.assertEqual(' 2 serial: Add a serial driver', next(itr)) - self.assertEqual(' 3 bootm: Make it boot', next(itr)) - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual( - "Processing 3 commits from branch 'second'", next(itr)) - self.assertRegex( - next(itr), - f'- added 1 tag: {HASH_RE} as {HASH_RE} ' - 'video: Some video improvements') - self.assertRegex( - next(itr), - f"- upd links '1:456': {HASH_RE} as {HASH_RE} " - 'serial: Add a serial driver') - self.assertRegex( - next(itr), - f'- {HASH_RE} as {HASH_RE} ' - 'bootm: Make it boot') - self.assertRegex( - next(itr), - f'Updating branch second from {HASH_RE} to {HASH_RE}') - self.assertEqual('', next(itr)) - - self.assertEqual("Syncing 'second' v2", next(itr)) - self.assertEqual(' 1 video: Some video improvements', next(itr)) - self.assertEqual( - ' + Reviewed-by: Fred Bloggs <[email protected]>', next(itr)) - self.assertEqual( - 'Review: Fred Bloggs <[email protected]>', next(itr)) - self.assertEqual(' > This was my original patch', next(itr)) - self.assertEqual(' > which is being quoted', next(itr)) - self.assertEqual( - ' I like the approach here and I would love to see more ' - 'of it.', next(itr)) - self.assertEqual('', next(itr)) - self.assertEqual(' 2 serial: Add a serial driver', next(itr)) - self.assertEqual(' 3 bootm: Make it boot', next(itr)) - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual( - "Processing 3 commits from branch 'second2'", next(itr)) - self.assertRegex( - next(itr), - f'- added 1 tag: {HASH_RE} as {HASH_RE} ' - 'video: Some video improvements') - self.assertRegex( - next(itr), - f"- upd links '2:457 1:456': {HASH_RE} as {HASH_RE} " - 'serial: Add a serial driver') - self.assertRegex( - next(itr), - f'- {HASH_RE} as {HASH_RE} ' - 'bootm: Make it boot') - self.assertRegex( - next(itr), - f'Updating branch second2 from {HASH_RE} to {HASH_RE}') - self.assertEqual('', next(itr)) - self.assertEqual( - '12 patches and 3 cover letters updated, 0 missing links ' - '(32 requests)', next(itr)) - self.assert_finished(itr) - - yield None - - def test_series_gather_all(self): - """Gather all series at once""" - cor = self.check_series_gather_all() - cser, pwork = next(cor) - - # no options - cser.gather_all(pwork, False, True, False, False, dry_run=True) - cser, pwork = next(cor) - - # gather - cser.gather_all(pwork, False, False, False, True, dry_run=True) - cser, pwork = next(cor) - - # gather, patch comments, !dry_run - cser.gather_all(pwork, True, False, True, True) - - self.assertFalse(next(cor)) - - def test_series_gather_all_cmdline(self): - """Sync all series at once using cmdline""" - cor = self.check_series_gather_all() - _, pwork = next(cor) - - # no options - self.run_args('series', '-n', '-s', 'second', 'gather-all', '-G', - pwork=pwork) - _, pwork = next(cor) - - # gather - self.run_args('series', '-n', '-s', 'second', 'gather-all', - pwork=pwork) - _, pwork = next(cor) - - # gather, patch comments, !dry_run - self.run_args('series', '-s', 'second', 'gather-all', '-a', '-c', - pwork=pwork) - - self.assertFalse(next(cor)) - - def _check_second(self, itr, show_all): - """Check output from a 'progress' command - - Args: - itr (Iterator): Contains the output lines to check - show_all (bool): True if all versions are being shown, not just - latest - """ - self.assertEqual('second: Series for my board (versions: 1 2)', - next(itr)) - if show_all: - self.assertEqual("Branch 'second' (total 3): 3:unknown", - next(itr)) - self.assertIn('PatchId', next(itr)) - self.assertRegex( - next(itr), - ' 0 unknown - .* video: Some video improvements') - self.assertRegex( - next(itr), - ' 1 unknown - .* serial: Add a serial driver') - self.assertRegex( - next(itr), - ' 2 unknown - .* bootm: Make it boot') - self.assertEqual('', next(itr)) - self.assertEqual( - "Branch 'second2' (total 3): 1:accepted 1:changes 1:rejected", - next(itr)) - self.assertIn('PatchId', next(itr)) - self.assertEqual( - 'Cov 2 139 ' - 'The name of the cover letter', next(itr)) - self.assertRegex( - next(itr), - ' 0 accepted 2 110 .* video: Some video improvements') - self.assertRegex( - next(itr), - ' 1 changes 111 .* serial: Add a serial driver') - self.assertRegex( - next(itr), - ' 2 rejected 3 112 .* bootm: Make it boot') - - def test_series_progress(self): - """Test showing progress for a cseries""" - self.setup_second() - self.db_close() - - with self.stage('latest versions'): - args = Namespace(subcmd='progress', series='second', - show_all_versions=False, list_patches=True) - with terminal.capture() as (out, _): - control.do_series(args, test_db=self.tmpdir, pwork=True) - lines = iter(out.getvalue().splitlines()) - self._check_second(lines, False) - - with self.stage('all versions'): - args.show_all_versions = True - with terminal.capture() as (out, _): - control.do_series(args, test_db=self.tmpdir, pwork=True) - lines = iter(out.getvalue().splitlines()) - self._check_second(lines, True) - - def _check_first(self, itr): - """Check output from the progress command - - Args: - itr (Iterator): Contains the output lines to check - """ - self.assertEqual('first: (versions: 1)', next(itr)) - self.assertEqual("Branch 'first' (total 2): 2:unknown", next(itr)) - self.assertIn('PatchId', next(itr)) - self.assertRegex( - next(itr), - ' 0 unknown - .* i2c: I2C things') - self.assertRegex( - next(itr), - ' 1 unknown - .* spi: SPI fixes') - self.assertEqual('', next(itr)) - - def test_series_progress_all(self): - """Test showing progress for all cseries""" - self.setup_second() - self.db_close() - - with self.stage('progress with patches'): - args = Namespace(subcmd='progress', series=None, - show_all_versions=False, list_patches=True) - with terminal.capture() as (out, _): - control.do_series(args, test_db=self.tmpdir, pwork=True) - lines = iter(out.getvalue().splitlines()) - self._check_first(lines) - self._check_second(lines, False) - - with self.stage('all versions'): - args.show_all_versions = True - with terminal.capture() as (out, _): - control.do_series(args, test_db=self.tmpdir, pwork=True) - lines = iter(out.getvalue().splitlines()) - self._check_first(lines) - self._check_second(lines, True) - - def test_series_progress_no_patches(self): - """Test showing progress for all cseries without patches""" - self.setup_second() - - with terminal.capture() as (out, _): - self.run_args('series', 'progress', pwork=True) - itr = iter(out.getvalue().splitlines()) - self.assertEqual( - 'Name Description ' - 'Count Status', next(itr)) - self.assertTrue(next(itr).startswith('--')) - self.assertEqual( - 'first ' - ' 2 2:unknown', next(itr)) - self.assertEqual( - 'second2 The name of the cover letter ' - ' 3 1:accepted 1:changes 1:rejected', next(itr)) - self.assertTrue(next(itr).startswith('--')) - self.assertEqual( - ['2', 'series', '5', '2:unknown', '1:accepted', '1:changes', - '1:rejected'], - next(itr).split()) - self.assert_finished(itr) - - def test_series_progress_all_no_patches(self): - """Test showing progress for all cseries versions without patches""" - self.setup_second() - - with terminal.capture() as (out, _): - self.run_args('series', 'progress', '--show-all-versions', - pwork=True) - itr = iter(out.getvalue().splitlines()) - self.assertEqual( - 'Name Description ' - 'Count Status', next(itr)) - self.assertTrue(next(itr).startswith('--')) - self.assertEqual( - 'first ' - ' 2 2:unknown', next(itr)) - self.assertEqual( - 'second Series for my board ' - ' 3 3:unknown', next(itr)) - self.assertEqual( - 'second2 The name of the cover letter ' - ' 3 1:accepted 1:changes 1:rejected', next(itr)) - self.assertTrue(next(itr).startswith('--')) - self.assertEqual( - ['3', 'series', '8', '5:unknown', '1:accepted', '1:changes', - '1:rejected'], - next(itr).split()) - self.assert_finished(itr) - - def test_series_summary(self): - """Test showing a summary of series status""" - self.setup_second() - - self.db_close() - args = Namespace(subcmd='summary', series=None) - with terminal.capture() as (out, _): - control.do_series(args, test_db=self.tmpdir, pwork=True) - lines = out.getvalue().splitlines() - self.assertEqual( - 'Name Status Description', - lines[0]) - self.assertEqual( - '----------------- ------ ------------------------------', - lines[1]) - self.assertEqual('first -/2 ', lines[2]) - self.assertEqual('second 1/3 Series for my board', lines[3]) - - def test_series_open(self): - """Test opening a series in a web browser""" - cser = self.get_cser() - pwork = Patchwork.for_testing(self._fake_patchwork_cser) - self.assertFalse(cser.project_get()) - pwork.project_set(self.PROJ_ID, self.PROJ_LINK_NAME) - - with terminal.capture(): - cser.add('second', allow_unmarked=True) - cser.increment('second') - cser.link_auto(pwork, 'second', 2, True) - cser.gather(pwork, 'second', 2, False, False, False) - - with mock.patch.object(cros_subprocess.Popen, '__init__', - return_value=None) as method: - with terminal.capture() as (out, _): - cser.open(pwork, 'second2', 2) - - url = ('https://patchwork.ozlabs.org/project/uboot/list/?series=457' - '&state=*&archive=both') - method.assert_called_once_with(['xdg-open', url]) - self.assertEqual(f'Opening {url}', out.getvalue().strip()) - - def test_name_version(self): - """Test handling of series names and versions""" - cser = self.get_cser() - repo = self.repo - - self.assertEqual(('fred', None), - cser_helper.split_name_version('fred')) - self.assertEqual(('mary', 2), cser_helper.split_name_version('mary2')) - - ser, version = cser._parse_series_and_version(None, None) - self.assertEqual('first', ser.name) - self.assertEqual(1, version) - - ser, version = cser._parse_series_and_version('first', None) - self.assertEqual('first', ser.name) - self.assertEqual(1, version) - - ser, version = cser._parse_series_and_version('first', 2) - self.assertEqual('first', ser.name) - self.assertEqual(2, version) - - with self.assertRaises(ValueError) as exc: - cser._parse_series_and_version('123', 2) - self.assertEqual( - "Series name '123' cannot be a number, use '<name><version>'", - str(exc.exception)) - - with self.assertRaises(ValueError) as exc: - cser._parse_series_and_version('first', 100) - self.assertEqual("Version 100 exceeds 99", str(exc.exception)) - - with terminal.capture() as (_, err): - cser._parse_series_and_version('mary3', 4) - self.assertIn('Version mismatch: -V has 4 but branch name indicates 3', - err.getvalue()) - - ser, version = cser._parse_series_and_version('mary', 4) - self.assertEqual('mary', ser.name) - self.assertEqual(4, version) - - # Move off the branch and check for a sensible error - commit = repo.revparse_single('first~') - repo.checkout_tree(commit) - repo.set_head(commit.oid) - - with self.assertRaises(ValueError) as exc: - cser._parse_series_and_version(None, None) - self.assertEqual('No branch detected: please use -s <series>', - str(exc.exception)) - - def test_name_version_extra(self): - """More tests for some corner cases""" - cser, _ = self.setup_second() - target = self.repo.lookup_reference('refs/heads/second2') - self.repo.checkout( - target, strategy=pygit2.enums.CheckoutStrategy.FORCE) - - ser, version = cser._parse_series_and_version(None, None) - self.assertEqual('second', ser.name) - self.assertEqual(2, version) - - ser, version = cser._parse_series_and_version('second2', None) - self.assertEqual('second', ser.name) - self.assertEqual(2, version) - - def test_migrate(self): - """Test migration to later schema versions""" - db = database.Database(f'{self.tmpdir}/.patman.db') - with terminal.capture() as (out, err): - db.open_it() - self.assertEqual( - f'Creating new database {self.tmpdir}/.patman.db', - err.getvalue().strip()) - - self.assertEqual(0, db.get_schema_version()) - - for version in range(1, database.LATEST + 1): - with terminal.capture() as (out, _): - db.migrate_to(version) - self.assertTrue(os.path.exists( - f'{self.tmpdir}/.patman.dbold.v{version - 1}')) - self.assertEqual(f'Update database to v{version}', - out.getvalue().strip()) - self.assertEqual(version, db.get_schema_version()) - self.assertEqual(4, database.LATEST) - - def test_series_scan(self): - """Test scanning a series for updates""" - cser, _ = self.setup_second() - target = self.repo.lookup_reference('refs/heads/second2') - self.repo.checkout( - target, strategy=pygit2.enums.CheckoutStrategy.FORCE) - - # Add a new commit - self.repo = pygit2.init_repository(self.gitdir) - self.make_commit_with_file( - 'wip: Try out a new thing', 'Just checking', 'wibble.c', - '''changes to wibble''') - target = self.repo.revparse_single('HEAD') - self.repo.reset(target.oid, pygit2.enums.ResetMode.HARD) - - # name = gitutil.get_branch(self.gitdir) - # upstream_name = gitutil.get_upstream(self.gitdir, name) - name, ser, version, _ = cser.prep_series(None) - - # We now have 4 commits numbered 0 (second~3) to 3 (the one we just - # added). Drop commit 1 (the 'serial' one) from the branch - cser._filter_commits(name, ser, 1) - svid = cser.get_ser_ver(ser.idnum, version).idnum - old_pcdict = cser.get_pcommit_dict(svid).values() - - expect = '''Syncing series 'second2' v2: mark False allow_unmarked True - 0 video: Some video improvements -- 1 serial: Add a serial driver - 1 bootm: Make it boot -+ 2 Just checking -''' - with terminal.capture() as (out, _): - self.run_args('series', '-n', 'scan', '-M', pwork=True) - self.assertEqual(expect + 'Dry run completed\n', out.getvalue()) - - new_pcdict = cser.get_pcommit_dict(svid).values() - self.assertEqual(list(old_pcdict), list(new_pcdict)) - - with terminal.capture() as (out, _): - self.run_args('series', 'scan', '-M', pwork=True) - self.assertEqual(expect, out.getvalue()) - - new_pcdict = cser.get_pcommit_dict(svid).values() - self.assertEqual(len(old_pcdict), len(new_pcdict)) - chk = list(new_pcdict) - self.assertNotEqual(list(old_pcdict), list(new_pcdict)) - self.assertEqual('video: Some video improvements', chk[0].subject) - self.assertEqual('bootm: Make it boot', chk[1].subject) - self.assertEqual('Just checking', chk[2].subject) - - def test_series_send(self): - """Test sending a series""" - cser, pwork = self.setup_second() - - # Create a third version - with terminal.capture(): - cser.increment('second') - series = patchstream.get_metadata_for_list('second3', self.gitdir, 3) - self.assertEqual('2:457 1:456', series.links) - self.assertEqual('3', series.version) - - with terminal.capture() as (out, err): - self.run_args('series', '-n', '-s', 'second3', 'send', - '--no-autolink', pwork=pwork) - self.assertIn('Send a total of 3 patches with a cover letter', - out.getvalue()) - self.assertIn( - 'video.c:1: warning: Missing or malformed SPDX-License-Identifier ' - 'tag in line 1', err.getvalue()) - self.assertIn( - '<patch>:19: warning: added, moved or deleted file(s), does ' - 'MAINTAINERS need updating?', err.getvalue()) - self.assertIn('bootm.c:1: check: Avoid CamelCase: <Fix>', - err.getvalue()) - self.assertIn( - 'Cc: Anatolij Gustschin <[email protected]>', out.getvalue()) - - self.assertTrue(os.path.exists(os.path.join( - self.tmpdir, '0001-video-Some-video-improvements.patch'))) - self.assertTrue(os.path.exists(os.path.join( - self.tmpdir, '0002-serial-Add-a-serial-driver.patch'))) - self.assertTrue(os.path.exists(os.path.join( - self.tmpdir, '0003-bootm-Make-it-boot.patch'))) - - def test_series_send_and_link(self): - """Test sending a series and then adding its link to the database""" - def h_sleep(time_s): - if cser.get_time() > 25: - self.autolink_extra = {'id': 500, - 'name': 'Series for my board', - 'version': 3} - cser.inc_fake_time(time_s) - - cser, pwork = self.setup_second() - - # Create a third version - with terminal.capture(): - cser.increment('second') - series = patchstream.get_metadata_for_list('second3', self.gitdir, 3) - self.assertEqual('2:457 1:456', series.links) - self.assertEqual('3', series.version) - - with terminal.capture(): - self.run_args('series', '-n', 'send', pwork=pwork) - - cser.set_fake_time(h_sleep) - with terminal.capture() as (out, _): - cser.link_auto(pwork, 'second3', 3, True, 50) - itr = iter(out.getvalue().splitlines()) - for i in range(7): - self.assertEqual( - "Possible matches for 'second' v3 desc 'Series for my board':", - next(itr), f'failed at i={i}') - self.assertEqual(' Link Version Description', next(itr)) - self.assertEqual(' 456 1 Series for my board', next(itr)) - self.assertEqual(' 457 2 Series for my board', next(itr)) - self.assertEqual('Sleeping for 5 seconds', next(itr)) - self.assertEqual('Link completed after 35 seconds', next(itr)) - self.assertRegex( - next(itr), 'Checking out upstream commit refs/heads/base: .*') - self.assertEqual( - "Processing 3 commits from branch 'second3'", next(itr)) - self.assertRegex( - next(itr), - f'- {HASH_RE} as {HASH_RE} ' - 'video: Some video improvements') - self.assertRegex( - next(itr), - f"- add links '3:500 2:457 1:456': {HASH_RE} as {HASH_RE} " - 'serial: Add a serial driver') - self.assertRegex( - next(itr), - f'- add v3: {HASH_RE} as {HASH_RE} ' - 'bootm: Make it boot') - self.assertRegex( - next(itr), - f'Updating branch second3 from {HASH_RE} to {HASH_RE}') - self.assertEqual( - "Setting link for series 'second' v3 to 500", next(itr)) - - def _check_status(self, out, has_comments, has_cover_comments): - """Check output from the status command - - Args: - itr (Iterator): Contains the output lines to check - """ - itr = iter(out.getvalue().splitlines()) - if has_cover_comments: - self.assertEqual('Cov The name of the cover letter', next(itr)) - self.assertEqual( - 'From: A user <[email protected]>: Sun 13 Apr 14:06:02 MDT 2025', - next(itr)) - self.assertEqual('some comment', next(itr)) - self.assertEqual('', next(itr)) - - self.assertEqual( - 'From: Ghenkis Khan <[email protected]>: Sun 13 Apr 13:06:02 ' - 'MDT 2025', - next(itr)) - self.assertEqual('another comment', next(itr)) - self.assertEqual('', next(itr)) - - self.assertEqual(' 1 video: Some video improvements', next(itr)) - self.assertEqual(' + Reviewed-by: Fred Bloggs <[email protected]>', - next(itr)) - if has_comments: - self.assertEqual( - 'Review: Fred Bloggs <[email protected]>', next(itr)) - self.assertEqual(' > This was my original patch', next(itr)) - self.assertEqual(' > which is being quoted', next(itr)) - self.assertEqual( - ' I like the approach here and I would love to see more ' - 'of it.', next(itr)) - self.assertEqual('', next(itr)) - - self.assertEqual(' 2 serial: Add a serial driver', next(itr)) - self.assertEqual(' 3 bootm: Make it boot', next(itr)) - self.assertEqual( - '1 new response available in patchwork (use -d to write them to ' - 'a new branch)', next(itr)) - - def test_series_status(self): - """Test getting the status of a series, including comments""" - cser, pwork = self.setup_second() - - # Use single threading for easy debugging, but the multithreaded - # version should produce the same output - with self.stage('status second2: single-threaded'): - with terminal.capture() as (out, _): - cser.status(pwork, 'second', 2, False) - self._check_status(out, False, False) - self.loop = asyncio.new_event_loop() - asyncio.set_event_loop(self.loop) - - with self.stage('status second2 (normal)'): - with terminal.capture() as (out2, _): - cser.status(pwork, 'second', 2, False) - self.assertEqual(out.getvalue(), out2.getvalue()) - self._check_status(out, False, False) - - with self.stage('with comments'): - with terminal.capture() as (out, _): - cser.status(pwork, 'second', 2, show_comments=True) - self._check_status(out, True, False) - - with self.stage('with comments and cover comments'): - with terminal.capture() as (out, _): - cser.status(pwork, 'second', 2, show_comments=True, - show_cover_comments=True) - self._check_status(out, True, True) - - def test_series_status_cmdline(self): - """Test getting the status of a series, including comments""" - cser, pwork = self.setup_second() - - with self.stage('status second2'): - with terminal.capture() as (out, _): - self.run_args('series', '-s', 'second', '-V', '2', 'status', - pwork=pwork) - self._check_status(out, False, False) - - with self.stage('status second2 (normal)'): - with terminal.capture() as (out, _): - cser.status(pwork, 'second', 2, show_comments=True) - self._check_status(out, True, False) - - with self.stage('with comments and cover comments'): - with terminal.capture() as (out, _): - cser.status(pwork, 'second', 2, show_comments=True, - show_cover_comments=True) - self._check_status(out, True, True) - - def test_series_no_subcmd(self): - """Test handling of things without a subcommand""" - parsers = cmdline.setup_parser() - parsers['series'].catch_error = True - with terminal.capture() as (out, _): - cmdline.parse_args(['series'], parsers=parsers) - self.assertIn('usage: patman series', out.getvalue()) - - parsers['patchwork'].catch_error = True - with terminal.capture() as (out, _): - cmdline.parse_args(['patchwork'], parsers=parsers) - self.assertIn('usage: patman patchwork', out.getvalue()) - - parsers['upstream'].catch_error = True - with terminal.capture() as (out, _): - cmdline.parse_args(['upstream'], parsers=parsers) - self.assertIn('usage: patman upstream', out.getvalue()) - - def check_series_rename(self): - """Check renaming a series""" - cser = self.get_cser() - with self.stage('setup'): - with terminal.capture() as (out, _): - cser.add('first', 'my name', allow_unmarked=True) - - # Remember the old series - old = cser.get_series_by_name('first') - - self.assertEqual('first', gitutil.get_branch(self.gitdir)) - with terminal.capture() as (out, _): - cser.increment('first') - self.assertEqual('first2', gitutil.get_branch(self.gitdir)) - - with terminal.capture() as (out, _): - cser.increment('first') - self.assertEqual('first3', gitutil.get_branch(self.gitdir)) - - # Do the dry run - with self.stage('rename - dry run'): - with terminal.capture() as (out, _): - yield cser - lines = out.getvalue().splitlines() - itr = iter(lines) - self.assertEqual("Renaming branch 'first' to 'newname'", next(itr)) - self.assertEqual( - "Renaming branch 'first2' to 'newname2'", next(itr)) - self.assertEqual( - "Renaming branch 'first3' to 'newname3'", next(itr)) - self.assertEqual("Renamed series 'first' to 'newname'", next(itr)) - self.assertEqual("Dry run completed", next(itr)) - self.assert_finished(itr) - - # Check nothing changed - self.assertEqual('first3', gitutil.get_branch(self.gitdir)) - sdict = cser.db.series_get_dict() - self.assertIn('first', sdict) - - # Now do it for real - with self.stage('rename - real'): - with terminal.capture() as (out2, _): - yield cser - lines2 = out2.getvalue().splitlines() - self.assertEqual(lines[:-1], lines2) - - self.assertEqual('newname3', gitutil.get_branch(self.gitdir)) - - # Check the series ID did not change - ser = cser.get_series_by_name('newname') - self.assertEqual(old.idnum, ser.idnum) - - yield None - - def test_series_rename(self): - """Test renaming of a series""" - cor = self.check_series_rename() - cser = next(cor) - - # Rename (dry run) - cser.rename('first', 'newname', dry_run=True) - cser = next(cor) - - # Rename (real) - cser.rename('first', 'newname') - self.assertFalse(next(cor)) - - def test_series_rename_cmdline(self): - """Test renaming of a series with the cmdline""" - cor = self.check_series_rename() - next(cor) - - # Rename (dry run) - self.run_args('series', '-n', '-s', 'first', 'rename', '-N', 'newname', - pwork=True) - next(cor) - - # Rename (real) - self.run_args('series', '-s', 'first', 'rename', '-N', 'newname', - pwork=True) - - self.assertFalse(next(cor)) - - def test_series_rename_bad(self): - """Test renaming when it is not allowed""" - cser = self.get_cser() - with terminal.capture(): - cser.add('first', 'my name', allow_unmarked=True) - cser.increment('first') - cser.increment('first') - - with self.assertRaises(ValueError) as exc: - cser.rename('first', 'first') - self.assertEqual("Cannot rename series 'first' to itself", - str(exc.exception)) - - with self.assertRaises(ValueError) as exc: - cser.rename('first2', 'newname') - self.assertEqual( - "Invalid series name 'first2': did you use the branch name?", - str(exc.exception)) - - with self.assertRaises(ValueError) as exc: - cser.rename('first', 'newname2') - self.assertEqual( - "Invalid series name 'newname2': did you use the branch name?", - str(exc.exception)) - - with self.assertRaises(ValueError) as exc: - cser.rename('first', 'second') - self.assertEqual("Cannot rename: branches exist: second", - str(exc.exception)) - - with terminal.capture(): - cser.add('second', 'another name', allow_unmarked=True) - cser.increment('second') - - with self.assertRaises(ValueError) as exc: - cser.rename('first', 'second') - self.assertEqual("Cannot rename: series 'second' already exists", - str(exc.exception)) - - # Rename second2 so that it gets in the way of the rename - gitutil.rename_branch('second2', 'newname2', self.gitdir) - with self.assertRaises(ValueError) as exc: - cser.rename('first', 'newname') - self.assertEqual("Cannot rename: branches exist: newname2", - str(exc.exception)) - - # Rename first3 and make sure it stops the rename - gitutil.rename_branch('first3', 'tempbranch', self.gitdir) - with self.assertRaises(ValueError) as exc: - cser.rename('first', 'newname') - self.assertEqual( - "Cannot rename: branches missing: first3: branches exist: " - 'newname2', str(exc.exception)) - - def test_version_change(self): - """Test changing a version of a series to a different version number""" - cser = self.get_cser() - - with self.stage('setup'): - with terminal.capture(): - cser.add('first', 'my description', allow_unmarked=True) - - with self.stage('non-existent version'): - # Check changing a non-existent version - with self.assertRaises(ValueError) as exc: - cser.version_change('first', 2, 3, dry_run=True) - self.assertEqual("Series 'first' does not have a version 2", - str(exc.exception)) - - with self.stage('new version missing'): - with self.assertRaises(ValueError) as exc: - cser.version_change('first', None, None, dry_run=True) - self.assertEqual("Please provide a new version number", - str(exc.exception)) - - # Change v1 to v2 (dry run) - with self.stage('v1 -> 2 dry run'): - with terminal.capture(): - self.assertTrue(gitutil.check_branch('first', self.gitdir)) - cser.version_change('first', 1, 3, dry_run=True) - self.assertTrue(gitutil.check_branch('first', self.gitdir)) - self.assertFalse(gitutil.check_branch('first3', self.gitdir)) - - # Check that nothing actually happened - series = patchstream.get_metadata('first', 0, 2, - git_dir=self.gitdir) - self.assertNotIn('version', series) - - svlist = cser.get_ser_ver_list() - self.assertEqual(1, len(svlist)) - item = svlist[0] - self.assertEqual(1, item.version) - - with self.stage('increment twice'): - # Increment so that we get first3 - with terminal.capture(): - cser.increment('first') - cser.increment('first') - - with self.stage('existing version'): - # Check changing to an existing version - with self.assertRaises(ValueError) as exc: - cser.version_change('first', 1, 3, dry_run=True) - self.assertEqual("Series 'first' already has a v3: 1 2 3", - str(exc.exception)) - - # Change v1 to v4 (for real) - with self.stage('v1 -> 4'): - with terminal.capture(): - self.assertTrue(gitutil.check_branch('first', self.gitdir)) - cser.version_change('first', 1, 4) - self.assertTrue(gitutil.check_branch('first', self.gitdir)) - self.assertTrue(gitutil.check_branch('first4', self.gitdir)) - - series = patchstream.get_metadata('first4', 0, 2, - git_dir=self.gitdir) - self.assertIn('version', series) - self.assertEqual('4', series.version) - - svdict = cser.get_ser_ver_dict() - self.assertEqual(3, len(svdict)) - item = svdict[item.idnum] - self.assertEqual(4, item.version) - - with self.stage('increment'): - # Now try to increment first again - with terminal.capture(): - cser.increment('first') - - ser = cser.get_series_by_name('first') - self.assertIn(5, cser._get_version_list(ser.idnum)) - - def test_version_change_cmdline(self): - """Check changing a version on the cmdline""" - self.get_cser() - with (mock.patch.object(cseries.Cseries, 'version_change', - return_value=None) as method): - self.run_args('series', '-s', 'first', 'version-change', - pwork=True) - method.assert_called_once_with('first', None, None, dry_run=False) - - with (mock.patch.object(cseries.Cseries, 'version_change', - return_value=None) as method): - self.run_args('series', '-s', 'first', 'version-change', - '--new-version', '3', pwork=True) - method.assert_called_once_with('first', None, 3, dry_run=False) diff --git a/tools/patman/test_settings.py b/tools/patman/test_settings.py deleted file mode 100644 index c117836de31..00000000000 --- a/tools/patman/test_settings.py +++ /dev/null @@ -1,67 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -# -# Copyright (c) 2022 Maxim Cournoyer <[email protected]> -# - -import argparse -import contextlib -import os -import sys -import tempfile - -from patman import settings -from u_boot_pylib import tools - - -def empty_git_repository(): - with tempfile.TemporaryDirectory() as tmpdir: - os.chdir(tmpdir) - tools.run('git', 'init', raise_on_error=True) - yield tmpdir - - -def cleared_command_line_args(): - old_value = sys.argv[:] - sys.argv = [sys.argv[0]] - try: - yield - finally: - sys.argv = old_value - - -def test_git_local_config(): - # Clearing the command line arguments is required, otherwise - # arguments passed to the test running such as in 'pytest -k - # filter' would be processed by _UpdateDefaults and fail. - with cleared_command_line_args(): - with empty_git_repository(): - with tempfile.NamedTemporaryFile() as global_config: - global_config.write(b'[settings]\n' - b'project=u-boot\n') - global_config.flush() - parser = argparse.ArgumentParser() - parser.add_argument('-p', '--project', default='unknown') - subparsers = parser.add_subparsers(dest='cmd') - send = subparsers.add_parser('send') - send.add_argument('--no-check', action='store_false', - dest='check_patch', default=True) - - # Test "global" config is used. - settings.Setup(parser, 'unknown', None, global_config.name) - args, _ = parser.parse_known_args([]) - assert args.project == 'u-boot' - send_args, _ = send.parse_known_args([]) - assert send_args.check_patch - - # Test local config can shadow it. - with open('.patman', 'w', buffering=1) as f: - f.write('[settings]\n' - 'project: guix-patches\n' - 'check_patch: False\n') - settings.Setup(parser, 'unknown', global_config.name) - args, _ = parser.parse_known_args([]) - assert args.project == 'guix-patches' - send_args, _ = send.parse_known_args([]) - assert not send_args.check_patch diff --git a/tools/rkcommon.c b/tools/rkcommon.c index cb2d30bfd57..b39777fc060 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -205,7 +205,7 @@ static int rkcommon_get_aligned_size(struct image_tool_params *params, /* * Pad to a 2KB alignment, as required for init/boot size by the ROM - * (see https://lists.denx.de/pipermail/u-boot/2017-May/293268.html) + * (see https://patch.msgid.link/CANbgqAQPw5Dxp7Qm_aZoL1nggg9Mm1SQoKvx=V5a8p-9+DTDNw@mail.gmail.com/) */ return ROUND(size, RK_SIZE_ALIGN); } @@ -328,7 +328,7 @@ static void rkcommon_set_header0(void *buf, struct image_tool_params *params) * to determine the size of the next-stage bootloader (e.g. U-Boot * proper), when used with the back-to-bootrom functionality. * - * see https://lists.denx.de/pipermail/u-boot/2017-May/293267.html + * see https://patch.msgid.link/CANbgqAQ5p-fE4T-Ye9UAMs-nRGU8AP_yxDf+5SbZbP8bxLa0dg@mail.gmail.com/ * for a more detailed explanation by Andy Yan */ if (spl_params.boot_file) diff --git a/tools/zynqmpbif.c b/tools/zynqmpbif.c index 82ce0ac1a52..50d76b03476 100644 --- a/tools/zynqmpbif.c +++ b/tools/zynqmpbif.c @@ -191,6 +191,7 @@ static char *parse_partition_owner(char *line, struct bif_entry *bf) } static const struct bif_flags bif_flags[] = { + { "init", BIF_FLAG_INIT }, { "fsbl_config", BIF_FLAG_FSBL_CONFIG }, { "trustzone", BIF_FLAG_TZ }, { "pmufw_image", BIF_FLAG_PMUFW_IMAGE }, @@ -316,6 +317,15 @@ static int bif_add_pmufw(struct bif_entry *bf, const char *data, size_t len) return 0; } +static int bif_add_reginit(struct bif_entry *init) +{ + /* User can pass in text file with init list */ + if (strlen(init->filename)) + zynqmpimage_parse_initparams(bif_output.header, init->filename); + + return 0; +} + static int bif_add_part(struct bif_entry *bf, const char *data, size_t len) { size_t parthdr_offset = 0; @@ -340,6 +350,8 @@ static int bif_add_part(struct bif_entry *bf, const char *data, size_t len) if (bf->flags & (1ULL << BIF_FLAG_PMUFW_IMAGE)) return bif_add_pmufw(bf, data, len); + else if (bf->flags & (1ULL << BIF_FLAG_INIT)) + return bif_add_reginit(bf); r = bif_add_blob(data, len, &bf->offset); if (r) diff --git a/tools/zynqmpimage.c b/tools/zynqmpimage.c index 4db9877127e..eb79c0696cc 100644 --- a/tools/zynqmpimage.c +++ b/tools/zynqmpimage.c @@ -400,8 +400,8 @@ static void zynqmpimage_pmufw(struct zynqmp_header *zynqhdr, fclose(fpmu); } -static void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr, - const char *filename) +void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr, + const char *filename) { FILE *fp; struct zynqmp_reginit reginit; diff --git a/tools/zynqmpimage.h b/tools/zynqmpimage.h index 7c47dc0763b..867fc5294a3 100644 --- a/tools/zynqmpimage.h +++ b/tools/zynqmpimage.h @@ -142,6 +142,8 @@ struct zynqmp_header { void zynqmpimage_default_header(struct zynqmp_header *ptr); void zynqmpimage_print_header(const void *ptr, struct image_tool_params *params); +void zynqmpimage_parse_initparams(struct zynqmp_header *zynqhdr, + const char *filename); static inline struct image_header_table * zynqmp_get_iht(const struct zynqmp_header *zynqhdr) |