diff options
| -rw-r--r-- | arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi | 10 | ||||
| -rw-r--r-- | arch/arm/mach-renesas/Kconfig.rcar5 | 1 | ||||
| -rw-r--r-- | board/renesas/common/gen5-cm33.c | 49 | ||||
| -rw-r--r-- | configs/r8a78000_ironhide_cm33_defconfig | 8 | ||||
| -rw-r--r-- | include/configs/rcar-gen5-common.h | 42 |
5 files changed, 108 insertions, 2 deletions
diff --git a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi index 2d4cdbac62a..356f633135d 100644 --- a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi +++ b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi @@ -65,10 +65,20 @@ syscon = <&ctl>; }; + ram@b8940000 { /* RT-VRAM */ + compatible = "renesas,r8a78000-rtvram"; + reg = <0 0xb8940000 0 0xf000>; + }; + scp@c1340000 { compatible = "renesas,r8a78000-rproc"; reg = <0 0xc1340000 0 0x80000>; }; + + ram@e9800000 { /* DBSC5 */ + compatible = "renesas,r8a78000-dbsc"; + reg = <0 0xe9800000 0 0x1000000>; + }; }; &cpg { diff --git a/arch/arm/mach-renesas/Kconfig.rcar5 b/arch/arm/mach-renesas/Kconfig.rcar5 index fcca3811241..33ad8522f07 100644 --- a/arch/arm/mach-renesas/Kconfig.rcar5 +++ b/arch/arm/mach-renesas/Kconfig.rcar5 @@ -2,6 +2,7 @@ if RCAR_GEN5 config RCAR_64_RSIP bool "Renesas ARM SoCs R-Car Gen5 (use Cortex-M33 RSIP)" + select LMB_ARCH_MEM_MAP select SKIP_RELOCATE_CODE select TMU_TIMER help diff --git a/board/renesas/common/gen5-cm33.c b/board/renesas/common/gen5-cm33.c index e07db9817f2..f06df824019 100644 --- a/board/renesas/common/gen5-cm33.c +++ b/board/renesas/common/gen5-cm33.c @@ -905,6 +905,24 @@ static void mfis_unprotect(void) } /** + * rsip_write_reg() - Write RSIP control register + * @reg: Register to write + * @val: Value to set in the register + */ +static void rsip_write_reg(const u32 reg, const int val) +{ + for (;;) { + writel(RSIP_CTL_PROT0PCMD_WREN, RSIP_CTL_PROT0PCMD); + writel(val, reg); + writel(~val, reg); + writel(val, reg); + + if (readl(RSIP_CTL_PROT0PS) != RSIP_CTL_PROT0PS_ERR) + break; + } +} + +/** * rsip_irq_setup() - Configure RSIP interrupts */ static void rsip_irq_setup(void) @@ -1353,6 +1371,26 @@ int mach_cpu_init(void) return 0; } +int board_early_init_r(void) +{ + u32 remaptmp = readl(RSIP_CTL_ESICREMAP0); + struct udevice *dev; + int ret; + + /* Remap DDR PHY during DRAM init. */ + rsip_write_reg(RSIP_CTL_ESICREMAP0, 0xe0000000); + + /* Start DBSC5 */ + ret = uclass_get_device_by_name(UCLASS_NOP, "ram@e9800000", &dev); + if (ret) + printf("DBSC5 init failed: %d\n", ret); + + /* Restore remapping. */ + rsip_write_reg(RSIP_CTL_ESICREMAP0, remaptmp); + + return 0; +} + /** * board_debug_uart_init() - Initialize all HSCIF */ @@ -1407,3 +1445,14 @@ void __weak reset_cpu(void) writel(RST_KCPROT_DIS, RST_RESKCPROT0); writel(0x1, RST_SWSRES1A); } + +/** + * lmb_arch_add_memory() - Add memory to LMB + * + * Add the window to a subset of 32bit DRAM are into LMB, + * to make it possible to TFTP into it. + */ +void lmb_arch_add_memory(void) +{ + lmb_add(0x60000000, 0x40000000); +} diff --git a/configs/r8a78000_ironhide_cm33_defconfig b/configs/r8a78000_ironhide_cm33_defconfig index dda096634b5..7ea3ae993ba 100644 --- a/configs/r8a78000_ironhide_cm33_defconfig +++ b/configs/r8a78000_ironhide_cm33_defconfig @@ -17,9 +17,14 @@ CONFIG_SKIP_RELOCATE_CODE_DATA_OFFSET=0xa0000000 CONFIG_ARCH_CPU_INIT=y CONFIG_BAUDRATE=1843200 -CONFIG_BOOTCOMMAND="" +CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_BOOTCOMMAND="run rsip_ipl_boot_ca0" CONFIG_BOUNCE_BUFFER=y CONFIG_CMD_IMI=y +CONFIG_CMD_PSTORE=y +CONFIG_CMD_PSTORE_MEM_ADDR=0x80000000 +CONFIG_CMD_PSTORE_RECORD_SIZE=0x400 +CONFIG_CMD_PSTORE_CONSOLE_SIZE=0x8000 CONFIG_CMD_REMOTEPROC=y CONFIG_CMD_UFS=y CONFIG_DM_DMA=y @@ -37,6 +42,7 @@ CONFIG_PHY_R8A78000_MP_PHY=y CONFIG_PHY_TI_DP83869=y CONFIG_POWER_DOMAIN=y CONFIG_RAM=y +CONFIG_RAM_RENESAS_DBSC5=y CONFIG_REMOTEPROC_RENESAS_RSIP=y CONFIG_RENESAS_ETHER_SWITCH=y CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h index 5ff2a76fc05..a0c05521c85 100644 --- a/include/configs/rcar-gen5-common.h +++ b/include/configs/rcar-gen5-common.h @@ -26,10 +26,50 @@ #if defined(CONFIG_RCAR_64_RSIP) #define CFG_SYS_TIMER_COUNTER (TMU_BASE + 0xc) /* TCNT0 */ #define CFG_SYS_TIMER_RATE (133333333 / 4) -#endif /* Environment setting */ +#define CFG_EXTRA_ENV_SETTINGS \ + "rsip_ipl_params_base=0x8c100000\0" \ + "rsip_ipl_params_optee=0x8c100088\0" \ + "rsip_ipl_params_uboot=0x8c100030\0" \ + "rsip_ipl_optee_ep=0x8c400000\0" \ + "rsip_ipl_tfa_ep=0x8c200000\0" \ + "rsip_ipl_uboot_ep=0x8e300000\0" \ + "rsip_ipl_params_write=" \ + "base ${rsip_ipl_params_base} ; " \ + "mw 0x00 0 0x9e ; " /* Clear the area */ \ + "mw 0x00 0x00300103 ; " /* type, version, size */ \ + "mw 0x20 0x${rsip_ipl_params_uboot} ; " /* U-Boot descriptor */ \ + "" \ + "base ${rsip_ipl_params_uboot} ; " \ + "mw 0x00 0x00580101 ; " /* type, version, size */ \ + "mw 0x04 0x00000001 ; " /* attr */ \ + "mw 0x08 ${rsip_ipl_uboot_ep} ; " /* U-Boot entry point */ \ + "mw 0x10 0x000003c5 ; " /* SPSR */ \ + "" \ + "base ${rsip_ipl_params_optee} ; " \ + "mw 0x00 0x00580201 ; " /* type, version, size */ \ + "mw 0x04 0x00000008 ; " /* attr */ \ + "mw 0x08 ${rsip_ipl_optee_ep} ; " /* OPTEE-OS entry point */ \ + "mw 0x10 0x000003c5 ; " /* SPSR */ \ + "" \ + "base 0\0" \ + "rsip_ipl_boot_ca0=" /* Start TFA BL31, OPTEE-OS, U-Boot on Cortex-A720AE core 0 */ \ + "scsi scan && " /* Scan for UFS devices */ \ + "rproc init && " /* Start remoteproc */ \ + "rproc load 0 0x344c0000 0x60000 && " /* Load SCP from HF */ \ + "rproc start 0 && " /* Start SCP */ \ + "scsi read ${rsip_ipl_uboot_ep} 0x7200 0x100 && " /* Load U-Boot from UFS */ \ + "scsi read ${rsip_ipl_optee_ep} 0x5200 0x200 && " /* Load OPTEE-OS from UFS */ \ + "scsi read ${rsip_ipl_tfa_ep} 0x5000 0x40 && " /* Load TFA BL31 from UFS */ \ + "run rsip_ipl_params_write && " /* Write entry point descriptors */ \ + "rproc load 13 ${rsip_ipl_tfa_ep} 4 && " /* Set up Cortex-A720AE Core 0 */ \ + "rproc start 13\0" /* Start Cortex-A720AE Core 0 */ + +#else +/* Environment setting */ #define CFG_EXTRA_ENV_SETTINGS \ "bootm_size=0x10000000\0" +#endif #endif /* __RCAR_GEN5_COMMON_H */ |