diff options
| -rw-r--r-- | board/phytec/phycore_am62x/phycore-am62x.c | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index 35e1bb96b8d..9f6bc736cbb 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -47,7 +47,12 @@ static u8 phytec_get_am62_ddr_size_default(void) int dram_init(void) { - u8 ram_size = phytec_get_am62_ddr_size_default(); + u8 ram_size; + + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_mem_size_base(); + + ram_size = phytec_get_am62_ddr_size_default(); /* * HACK: ddrss driver support 2GB RAM by default @@ -92,6 +97,9 @@ int dram_init_banksize(void) { u8 ram_size; + if (!IS_ENABLED(CONFIG_CPU_V7R)) + return fdtdec_setup_memory_banksize(); + ram_size = phytec_get_am62_ddr_size_default(); switch (ram_size) { case EEPROM_RAM_SIZE_1GB: @@ -174,6 +182,26 @@ int do_board_detect(void) } #endif +#if IS_ENABLED(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS); +} +#endif + #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CTRLMMR_USB1_PHY_CTRL 0x43004018 #define CORE_VOLTAGE 0x80000000 |