diff options
| -rw-r--r-- | arch/arm/dts/imx6q-ba16.dtsi | 11 | ||||
| -rw-r--r-- | board/ge/bx50v3/bx50v3.c | 35 |
2 files changed, 23 insertions, 23 deletions
diff --git a/arch/arm/dts/imx6q-ba16.dtsi b/arch/arm/dts/imx6q-ba16.dtsi index 7d8f61f2fd7..9da2bb6e869 100644 --- a/arch/arm/dts/imx6q-ba16.dtsi +++ b/arch/arm/dts/imx6q-ba16.dtsi @@ -174,6 +174,17 @@ pinctrl-0 = <&pinctrl_enet>; phy-mode = "rgmii-id"; status = "okay"; + phy-handle = <&phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@4 { + reg = <4>; + qca,clk-out-frequency = <125000000>; + }; + }; }; &hdmi { diff --git a/board/ge/bx50v3/bx50v3.c b/board/ge/bx50v3/bx50v3.c index a3ae037a82e..3ea9425fd1e 100644 --- a/board/ge/bx50v3/bx50v3.c +++ b/board/ge/bx50v3/bx50v3.c @@ -47,6 +47,10 @@ DECLARE_GLOBAL_DATA_PTR; #define VPD_PRODUCT_B650 2 #define VPD_PRODUCT_B450 3 +#define AR8033_DBG_REG_ADDR 0x1d +#define AR8033_DBG_REG_DATA 0x1e +#define AR8033_SERDES_REG 0x5 + static int productid; /* Default to generic. */ static struct vpd_cache vpd; @@ -61,31 +65,16 @@ int dram_init(void) return 0; } -static int mx6_rgmii_rework(struct phy_device *phydev) -{ - /* Configure AR8033 to ouput a 125MHz clk from CLK_25M */ - /* set device address 0x7 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - /* offset 0x8016: CLK_25M Clock Select */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - /* enable register write, no post increment, address 0x7 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - /* set to 125 MHz from local PLL source */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18); - - /* rgmii tx clock delay enable */ - /* set debug port address: SerDes Test and System Mode Control */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - /* enable rgmii tx clock delay */ - /* set the reserved bits to avoid board specific voltage peak issue*/ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); - - return 0; -} - int board_phy_config(struct phy_device *phydev) { - mx6_rgmii_rework(phydev); + /* + * Set reserved bits to avoid board specific voltage peak issue. The + * value is a magic number provided directly by Qualcomm. Note, that + * PHY driver will take control of BIT(8) in this register to control + * TX clock delay, so we do not initialize that bit here. + */ + phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_ADDR, AR8033_SERDES_REG); + phy_write(phydev, MDIO_DEVAD_NONE, AR8033_DBG_REG_DATA, 0x3c47); if (phydev->drv->config) phydev->drv->config(phydev); |